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Differential D39782

[X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
ClosedPublic

Authored by craig.topper on Nov 7 2017, 11:31 PM.

Details

Reviewers
erichkeane
echristo
asbirlea
Commits
rGc77d00e327d4: [X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
rL317900: [X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
Summary

I want to leverage this to clean up some of the code in clang. This will allow us to simplify D39521 which was trying to do some of the same.

If we accurately keep the code in Host.cpp synced with new CPUs added to compile-rt/libgcc we should be able to use this file as a proxy for what's implemented in the libraries.

The entries for the CPUs recognized by the libraries use separate macros that define additional parameters like the name for builtin_cpu_is and an alias string for the couple cases where builtin_cpu_is accepts two different names.

All of the macros contain an ARCHNAME that is usually the same as the __builtin_cpu_is string, but sometimes isn't. This represents the name recognized by X86.td and -march.

I'm following the precedent set by ARM and AArch64 and adding this information to lib/Support/TargetParser.cpp

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Nov 7 2017, 11:31 PM
Herald added subscribers: kristof.beyls, aemerson. · View Herald TranscriptNov 7 2017, 11:31 PM
craig.topper updated this revision to Diff 122034.Nov 7 2017, 11:34 PM

Fix some typos

craig.topper added reviewers: erichkeane, echristo, asbirlea.Nov 7 2017, 11:35 PM
craig.topper added a subscriber: llvm-commits.
echristo accepted this revision.Nov 9 2017, 10:53 PM

Seems to be a step in the right direction anyhow.

This revision is now accepted and ready to land.Nov 9 2017, 10:53 PM
Closed by commit rL317900: [X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp (authored by ctopper). · Explain WhyNov 10 2017, 9:11 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
Support/
35 lines
105 lines
lib/
Support/
372 lines

Diff 122456

llvm/trunk/include/llvm/Support/TargetParser.h

Show First 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
unsigned parseArchExt(StringRef ArchExt); unsigned parseArchExt(StringRef ArchExt);
ArchKind parseCPUArch(StringRef CPU); ArchKind parseCPUArch(StringRef CPU);
ARM::ISAKind parseArchISA(StringRef Arch); ARM::ISAKind parseArchISA(StringRef Arch);
ARM::EndianKind parseArchEndian(StringRef Arch); ARM::EndianKind parseArchEndian(StringRef Arch);
ARM::ProfileKind parseArchProfile(StringRef Arch); ARM::ProfileKind parseArchProfile(StringRef Arch);
unsigned parseArchVersion(StringRef Arch); unsigned parseArchVersion(StringRef Arch);
} // namespace AArch64 } // namespace AArch64
namespace X86 {
// This should be kept in sync with libcc/compiler-rt as its included by clang
// as a proxy for what's in libgcc/compiler-rt.
enum ProcessorVendors : unsigned {
VENDOR_DUMMY,
#define X86_VENDOR(ENUM, STRING) \
ENUM,
#include "llvm/Support/X86TargetParser.def"
VENDOR_OTHER
};
// This should be kept in sync with libcc/compiler-rt as its included by clang
// as a proxy for what's in libgcc/compiler-rt.
enum ProcessorTypes : unsigned {
CPU_TYPE_DUMMY,
#define X86_CPU_TYPE(ARCHNAME, ENUM) \
ENUM,
#include "llvm/Support/X86TargetParser.def"
CPU_TYPE_MAX
};
// This should be kept in sync with libcc/compiler-rt as its included by clang
// as a proxy for what's in libgcc/compiler-rt.
enum ProcessorSubtypes : unsigned {
CPU_SUBTYPE_DUMMY,
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
ENUM,
#include "llvm/Support/X86TargetParser.def"
CPU_SUBTYPE_MAX
};
} // namespace X86
} // namespace llvm } // namespace llvm
#endif #endif

llvm/trunk/include/llvm/Support/X86TargetParser.def

//===- X86TargetParser.def - X86 target parsing defines ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides defines to build up the X86 target parser's logic.
//
//===----------------------------------------------------------------------===//
// NOTE: NO INCLUDE GUARD DESIRED!
#ifndef X86_VENDOR
#define X86_VENDOR(STRING, ENUM)
#endif
X86_VENDOR(VENDOR_INTEL, "intel")
X86_VENDOR(VENDOR_AMD, "amd")
#undef X86_VENDOR
// This macro is used to implement CPU types that have an alias. As of now
// there is only ever one alias.
#ifndef X86_CPU_TYPE_COMPAT_WITH_ALIAS
#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR)
#endif
// This macro is used for cpu types present in compiler-rt/libgcc.
#ifndef X86_CPU_TYPE_COMPAT
#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) X86_CPU_TYPE(ARCHNAME, ENUM)
#endif
#ifndef X86_CPU_TYPE
#define X86_CPU_TYPE(ARCHNAME, ENUM)
#endif
X86_CPU_TYPE_COMPAT_WITH_ALIAS("bonnell", INTEL_BONNELL, "bonnell", "atom")
X86_CPU_TYPE_COMPAT ("core2", INTEL_CORE2, "core2")
X86_CPU_TYPE_COMPAT ("nehalem", INTEL_COREI7, "corei7")
X86_CPU_TYPE_COMPAT_WITH_ALIAS("amdfam10", AMDFAM10H, "amdfam10h", "amdfam10")
X86_CPU_TYPE_COMPAT_WITH_ALIAS("bdver1", AMDFAM15H, "amdfam15h", "amdfam15")
X86_CPU_TYPE_COMPAT_WITH_ALIAS("silvermont", INTEL_SILVERMONT, "silvermont", "slm")
X86_CPU_TYPE_COMPAT ("knl", INTEL_KNL, "knl")
X86_CPU_TYPE_COMPAT ("btver1", AMD_BTVER1, "btver1")
X86_CPU_TYPE_COMPAT ("btver2", AMD_BTVER2, "btver2")
X86_CPU_TYPE_COMPAT ("znver1", AMDFAM17H, "amdfam17h")
X86_CPU_TYPE_COMPAT ("knm", INTEL_KNM, "knm")
// Entries below this are not in libgcc/compiler-rt.
X86_CPU_TYPE ("i386", INTEL_i386)
X86_CPU_TYPE ("i486", INTEL_i486)
X86_CPU_TYPE ("pentium", INTEL_PENTIUM)
X86_CPU_TYPE ("pentium-mmx", INTEL_PENTIUM_MMX)
X86_CPU_TYPE ("pentium-pro", INTEL_PENTIUM_PRO)
X86_CPU_TYPE ("pentium2", INTEL_PENTIUM_II)
X86_CPU_TYPE ("pentium3", INTEL_PENTIUM_III)
X86_CPU_TYPE ("pentium4", INTEL_PENTIUM_IV)
X86_CPU_TYPE ("pentium-m", INTEL_PENTIUM_M)
X86_CPU_TYPE ("yonah", INTEL_CORE_DUO)
X86_CPU_TYPE ("nocona", INTEL_NOCONA)
X86_CPU_TYPE ("prescott", INTEL_PRESCOTT)
X86_CPU_TYPE ("i486", AMD_i486)
X86_CPU_TYPE ("pentium", AMDPENTIUM)
X86_CPU_TYPE ("athlon", AMD_ATHLON)
X86_CPU_TYPE ("athlon-xp", AMD_ATHLON_XP)
X86_CPU_TYPE ("k8", AMD_K8)
X86_CPU_TYPE ("k8-sse3", AMD_K8SSE3)
X86_CPU_TYPE ("goldmont", INTEL_GOLDMONT)
#undef X86_CPU_TYPE_COMPAT_WITH_ALIAS
#undef X86_CPU_TYPE_COMPAT
#undef X86_CPU_TYPE
// This macro is used for cpu subtypes present in compiler-rt/libgcc.
#ifndef X86_CPU_SUBTYPE_COMPAT
#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) X86_CPU_SUBTYPE(ARCHNAME, ENUM)
#endif
#ifndef X86_CPU_SUBTYPE
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM)
#endif
X86_CPU_SUBTYPE_COMPAT("nehalem", INTEL_COREI7_NEHALEM, "nehalem")
X86_CPU_SUBTYPE_COMPAT("westmere", INTEL_COREI7_WESTMERE, "westmere")
X86_CPU_SUBTYPE_COMPAT("sandybridge", INTEL_COREI7_SANDYBRIDGE, "sandybridge")
X86_CPU_SUBTYPE_COMPAT("amdfam10", AMDFAM10H_BARCELONA, "barcelona")
X86_CPU_SUBTYPE_COMPAT("amdfam10", AMDFAM10H_SHANGHAI, "shanghai")
X86_CPU_SUBTYPE_COMPAT("amdfam10", AMDFAM10H_ISTANBUL, "istanbul")
X86_CPU_SUBTYPE_COMPAT("bdver1", AMDFAM15H_BDVER1, "bdver1")
X86_CPU_SUBTYPE_COMPAT("bdver2", AMDFAM15H_BDVER2, "bdver2")
X86_CPU_SUBTYPE_COMPAT("bdver3", AMDFAM15H_BDVER3, "bdver3")
X86_CPU_SUBTYPE_COMPAT("bdver4", AMDFAM15H_BDVER4, "bdver4")
X86_CPU_SUBTYPE_COMPAT("znver1", AMDFAM17H_ZNVER1, "znver1")
X86_CPU_SUBTYPE_COMPAT("ivybridge", INTEL_COREI7_IVYBRIDGE, "ivybridge")
X86_CPU_SUBTYPE_COMPAT("haswell", INTEL_COREI7_HASWELL, "haswell")
X86_CPU_SUBTYPE_COMPAT("broadwell", INTEL_COREI7_BROADWELL, "broadwell")
X86_CPU_SUBTYPE_COMPAT("skylake", INTEL_COREI7_SKYLAKE, "skylake")
X86_CPU_SUBTYPE_COMPAT("skylake-avx512", INTEL_COREI7_SKYLAKE_AVX512, "skylake-avx512")
// Entries below this are not in libgcc/compiler-rt.
X86_CPU_SUBTYPE ("core2", INTEL_CORE2_65)
X86_CPU_SUBTYPE ("penryn", INTEL_CORE2_45)
X86_CPU_SUBTYPE ("k6", AMDPENTIUM_K6)
X86_CPU_SUBTYPE ("k6-2", AMDPENTIUM_K62)
X86_CPU_SUBTYPE ("k6-3", AMDPENTIUM_K63)
X86_CPU_SUBTYPE ("geode", AMDPENTIUM_GEODE)
#undef X86_CPU_SUBTYPE_COMPAT
#undef X86_CPU_SUBTYPE

llvm/trunk/lib/Support/Host.cpp

//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the operating system Host concept. // This file implements the operating system Host concept.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/Support/Host.h" #include "llvm/Support/Host.h"
#include "llvm/Support/TargetParser.h"
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h" #include "llvm/ADT/Triple.h"
#include "llvm/Config/config.h" #include "llvm/Config/config.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/FileSystem.h" #include "llvm/Support/FileSystem.h"
▲ Show 20 Lines • Show All 293 Lines • ▼ Show 20 Lines
#if defined(__i386__) || defined(_M_IX86) || \ #if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64) defined(__x86_64__) || defined(_M_X64)
enum VendorSignatures { enum VendorSignatures {
SIG_INTEL = 0x756e6547 /* Genu */, SIG_INTEL = 0x756e6547 /* Genu */,
SIG_AMD = 0x68747541 /* Auth */ SIG_AMD = 0x68747541 /* Auth */
}; };
enum ProcessorVendors {
VENDOR_INTEL = 1,
VENDOR_AMD,
VENDOR_OTHER,
VENDOR_MAX
};
enum ProcessorTypes {
INTEL_BONNELL = 1,
INTEL_CORE2,
INTEL_COREI7,
AMDFAM10H,
AMDFAM15H,
INTEL_SILVERMONT,
INTEL_KNL,
AMD_BTVER1,
AMD_BTVER2,
AMDFAM17H,
INTEL_KNM,
// Entries below this are not in libgcc/compiler-rt.
INTEL_i386,
INTEL_i486,
INTEL_PENTIUM,
INTEL_PENTIUM_MMX,
INTEL_PENTIUM_PRO,
INTEL_PENTIUM_II,
INTEL_PENTIUM_III,
INTEL_PENTIUM_IV,
INTEL_PENTIUM_M,
INTEL_CORE_DUO,
INTEL_NOCONA,
INTEL_PRESCOTT,
AMD_i486,
AMDPENTIUM,
AMD_ATHLON,
AMD_ATHLON_XP,
AMD_K8,
AMD_K8SSE3,
INTEL_GOLDMONT,
CPU_TYPE_MAX
};
enum ProcessorSubtypes {
INTEL_COREI7_NEHALEM = 1,
INTEL_COREI7_WESTMERE,
INTEL_COREI7_SANDYBRIDGE,
AMDFAM10H_BARCELONA,
AMDFAM10H_SHANGHAI,
AMDFAM10H_ISTANBUL,
AMDFAM15H_BDVER1,
AMDFAM15H_BDVER2,
AMDFAM15H_BDVER3,
AMDFAM15H_BDVER4,
AMDFAM17H_ZNVER1,
INTEL_COREI7_IVYBRIDGE,
INTEL_COREI7_HASWELL,
INTEL_COREI7_BROADWELL,
INTEL_COREI7_SKYLAKE,
INTEL_COREI7_SKYLAKE_AVX512,
// Entries below this are not in libgcc/compiler-rt.
INTEL_CORE2_65,
INTEL_CORE2_45,
AMDPENTIUM_K6,
AMDPENTIUM_K62,
AMDPENTIUM_K63,
AMDPENTIUM_GEODE,
CPU_SUBTYPE_MAX
};
enum ProcessorFeatures { enum ProcessorFeatures {
FEATURE_CMOV = 0, FEATURE_CMOV = 0,
FEATURE_MMX, FEATURE_MMX,
FEATURE_POPCNT, FEATURE_POPCNT,
FEATURE_SSE, FEATURE_SSE,
FEATURE_SSE2, FEATURE_SSE2,
FEATURE_SSE3, FEATURE_SSE3,
FEATURE_SSSE3, FEATURE_SSSE3,
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines
getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
unsigned Brand_id, unsigned Features, unsigned Brand_id, unsigned Features,
unsigned Features2, unsigned *Type, unsigned Features2, unsigned *Type,
unsigned *Subtype) { unsigned *Subtype) {
if (Brand_id != 0) if (Brand_id != 0)
return; return;
switch (Family) { switch (Family) {
case 3: case 3:
*Type = INTEL_i386; *Type = X86::INTEL_i386;
break; break;
case 4: case 4:
*Type = INTEL_i486; *Type = X86::INTEL_i486;
break; break;
case 5: case 5:
if (Features & (1 << FEATURE_MMX)) { if (Features & (1 << FEATURE_MMX)) {
*Type = INTEL_PENTIUM_MMX; *Type = X86::INTEL_PENTIUM_MMX;
break; break;
} }
*Type = INTEL_PENTIUM; *Type = X86::INTEL_PENTIUM;
break; break;
case 6: case 6:
switch (Model) { switch (Model) {
case 0x01: // Pentium Pro processor case 0x01: // Pentium Pro processor
*Type = INTEL_PENTIUM_PRO; *Type = X86::INTEL_PENTIUM_PRO;
break; break;
case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
// model 03 // model 03
case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
// model 05, and Intel Celeron processor, model 05 // model 05, and Intel Celeron processor, model 05
case 0x06: // Celeron processor, model 06 case 0x06: // Celeron processor, model 06
*Type = INTEL_PENTIUM_II; *Type = X86::INTEL_PENTIUM_II;
break; break;
case 0x07: // Pentium III processor, model 07, and Pentium III Xeon case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
// processor, model 07 // processor, model 07
case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
// model 08, and Celeron processor, model 08 // model 08, and Celeron processor, model 08
case 0x0a: // Pentium III Xeon processor, model 0Ah case 0x0a: // Pentium III Xeon processor, model 0Ah
case 0x0b: // Pentium III processor, model 0Bh case 0x0b: // Pentium III processor, model 0Bh
*Type = INTEL_PENTIUM_III; *Type = X86::INTEL_PENTIUM_III;
break; break;
case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
// 0Dh. All processors are manufactured using the 90 nm process. // 0Dh. All processors are manufactured using the 90 nm process.
case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
// Integrated Processor with Intel QuickAssist Technology // Integrated Processor with Intel QuickAssist Technology
*Type = INTEL_PENTIUM_M; *Type = X86::INTEL_PENTIUM_M;
break; break;
case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
// 0Eh. All processors are manufactured using the 65 nm process. // 0Eh. All processors are manufactured using the 65 nm process.
*Type = INTEL_CORE_DUO; *Type = X86::INTEL_CORE_DUO;
break; // yonah break; // yonah
case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
// processor, Intel Core 2 Quad processor, Intel Core 2 Quad // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
// mobile processor, Intel Core 2 Extreme processor, Intel // mobile processor, Intel Core 2 Extreme processor, Intel
// Pentium Dual-Core processor, Intel Xeon processor, model // Pentium Dual-Core processor, Intel Xeon processor, model
// 0Fh. All processors are manufactured using the 65 nm process. // 0Fh. All processors are manufactured using the 65 nm process.
case 0x16: // Intel Celeron processor model 16h. All processors are case 0x16: // Intel Celeron processor model 16h. All processors are
// manufactured using the 65 nm process // manufactured using the 65 nm process
*Type = INTEL_CORE2; // "core2" *Type = X86::INTEL_CORE2; // "core2"
*Subtype = INTEL_CORE2_65; *Subtype = X86::INTEL_CORE2_65;
break; break;
case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
// 17h. All processors are manufactured using the 45 nm process. // 17h. All processors are manufactured using the 45 nm process.
// //
// 45nm: Penryn , Wolfdale, Yorkfield (XE) // 45nm: Penryn , Wolfdale, Yorkfield (XE)
case 0x1d: // Intel Xeon processor MP. All processors are manufactured using case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
// the 45 nm process. // the 45 nm process.
*Type = INTEL_CORE2; // "penryn" *Type = X86::INTEL_CORE2; // "penryn"
*Subtype = INTEL_CORE2_45; *Subtype = X86::INTEL_CORE2_45;
break; break;
case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
// processors are manufactured using the 45 nm process. // processors are manufactured using the 45 nm process.
case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
// As found in a Summer 2010 model iMac. // As found in a Summer 2010 model iMac.
case 0x1f: case 0x1f:
case 0x2e: // Nehalem EX case 0x2e: // Nehalem EX
*Type = INTEL_COREI7; // "nehalem" *Type = X86::INTEL_COREI7; // "nehalem"
*Subtype = INTEL_COREI7_NEHALEM; *Subtype = X86::INTEL_COREI7_NEHALEM;
break; break;
case 0x25: // Intel Core i7, laptop version. case 0x25: // Intel Core i7, laptop version.
case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
// processors are manufactured using the 32 nm process. // processors are manufactured using the 32 nm process.
case 0x2f: // Westmere EX case 0x2f: // Westmere EX
*Type = INTEL_COREI7; // "westmere" *Type = X86::INTEL_COREI7; // "westmere"
*Subtype = INTEL_COREI7_WESTMERE; *Subtype = X86::INTEL_COREI7_WESTMERE;
break; break;
case 0x2a: // Intel Core i7 processor. All processors are manufactured case 0x2a: // Intel Core i7 processor. All processors are manufactured
// using the 32 nm process. // using the 32 nm process.
case 0x2d: case 0x2d:
*Type = INTEL_COREI7; //"sandybridge" *Type = X86::INTEL_COREI7; //"sandybridge"
*Subtype = INTEL_COREI7_SANDYBRIDGE; *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
break; break;
case 0x3a: case 0x3a:
case 0x3e: // Ivy Bridge EP case 0x3e: // Ivy Bridge EP
*Type = INTEL_COREI7; // "ivybridge" *Type = X86::INTEL_COREI7; // "ivybridge"
*Subtype = INTEL_COREI7_IVYBRIDGE; *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
break; break;
// Haswell: // Haswell:
case 0x3c: case 0x3c:
case 0x3f: case 0x3f:
case 0x45: case 0x45:
case 0x46: case 0x46:
*Type = INTEL_COREI7; // "haswell" *Type = X86::INTEL_COREI7; // "haswell"
*Subtype = INTEL_COREI7_HASWELL; *Subtype = X86::INTEL_COREI7_HASWELL;
break; break;
// Broadwell: // Broadwell:
case 0x3d: case 0x3d:
case 0x47: case 0x47:
case 0x4f: case 0x4f:
case 0x56: case 0x56:
*Type = INTEL_COREI7; // "broadwell" *Type = X86::INTEL_COREI7; // "broadwell"
*Subtype = INTEL_COREI7_BROADWELL; *Subtype = X86::INTEL_COREI7_BROADWELL;
break; break;
// Skylake: // Skylake:
case 0x4e: // Skylake mobile case 0x4e: // Skylake mobile
case 0x5e: // Skylake desktop case 0x5e: // Skylake desktop
case 0x8e: // Kaby Lake mobile case 0x8e: // Kaby Lake mobile
case 0x9e: // Kaby Lake desktop case 0x9e: // Kaby Lake desktop
*Type = INTEL_COREI7; // "skylake" *Type = X86::INTEL_COREI7; // "skylake"
*Subtype = INTEL_COREI7_SKYLAKE; *Subtype = X86::INTEL_COREI7_SKYLAKE;
break; break;
// Skylake Xeon: // Skylake Xeon:
case 0x55: case 0x55:
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
break; break;
case 0x1c: // Most 45 nm Intel Atom processors case 0x1c: // Most 45 nm Intel Atom processors
case 0x26: // 45 nm Atom Lincroft case 0x26: // 45 nm Atom Lincroft
case 0x27: // 32 nm Atom Medfield case 0x27: // 32 nm Atom Medfield
case 0x35: // 32 nm Atom Midview case 0x35: // 32 nm Atom Midview
case 0x36: // 32 nm Atom Midview case 0x36: // 32 nm Atom Midview
*Type = INTEL_BONNELL; *Type = X86::INTEL_BONNELL;
break; // "bonnell" break; // "bonnell"
// Atom Silvermont codes from the Intel software optimization guide. // Atom Silvermont codes from the Intel software optimization guide.
case 0x37: case 0x37:
case 0x4a: case 0x4a:
case 0x4d: case 0x4d:
case 0x5a: case 0x5a:
case 0x5d: case 0x5d:
case 0x4c: // really airmont case 0x4c: // really airmont
*Type = INTEL_SILVERMONT; *Type = X86::INTEL_SILVERMONT;
break; // "silvermont" break; // "silvermont"
// Goldmont: // Goldmont:
case 0x5c: case 0x5c:
case 0x5f: case 0x5f:
*Type = INTEL_GOLDMONT; *Type = X86::INTEL_GOLDMONT;
break; // "goldmont" break; // "goldmont"
case 0x57: case 0x57:
*Type = INTEL_KNL; // knl *Type = X86::INTEL_KNL; // knl
break; break;
case 0x85: case 0x85:
*Type = INTEL_KNM; // knm *Type = X86::INTEL_KNM; // knm
break; break;
default: // Unknown family 6 CPU, try to guess. default: // Unknown family 6 CPU, try to guess.
if (Features & (1 << FEATURE_AVX512F)) { if (Features & (1 << FEATURE_AVX512F)) {
if (Features & (1 << FEATURE_AVX512VL)) { if (Features & (1 << FEATURE_AVX512VL)) {
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_SKYLAKE_AVX512; *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
} else { } else {
*Type = INTEL_KNL; // knl *Type = X86::INTEL_KNL; // knl
} }
break; break;
} }
if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) { if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) {
if (Features2 & (1 << (FEATURE_SHA - 32))) { if (Features2 & (1 << (FEATURE_SHA - 32))) {
*Type = INTEL_GOLDMONT; *Type = X86::INTEL_GOLDMONT;
} else { } else {
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_SKYLAKE; *Subtype = X86::INTEL_COREI7_SKYLAKE;
} }
break; break;
} }
if (Features2 & (1 << (FEATURE_ADX - 32))) { if (Features2 & (1 << (FEATURE_ADX - 32))) {
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_BROADWELL; *Subtype = X86::INTEL_COREI7_BROADWELL;
break; break;
} }
if (Features & (1 << FEATURE_AVX2)) { if (Features & (1 << FEATURE_AVX2)) {
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_HASWELL; *Subtype = X86::INTEL_COREI7_HASWELL;
break; break;
} }
if (Features & (1 << FEATURE_AVX)) { if (Features & (1 << FEATURE_AVX)) {
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_SANDYBRIDGE; *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
break; break;
} }
if (Features & (1 << FEATURE_SSE4_2)) { if (Features & (1 << FEATURE_SSE4_2)) {
if (Features2 & (1 << (FEATURE_MOVBE - 32))) { if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
*Type = INTEL_SILVERMONT; *Type = X86::INTEL_SILVERMONT;
} else { } else {
*Type = INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = INTEL_COREI7_NEHALEM; *Subtype = X86::INTEL_COREI7_NEHALEM;
} }
break; break;
} }
if (Features & (1 << FEATURE_SSE4_1)) { if (Features & (1 << FEATURE_SSE4_1)) {
*Type = INTEL_CORE2; // "penryn" *Type = X86::INTEL_CORE2; // "penryn"
*Subtype = INTEL_CORE2_45; *Subtype = X86::INTEL_CORE2_45;
break; break;
} }
if (Features & (1 << FEATURE_SSSE3)) { if (Features & (1 << FEATURE_SSSE3)) {
if (Features2 & (1 << (FEATURE_MOVBE - 32))) { if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
*Type = INTEL_BONNELL; // "bonnell" *Type = X86::INTEL_BONNELL; // "bonnell"
} else { } else {
*Type = INTEL_CORE2; // "core2" *Type = X86::INTEL_CORE2; // "core2"
*Subtype = INTEL_CORE2_65; *Subtype = X86::INTEL_CORE2_65;
} }
break; break;
} }
if (Features2 & (1 << (FEATURE_EM64T - 32))) { if (Features2 & (1 << (FEATURE_EM64T - 32))) {
*Type = INTEL_CORE2; // "core2" *Type = X86::INTEL_CORE2; // "core2"
*Subtype = INTEL_CORE2_65; *Subtype = X86::INTEL_CORE2_65;
break; break;
} }
if (Features & (1 << FEATURE_SSE3)) { if (Features & (1 << FEATURE_SSE3)) {
*Type = INTEL_CORE_DUO; *Type = X86::INTEL_CORE_DUO;
break; break;
} }
if (Features & (1 << FEATURE_SSE2)) { if (Features & (1 << FEATURE_SSE2)) {
*Type = INTEL_PENTIUM_M; *Type = X86::INTEL_PENTIUM_M;
break; break;
} }
if (Features & (1 << FEATURE_SSE)) { if (Features & (1 << FEATURE_SSE)) {
*Type = INTEL_PENTIUM_III; *Type = X86::INTEL_PENTIUM_III;
break; break;
} }
if (Features & (1 << FEATURE_MMX)) { if (Features & (1 << FEATURE_MMX)) {
*Type = INTEL_PENTIUM_II; *Type = X86::INTEL_PENTIUM_II;
break; break;
} }
*Type = INTEL_PENTIUM_PRO; *Type = X86::INTEL_PENTIUM_PRO;
break; break;
} }
break; break;
case 15: { case 15: {
if (Features2 & (1 << (FEATURE_EM64T - 32))) { if (Features2 & (1 << (FEATURE_EM64T - 32))) {
*Type = INTEL_NOCONA; *Type = X86::INTEL_NOCONA;
break; break;
} }
if (Features & (1 << FEATURE_SSE3)) { if (Features & (1 << FEATURE_SSE3)) {
*Type = INTEL_PRESCOTT; *Type = X86::INTEL_PRESCOTT;
break; break;
} }
*Type = INTEL_PENTIUM_IV; *Type = X86::INTEL_PENTIUM_IV;
break; break;
} }
default: default:
break; /*"generic"*/ break; /*"generic"*/
} }
} }
static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
unsigned Features, unsigned *Type, unsigned Features, unsigned *Type,
unsigned *Subtype) { unsigned *Subtype) {
// FIXME: this poorly matches the generated SubtargetFeatureKV table. There // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
// appears to be no way to generate the wide variety of AMD-specific targets // appears to be no way to generate the wide variety of AMD-specific targets
// from the information returned from CPUID. // from the information returned from CPUID.
switch (Family) { switch (Family) {
case 4: case 4:
*Type = AMD_i486; *Type = X86::AMD_i486;
break; break;
case 5: case 5:
*Type = AMDPENTIUM; *Type = X86::AMDPENTIUM;
switch (Model) { switch (Model) {
case 6: case 6:
case 7: case 7:
*Subtype = AMDPENTIUM_K6; *Subtype = X86::AMDPENTIUM_K6;
break; // "k6" break; // "k6"
case 8: case 8:
*Subtype = AMDPENTIUM_K62; *Subtype = X86::AMDPENTIUM_K62;
break; // "k6-2" break; // "k6-2"
case 9: case 9:
case 13: case 13:
*Subtype = AMDPENTIUM_K63; *Subtype = X86::AMDPENTIUM_K63;
break; // "k6-3" break; // "k6-3"
case 10: case 10:
*Subtype = AMDPENTIUM_GEODE; *Subtype = X86::AMDPENTIUM_GEODE;
break; // "geode" break; // "geode"
} }
break; break;
case 6: case 6:
if (Features & (1 << FEATURE_SSE)) { if (Features & (1 << FEATURE_SSE)) {
*Type = AMD_ATHLON_XP; *Type = X86::AMD_ATHLON_XP;
break; // "athlon-xp" break; // "athlon-xp"
} }
*Type = AMD_ATHLON; *Type = X86::AMD_ATHLON;
break; // "athlon" break; // "athlon"
case 15: case 15:
if (Features & (1 << FEATURE_SSE3)) { if (Features & (1 << FEATURE_SSE3)) {
*Type = AMD_K8SSE3; *Type = X86::AMD_K8SSE3;
break; // "k8-sse3" break; // "k8-sse3"
} }
*Type = AMD_K8; *Type = X86::AMD_K8;
break; // "k8" break; // "k8"
case 16: case 16:
*Type = AMDFAM10H; // "amdfam10" *Type = X86::AMDFAM10H; // "amdfam10"
switch (Model) { switch (Model) {
case 2: case 2:
*Subtype = AMDFAM10H_BARCELONA; *Subtype = X86::AMDFAM10H_BARCELONA;
break; break;
case 4: case 4:
*Subtype = AMDFAM10H_SHANGHAI; *Subtype = X86::AMDFAM10H_SHANGHAI;
break; break;
case 8: case 8:
*Subtype = AMDFAM10H_ISTANBUL; *Subtype = X86::AMDFAM10H_ISTANBUL;
break; break;
} }
break; break;
case 20: case 20:
*Type = AMD_BTVER1; *Type = X86::AMD_BTVER1;
break; // "btver1"; break; // "btver1";
case 21: case 21:
*Type = AMDFAM15H; *Type = X86::AMDFAM15H;
if (Model >= 0x60 && Model <= 0x7f) { if (Model >= 0x60 && Model <= 0x7f) {
*Subtype = AMDFAM15H_BDVER4; *Subtype = X86::AMDFAM15H_BDVER4;
break; // "bdver4"; 60h-7Fh: Excavator break; // "bdver4"; 60h-7Fh: Excavator
} }
if (Model >= 0x30 && Model <= 0x3f) { if (Model >= 0x30 && Model <= 0x3f) {
*Subtype = AMDFAM15H_BDVER3; *Subtype = X86::AMDFAM15H_BDVER3;
break; // "bdver3"; 30h-3Fh: Steamroller break; // "bdver3"; 30h-3Fh: Steamroller
} }
if (Model >= 0x10 && Model <= 0x1f) { if (Model >= 0x10 && Model <= 0x1f) {
*Subtype = AMDFAM15H_BDVER2; *Subtype = X86::AMDFAM15H_BDVER2;
break; // "bdver2"; 10h-1Fh: Piledriver break; // "bdver2"; 10h-1Fh: Piledriver
} }
if (Model <= 0x0f) { if (Model <= 0x0f) {
*Subtype = AMDFAM15H_BDVER1; *Subtype = X86::AMDFAM15H_BDVER1;
break; // "bdver1"; 00h-0Fh: Bulldozer break; // "bdver1"; 00h-0Fh: Bulldozer
} }
break; break;
case 22: case 22:
*Type = AMD_BTVER2; *Type = X86::AMD_BTVER2;
break; // "btver2" break; // "btver2"
case 23: case 23:
*Type = AMDFAM17H; *Type = X86::AMDFAM17H;
*Subtype = AMDFAM17H_ZNVER1; *Subtype = X86::AMDFAM17H_ZNVER1;
break; break;
default: default:
break; // "generic" break; // "generic"
} }
} }
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
unsigned *FeaturesOut, unsigned *FeaturesOut,
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines#endif
getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2);
unsigned Type = 0; unsigned Type = 0;
unsigned Subtype = 0; unsigned Subtype = 0;
if (Vendor == SIG_INTEL) { if (Vendor == SIG_INTEL) {
getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
Features2, &Type, &Subtype); Features2, &Type, &Subtype);
switch (Type) {
case INTEL_i386:
return "i386";
case INTEL_i486:
return "i486";
case INTEL_PENTIUM:
return "pentium";
case INTEL_PENTIUM_MMX:
return "pentium-mmx";
case INTEL_PENTIUM_PRO:
return "pentiumpro";
case INTEL_PENTIUM_II:
return "pentium2";
case INTEL_PENTIUM_III:
return "pentium3";
case INTEL_PENTIUM_IV:
return "pentium4";
case INTEL_PENTIUM_M:
return "pentium-m";
case INTEL_CORE_DUO:
return "yonah";
case INTEL_CORE2:
switch (Subtype) {
case INTEL_CORE2_65:
return "core2";
case INTEL_CORE2_45:
return "penryn";
default:
llvm_unreachable("Unexpected subtype!");
}
case INTEL_COREI7:
switch (Subtype) {
case INTEL_COREI7_NEHALEM:
return "nehalem";
case INTEL_COREI7_WESTMERE:
return "westmere";
case INTEL_COREI7_SANDYBRIDGE:
return "sandybridge";
case INTEL_COREI7_IVYBRIDGE:
return "ivybridge";
case INTEL_COREI7_HASWELL:
return "haswell";
case INTEL_COREI7_BROADWELL:
return "broadwell";
case INTEL_COREI7_SKYLAKE:
return "skylake";
case INTEL_COREI7_SKYLAKE_AVX512:
return "skylake-avx512";
default:
llvm_unreachable("Unexpected subtype!");
}
case INTEL_BONNELL:
return "bonnell";
case INTEL_SILVERMONT:
return "silvermont";
case INTEL_GOLDMONT:
return "goldmont";
case INTEL_KNL:
return "knl";
case INTEL_KNM:
return "knm";
case INTEL_NOCONA:
return "nocona";
case INTEL_PRESCOTT:
return "prescott";
default:
break;
}
} else if (Vendor == SIG_AMD) { } else if (Vendor == SIG_AMD) {
getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
switch (Type) {
case AMD_i486:
return "i486";
case AMDPENTIUM:
switch (Subtype) {
case AMDPENTIUM_K6:
return "k6";
case AMDPENTIUM_K62:
return "k6-2";
case AMDPENTIUM_K63:
return "k6-3";
case AMDPENTIUM_GEODE:
return "geode";
default:
return "pentium";
}
case AMD_ATHLON:
return "athlon";
case AMD_ATHLON_XP:
return "athlon-xp";
case AMD_K8:
return "k8";
case AMD_K8SSE3:
return "k8-sse3";
case AMDFAM10H:
return "amdfam10";
case AMD_BTVER1:
return "btver1";
case AMDFAM15H:
switch (Subtype) {
default: // There are gaps in the subtype detection.
case AMDFAM15H_BDVER1:
return "bdver1";
case AMDFAM15H_BDVER2:
return "bdver2";
case AMDFAM15H_BDVER3:
return "bdver3";
case AMDFAM15H_BDVER4:
return "bdver4";
}
case AMD_BTVER2:
return "btver2";
case AMDFAM17H:
return "znver1";
default:
break;
}
} }
// Check subtypes first since those are more specific.
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
if (Subtype == X86::ENUM) \
return ARCHNAME;
#include "llvm/Support/X86TargetParser.def"
// Now check types.
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
if (Type == X86::ENUM) \
return ARCHNAME;
#include "llvm/Support/X86TargetParser.def"
return "generic"; return "generic";
} }
#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
StringRef sys::getHostCPUName() { StringRef sys::getHostCPUName() {
host_basic_info_data_t hostInfo; host_basic_info_data_t hostInfo;
mach_msg_type_number_t infoCount; mach_msg_type_number_t infoCount;
▲ Show 20 Lines • Show All 322 Lines • Show Last 20 Lines