This is an archive of the discontinued LLVM Phabricator instance.

Differential D39560

[AMDGPU] Convert lit tests to new addr space mapping, part 1
AbandonedPublic

Authored by yaxunl on Nov 2 2017, 11:19 AM.

Details

Reviewers
arsenm
rampitec
b-sumner
Summary

Convert AMDGPU/*.ll to use amdgiz environment by the following script.

The plan is to convert all lit tests in llvm and calng for amdgpu to use amdgiz step by step,
then make amdgiz the default environment and clean up the old address space mapping.

#!/bin/bash
#
# script to convert .ll from old address space mapping
# to new address space mapping for AMDGPU.
#
# addr space change:
# 0 -> 5
# 4 -> 0
#

if [[ $# -ne 2 ]]; then
  echo "Convert .ll from old address space mapping to new address space mapping for AMDGPU"
  echo "Usage: chaddr.sh file newfile"
  exit
fi

file=$1
newf=$2

if grep amdgiz $file >/dev/null; then
    exit
fi

has_amdgcn=0
if grep 'mtriple=amdgcn' $file >/dev/null; then
  has_amdgcn=1
elif grep 'march=amdgcn' $file >/dev/null; then
  has_amdgcn=1
fi

has_r600=0
if grep 'mtriple=r600' $file >/dev/null; then
  has_r600=1
elif grep 'march=r600' $file >/dev/null; then
  has_r600=1
fi

if [[ $has_amdgcn == 0 && $has_r600 == 0 ]] ; then
  exit
fi

cp $file $newf

sed -i -e 's:\([]a-zA-Z0-9_>][]a-zA-Z0-9_>]* *\)\*:\1 addrspace(5)*:g' \
    -e 's: addrspace(4) *\*:*:g' \
    -e 's: addrspace(0) *\*: addrspace(5)*:g' \
    -e 's: \(addrspace(.)\*\)\*: \1 addrspace(5)*:g' \
    -e 's:-mtriple=\([^ ]*\):-mtriple=\1-amdgiz:g' \
    -e 's:-march=\([^ ]*\):-march=\1 -mtriple=\1---amdgiz:g' \
    -e 's:-mtriple=\([^ ]*\) \(.*\)-mtriple=\([^ ]*\): \2 -mtriple=\3:g' \
    -e 's: = alloca \(.*\): = alloca \1, addrspace(5):g' \
    -e '/INT/s: addrspace(5)\*:*:g' \
    -e '/SET/s: addrspace(5)\*:*:g' \
    -e '/MOV/s: addrspace(5)\*:*:g' \
    -e '/SH/s: addrspace(5)\*:*:g' \
    -e '/MUL/s: addrspace(5)\*:*:g' \
    -e '/LDS/s: addrspace(5)\*:*:g' \
    -e '/IEEE/s: addrspace(5)\*:*:g' \
    -e '/NoAlias/s: addrspace(5)\*:*:g' \
    -e '/DOT/s: addrspace(5)\*:*:g' \
    $newf

if ! grep mtriple $newf >/dev/null; then
  sed -i -e 's:-march=\([^ ]*\):-march=\1 -mtriple=\1---amdgiz:g' $newf
fi
 
## add missing datalayout 
if grep alloca $file >/dev/null && ! grep datalayout $file >/dev/null; then
    line=$(cat -n $file | grep ';.*RUN'| tail -1 |while read a b; do echo $a; done)
    let "line=line+1"
    sed -i "${line}i"'target datalayout = "A5"' $newf
fi

Diff Detail

Event Timeline

yaxunl created this revision.Nov 2 2017, 11:19 AM
Herald added subscribers: eraman, t-tye, tpr and 7 others. · View Herald TranscriptNov 2 2017, 11:19 AM
arsenm edited edge metadata.Nov 3 2017, 6:18 AM

You should put the script you used to convert in the commit message since I'll undoubtedly need to convert some tests at some point

yaxunl added a comment.Nov 3 2017, 7:15 AM
In D39560#915041, @arsenm wrote:

You should put the script you used to convert in the commit message since I'll undoubtedly need to convert some tests at some point

I will add it.

yaxunl updated this revision to Diff 121485.Nov 3 2017, 8:22 AM

Add the script for converting .ll from old addr space to new addr space.

yaxunl added a comment.Nov 3 2017, 8:32 AM

the script is chaddr.sh.

yaxunl updated this revision to Diff 121660.Nov 5 2017, 12:20 PM

Update tests.

arsenm added a comment.Nov 5 2017, 3:52 PM

The script isn't that big, so in the past the policy has been to just put the body of the script literally in the commit message rather than adding a temporary file that will be forgotten.

This is adding the amdgiz environment to all the tests, which is not what I expected. I expected that to be removed and to change the default to the new mapping thus removing the need for the triple changes in all of these tests. Is your plan to do that as a separate step after?

yaxunl added a comment.Nov 9 2017, 5:11 PM
In D39560#916380, @arsenm wrote:

The script isn't that big, so in the past the policy has been to just put the body of the script literally in the commit message rather than adding a temporary file that will be forgotten.

This is adding the amdgiz environment to all the tests, which is not what I expected. I expected that to be removed and to change the default to the new mapping thus removing the need for the triple changes in all of these tests. Is your plan to do that as a separate step after?

Yes. Because I have to convert all llvm and clang lit tests then be able to change amdgiz to be the default address space and remove the code about the old address space mapping. However there are still issues which I need to fix. If I do not do the conversion by parts, I face the risk of regression of already passing lit tests. So my plan is to convert the passing lit tests gradually, until all tests are using amdgiz, then make it default in llvm and clang and remove the old address space mapping.

yaxunl updated this revision to Diff 122441.Nov 10 2017, 8:21 AM
yaxunl edited the summary of this revision. (Show Details)
yaxunl added a subscriber: jvesely.

Update all passing ll tests under AMDGPU for new addr space mapping.

Remove the script and put it in git log.

yaxunl updated this revision to Diff 122634.Nov 13 2017, 4:04 AM
yaxunl edited the summary of this revision. (Show Details)

Fixed some script issue and added more passing tests.

yaxunl added a comment.Nov 13 2017, 1:48 PM

ping

yaxunl abandoned this revision.Dec 7 2017, 7:51 AM

superseded by D40955

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Diff 122634

test/CodeGen/AMDGPU/32-bit-local-address-space.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and ; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
; the global address space(1) uses 64-bit pointers. These tests check to make sure ; the global address space(1) uses 64-bit pointers. These tests check to make sure

test/CodeGen/AMDGPU/InlineAsmCrash.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; CHECK: ;;#ASMSTART ; CHECK: ;;#ASMSTART
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
define void @foo(i32* %ptr) { define void @foo(i32 addrspace(5)* %ptr) {
%tmp = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "s_nop 0", "=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65"(i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2) %tmp = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "s_nop 0", "=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65"(i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2)
%tmp2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %tmp, 0 %tmp2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %tmp, 0
store i32 %tmp2, i32* %ptr, align 4 store i32 %tmp2, i32 addrspace(5)* %ptr, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/add-debug.ll

; RUN: llc < %s -march=amdgcn -mcpu=tahiti -debug ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -debug
; RUN: llc < %s -march=amdgcn -mcpu=tonga -debug ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -debug
; REQUIRES: asserts ; REQUIRES: asserts
; Check that SelectionDAGDumper does not crash on int_SI_if. ; Check that SelectionDAGDumper does not crash on int_SI_if.

test/CodeGen/AMDGPU/add.i16.ll

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_add_i16: ; GCN-LABEL: {{^}}v_test_add_i16:

test/CodeGen/AMDGPU/add.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
;FUNC-LABEL: {{^}}test1: ;FUNC-LABEL: {{^}}test1:
;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

test/CodeGen/AMDGPU/add.v2i16.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_add_v2i16: ; GCN-LABEL: {{^}}v_test_add_v2i16:

test/CodeGen/AMDGPU/add_i128.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_i128_vreg: ; GCN-LABEL: {{^}}test_i128_vreg:
; GCN: v_add_i32_e32 v[[LO:[0-9]+]], vcc, ; GCN: v_add_i32_e32 v[[LO:[0-9]+]], vcc,

test/CodeGen/AMDGPU/add_i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() readnone declare i32 @llvm.amdgcn.workitem.id.x() readnone

test/CodeGen/AMDGPU/addrspacecast-captured.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
; Nothing should be done if the addrspacecast is captured. ; Nothing should be done if the addrspacecast is captured.
declare void @consume_ptr2int(i32) #0 declare void @consume_ptr2int(i32) #0
; CHECK-LABEL: @addrspacecast_captured( ; CHECK-LABEL: @addrspacecast_captured(
; CHECK: %data = alloca i32, align 4 ; CHECK: %data = alloca i32, align 4, addrspace(5)
; CHECK: %cast = addrspacecast i32* %data to i32 addrspace(4)* ; CHECK: %cast = addrspacecast i32 addrspace(5)* %data to i32*
; CHECK: %ptr2int = ptrtoint i32 addrspace(4)* %cast to i32 ; CHECK: %ptr2int = ptrtoint i32* %cast to i32
; CHECK: store i32 %ptr2int, i32 addrspace(1)* %out ; CHECK: store i32 %ptr2int, i32 addrspace(1)* %out
define amdgpu_kernel void @addrspacecast_captured(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @addrspacecast_captured(i32 addrspace(1)* %out) #0 {
entry: entry:
%data = alloca i32, align 4 %data = alloca i32, align 4, addrspace(5)
%cast = addrspacecast i32* %data to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(5)* %data to i32*
%ptr2int = ptrtoint i32 addrspace(4)* %cast to i32 %ptr2int = ptrtoint i32* %cast to i32
store i32 %ptr2int, i32 addrspace(1)* %out store i32 %ptr2int, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: @addrspacecast_captured_store( ; CHECK-LABEL: @addrspacecast_captured_store(
; CHECK: %data = alloca i32, align 4 ; CHECK: %data = alloca i32, align 4, addrspace(5)
; CHECK: %cast = addrspacecast i32* %data to i32 addrspace(4)* ; CHECK: %cast = addrspacecast i32 addrspace(5)* %data to i32*
; CHECK: store i32 addrspace(4)* %cast, i32 addrspace(4)* addrspace(1)* %out ; CHECK: store i32* %cast, i32* addrspace(1)* %out
define amdgpu_kernel void @addrspacecast_captured_store(i32 addrspace(4)* addrspace(1)* %out) #0 { define amdgpu_kernel void @addrspacecast_captured_store(i32* addrspace(1)* %out) #0 {
entry: entry:
%data = alloca i32, align 4 %data = alloca i32, align 4, addrspace(5)
%cast = addrspacecast i32* %data to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(5)* %data to i32*
store i32 addrspace(4)* %cast, i32 addrspace(4)* addrspace(1)* %out store i32* %cast, i32* addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: @addrspacecast_captured_call( ; CHECK-LABEL: @addrspacecast_captured_call(
; CHECK: %data = alloca i32, align 4 ; CHECK: %data = alloca i32, align 4, addrspace(5)
; CHECK: %cast = addrspacecast i32* %data to i32 addrspace(4)* ; CHECK: %cast = addrspacecast i32 addrspace(5)* %data to i32*
; CHECK: %ptr2int = ptrtoint i32 addrspace(4)* %cast to i32 ; CHECK: %ptr2int = ptrtoint i32* %cast to i32
; CHECK: call void @consume_ptr2int(i32 %ptr2int) ; CHECK: call void @consume_ptr2int(i32 %ptr2int)
define amdgpu_kernel void @addrspacecast_captured_call() #0 { define amdgpu_kernel void @addrspacecast_captured_call() #0 {
entry: entry:
%data = alloca i32, align 4 %data = alloca i32, align 4, addrspace(5)
%cast = addrspacecast i32* %data to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(5)* %data to i32*
%ptr2int = ptrtoint i32 addrspace(4)* %cast to i32 %ptr2int = ptrtoint i32* %cast to i32
call void @consume_ptr2int(i32 %ptr2int) call void @consume_ptr2int(i32 %ptr2int)
ret void ret void
} }

test/CodeGen/AMDGPU/addrspacecast.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
target datalayout = "A5"
; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
Context not available.
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 7, i32 addrspace(4)* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
Context not available.
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 {
%stof = addrspacecast i32* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(5)* %ptr to i32*
store volatile i32 7, i32 addrspace(4)* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
Context not available.
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] ; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
store volatile i32 7, i32 addrspace(4)* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
Context not available.
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} ; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(2)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(2)* %ptr to i32*
%ld = load volatile i32, i32 addrspace(4)* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
Context not available.
; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
; HSA: ds_write_b32 [[CASTPTR]], v[[K]] ; HSA: ds_write_b32 [[CASTPTR]], v[[K]]
define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(3)* %ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
store volatile i32 0, i32 addrspace(3)* %ftos store volatile i32 0, i32 addrspace(3)* %ftos
ret void ret void
} }
Context not available.
; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]] ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]]
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} ; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}
define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32* %ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
store volatile i32 0, i32* %ftos store volatile i32 0, i32 addrspace(5)* %ftos
ret void ret void
} }
Context not available.
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0
; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
store volatile i32 0, i32 addrspace(1)* %ftos store volatile i32 0, i32 addrspace(1)* %ftos
ret void ret void
} }
Context not available.
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 ; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(2)* %ftos = addrspacecast i32* %ptr to i32 addrspace(2)*
load volatile i32, i32 addrspace(2)* %ftos load volatile i32, i32 addrspace(2)* %ftos
ret void ret void
} }
Context not available.
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(3)* null to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* null to i32*
store volatile i32 7, i32 addrspace(4)* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
Context not available.
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: ds_write_b32 [[PTR]], [[K]] ; HSA: ds_write_b32 [[PTR]], [[K]]
define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 { define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(3)* %cast = addrspacecast i32* null to i32 addrspace(3)*
store volatile i32 7, i32 addrspace(3)* %cast store volatile i32 7, i32 addrspace(3)* %cast
ret void ret void
} }
Context not available.
; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32*
store volatile i32 7, i32 addrspace(4)* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
Context not available.
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: ds_write_b32 [[PTR]], [[K]] ; HSA: ds_write_b32 [[PTR]], [[K]]
define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 { define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(4)* inttoptr (i64 -1 to i32 addrspace(4)*) to i32 addrspace(3)* %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)*
store volatile i32 7, i32 addrspace(3)* %cast store volatile i32 7, i32 addrspace(3)* %cast
ret void ret void
} }
Context not available.
; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32* null to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(5)* null to i32*
store volatile i32 7, i32 addrspace(4)* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
Context not available.
; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} ; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 { define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(0)* %cast = addrspacecast i32* null to i32 addrspace(5)*
store volatile i32 7, i32* %cast store volatile i32 7, i32 addrspace(5)* %cast
ret void ret void
} }
Context not available.
br i1 %cmp, label %local, label %global br i1 %cmp, label %local, label %global
local: local:
%flat_local = addrspacecast i32 addrspace(3)* %lptr to i32 addrspace(4)* %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32*
br label %end br label %end
global: global:
%flat_global = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32*
br label %end br label %end
end: end:
%fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ] %fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ]
store volatile i32 %x, i32 addrspace(4)* %fptr, align 4 store volatile i32 %x, i32* %fptr, align 4
; %val = load i32, i32 addrspace(4)* %fptr, align 4 ; %val = load i32, i32* %fptr, align 4
; store i32 %val, i32 addrspace(1)* %out, align 4 ; store i32 %val, i32 addrspace(1)* %out, align 4
ret void ret void
} }
Context not available.
; HSA: s_barrier ; HSA: s_barrier
; HSA: {{flat|global}}_load_dword ; HSA: {{flat|global}}_load_dword
define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
%alloca = alloca i32, i32 9, align 4 %alloca = alloca i32, i32 9, align 4, addrspace(5)
%x = call i32 @llvm.amdgcn.workitem.id.x() #2 %x = call i32 @llvm.amdgcn.workitem.id.x() #2
%pptr = getelementptr i32, i32* %alloca, i32 %x %pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x
%fptr = addrspacecast i32* %pptr to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(5)* %pptr to i32*
store volatile i32 %x, i32 addrspace(4)* %fptr store volatile i32 %x, i32* %fptr
; Dummy call ; Dummy call
call void @llvm.amdgcn.s.barrier() #1 call void @llvm.amdgcn.s.barrier() #1
%reload = load volatile i32, i32 addrspace(4)* %fptr, align 4 %reload = load volatile i32, i32* %fptr, align 4
store volatile i32 %reload, i32 addrspace(1)* %out, align 4 store volatile i32 %reload, i32 addrspace(1)* %out, align 4
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/alignbit-pat.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}alignbit_shr_pat: ; GCN-LABEL: {{^}}alignbit_shr_pat:
; GCN-DAG: s_load_dword s[[SHR:[0-9]+]] ; GCN-DAG: s_load_dword s[[SHR:[0-9]+]]

test/CodeGen/AMDGPU/amdgcn.bitcast.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; This test just checks that the compiler doesn't crash. ; This test just checks that the compiler doesn't crash.

test/CodeGen/AMDGPU/amdgcn.private-memory.ll

; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s ; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s
; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE -check-prefix=HSA %s ; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE -check-prefix=HSA %s
; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s ; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s
; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA -check-prefix=HSA %s ; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa-amdgiz -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA -check-prefix=HSA %s
; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s ; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s
; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s ; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s
target datalayout = "A5"
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
Context not available.
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
entry: entry:
%0 = alloca [2 x i32] %0 = alloca [2 x i32], addrspace(5)
%1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 %1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 %2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
store i32 0, i32* %1 store i32 0, i32 addrspace(5)* %1
store i32 1, i32* %2 store i32 1, i32 addrspace(5)* %2
%3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in %3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
%4 = load i32, i32* %3 %4 = load i32, i32 addrspace(5)* %3
%5 = call i32 @llvm.amdgcn.workitem.id.x() %5 = call i32 @llvm.amdgcn.workitem.id.x()
%6 = add i32 %4, %5 %6 = add i32 %4, %5
store i32 %6, i32 addrspace(1)* %out store i32 %6, i32 addrspace(1)* %out
Context not available.

test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll

; RUN: opt -mtriple=amdgcn-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s ; RUN: opt -mtriple=amdgcn---amdgiz -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s
; RUN: opt -mtriple=r600-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s ; RUN: opt -mtriple=r600---amdgiz -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s
; CHECK: NoAlias: i8 addrspace(1)* %p1, i8* %p ; CHECK: NoAlias: i8 addrspace(1)* %p1, i8 addrspace(5)* %p
define void @test(i8* %p, i8 addrspace(1)* %p1) { define void @test(i8 addrspace(5)* %p, i8 addrspace(1)* %p1) {
ret void ret void
} }

test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll

; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -amdgpu-codegenprepare %s | FileCheck %s
; RUN: opt -S -amdgpu-codegenprepare %s | FileCheck -check-prefix=NOOP %s ; RUN: opt -S -amdgpu-codegenprepare %s | FileCheck -check-prefix=NOOP %s
; Make sure this doesn't crash with no triple ; Make sure this doesn't crash with no triple

test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll

; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: @add_i3( ; GCN-LABEL: @add_i3(
; SI: %r = add i3 %a, %b ; SI: %r = add i3 %a, %b

test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}shader_cc: ; GCN-LABEL: {{^}}shader_cc:

test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; Legacy intrinsics that just read implicit parameters ; Legacy intrinsics that just read implicit parameters

test/CodeGen/AMDGPU/amdpal-cs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; GCN-LABEL: {{^}}cs_amdpal: ; GCN-LABEL: {{^}}cs_amdpal:

test/CodeGen/AMDGPU/amdpal-es.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
; GCN-LABEL: {{^}}es_amdpal: ; GCN-LABEL: {{^}}es_amdpal:

test/CodeGen/AMDGPU/amdpal-gs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
; GCN-LABEL: {{^}}gs_amdpal: ; GCN-LABEL: {{^}}gs_amdpal:

test/CodeGen/AMDGPU/amdpal-hs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
; GCN-LABEL: {{^}}hs_amdpal: ; GCN-LABEL: {{^}}hs_amdpal:

test/CodeGen/AMDGPU/amdpal-ls.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
; GCN-LABEL: {{^}}ls_amdpal: ; GCN-LABEL: {{^}}ls_amdpal:

test/CodeGen/AMDGPU/amdpal-psenable.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; This pixel shader does not use the result of its interpolation, so it would ; This pixel shader does not use the result of its interpolation, so it would
; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests ; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests

test/CodeGen/AMDGPU/amdpal-vs.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
; GCN-LABEL: {{^}}vs_amdpal: ; GCN-LABEL: {{^}}vs_amdpal:

test/CodeGen/AMDGPU/amdpal.ll

; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefix=PAL --enable-var-scope %s ; RUN: llc < %s -mtriple=amdgcn--amdpal-amdgiz -mcpu=tahiti | FileCheck --check-prefix=PAL --enable-var-scope %s
target datalayout = "A5"
; PAL: .AMDGPU.config ; PAL: .AMDGPU.config
Context not available.
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]: ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32* %out) { define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
entry: entry:
%v = alloca [2 x i32] %v = alloca [2 x i32], addrspace(5)
%vv = bitcast [2 x i32]* %v to <2 x i32>* %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
store <2 x i32> %in, <2 x i32>* %vv store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
%e = getelementptr [2 x i32], [2 x i32]* %v, i32 0, i32 %idx %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
%x = load i32, i32* %e %x = load i32, i32 addrspace(5)* %e
store i32 %x, i32* %out store i32 %x, i32 addrspace(5)* %out
ret void ret void
} }
Context not available.
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]: ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32* %out) #0 { define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
entry: entry:
%v = alloca [2 x i32] %v = alloca [2 x i32], addrspace(5)
%vv = bitcast [2 x i32]* %v to <2 x i32>* %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
store <2 x i32> %in, <2 x i32>* %vv store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
%e = getelementptr [2 x i32], [2 x i32]* %v, i32 0, i32 %idx %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
%x = load i32, i32* %e %x = load i32, i32 addrspace(5)* %e
store i32 %x, i32* %out store i32 %x, i32 addrspace(5)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/and-gcn.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}v_and_i64_br: ; FUNC-LABEL: {{^}}v_and_i64_br:
; SI: s_and_b64 ; SI: s_and_b64

test/CodeGen/AMDGPU/and.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() #0 declare i32 @llvm.r600.read.tidig.x() #0

test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
Context not available.
; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 { ; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 {
define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 { ; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 {
define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 { define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 { ; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 {
define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 { define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
call void @func_indirect_use_queue_ptr() call void @func_indirect_use_queue_ptr()
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll

; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s ; RUN: opt -mtriple=amdgcn-unknown-amdhsa-amdgiz -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
Context not available.
; HSA: define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 { ; HSA: define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 {
define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32* %ptr) #11 { ; HSA: define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #11 {
define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32* %ptr) #1 { define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #1 {
%stof = addrspacecast i32* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(5)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(3)* %ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
store volatile i32 0, i32 addrspace(3)* %ftos store volatile i32 0, i32 addrspace(3)* %ftos
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32* %ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
store volatile i32 0, i32* %ftos store volatile i32 0, i32 addrspace(5)* %ftos
ret void ret void
} }
; No-op addrspacecast should not use queue ptr ; No-op addrspacecast should not use queue ptr
; HSA: define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 {
define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 {
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(2)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(2)* %ptr to i32*
%ld = load volatile i32, i32 addrspace(4)* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
store volatile i32 0, i32 addrspace(1)* %ftos store volatile i32 0, i32 addrspace(1)* %ftos
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(2)* %ftos = addrspacecast i32* %ptr to i32 addrspace(2)*
%ld = load volatile i32, i32 addrspace(2)* %ftos %ld = load volatile i32, i32 addrspace(2)* %ftos
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/annotate-kernel-features.ll

; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=NOHSA -check-prefix=ALL %s ; RUN: opt -S -mtriple=amdgcn-unknown-unknown-amdgiz -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=NOHSA -check-prefix=ALL %s
declare i32 @llvm.r600.read.tgid.x() #0 declare i32 @llvm.r600.read.tgid.x() #0
declare i32 @llvm.r600.read.tgid.y() #0 declare i32 @llvm.r600.read.tgid.y() #0

test/CodeGen/AMDGPU/anonymous-gv.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji | FileCheck %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji | FileCheck %s
; Make sure we don't crash on a global variable with no name. ; Make sure we don't crash on a global variable with no name.
@0 = external addrspace(1) global i32 @0 = external addrspace(1) global i32

test/CodeGen/AMDGPU/any_extend_vector_inreg.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}any_extend_vector_inreg_v16i8_to_v4i32: ; GCN-LABEL: {{^}}any_extend_vector_inreg_v16i8_to_v4i32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4

test/CodeGen/AMDGPU/anyext.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX89 %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone

test/CodeGen/AMDGPU/array-ptr-calc-i32.ll

; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
target datalayout = "A5"
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
Context not available.
; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this ; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
; alloca to a vector. It currently fails because it does not know how ; alloca to a vector. It currently fails because it does not know how
; to interpret: ; to interpret:
; getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b ; getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 1, i32 %b
; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64 ; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64
; SI-PROMOTE: ds_write_b32 [[PTRREG]] ; SI-PROMOTE: ds_write_b32 [[PTRREG]]
define amdgpu_kernel void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 { define amdgpu_kernel void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 {
%alloca = alloca [16 x i32], align 16 %alloca = alloca [16 x i32], align 16, addrspace(5)
%mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0); %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0);
%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
%a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid
Context not available.
%a = load i32, i32 addrspace(1)* %a_ptr %a = load i32, i32 addrspace(1)* %a_ptr
%b = load i32, i32 addrspace(1)* %b_ptr %b = load i32, i32 addrspace(1)* %b_ptr
%result = add i32 %a, %b %result = add i32 %a, %b
%alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b %alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 1, i32 %b
store i32 %result, i32* %alloca_ptr, align 4 store i32 %result, i32 addrspace(5)* %alloca_ptr, align 4
; Dummy call ; Dummy call
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%reload = load i32, i32* %alloca_ptr, align 4 %reload = load i32, i32 addrspace(5)* %alloca_ptr, align 4
%out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store i32 %reload, i32 addrspace(1)* %out_ptr, align 4 store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
ret void ret void
Context not available.

test/CodeGen/AMDGPU/array-ptr-calc-i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0

test/CodeGen/AMDGPU/ashr.v2i16.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
; GCN-LABEL: {{^}}s_ashr_v2i16: ; GCN-LABEL: {{^}}s_ashr_v2i16:
; GFX9: s_load_dword [[LHS:s[0-9]+]] ; GFX9: s_load_dword [[LHS:s[0-9]+]]

test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SICI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SICI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SICI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SICI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset: ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb

test/CodeGen/AMDGPU/atomic_load_add.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}atomic_add_local: ; FUNC-LABEL: {{^}}atomic_add_local:
; R600: LDS_ADD * ; R600: LDS_ADD *

test/CodeGen/AMDGPU/atomic_load_sub.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}atomic_sub_local: ; FUNC-LABEL: {{^}}atomic_sub_local:
; R600: LDS_SUB * ; R600: LDS_SUB *

test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=HSAMD %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=HSAMD %s
; CHECK-LABEL: {{^}}min_64_max_64: ; CHECK-LABEL: {{^}}min_64_max_64:
; CHECK: SGPRBlocks: 0 ; CHECK: SGPRBlocks: 0

test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=ALL %s
; If spilling to smem, additional registers are used for the resource ; If spilling to smem, additional registers are used for the resource
; descriptor. ; descriptor.
Context not available.
; %x.3 = call i64 @llvm.amdgcn.dispatch.id() ; %x.3 = call i64 @llvm.amdgcn.dispatch.id()
; %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() ; %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
; %x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr() ; %x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()
; store volatile i32 0, i32* undef ; store volatile i32 0, i32 addrspace(5)* undef
; br label %stores ; br label %stores
; ;
;stores: ;stores:
Context not available.
; i32 addrspace(1)* %out3, ; i32 addrspace(1)* %out3,
; i32 addrspace(1)* %out4, ; i32 addrspace(1)* %out4,
; i32 %one, i32 %two, i32 %three, i32 %four) #2 { ; i32 %one, i32 %two, i32 %three, i32 %four) #2 {
; store volatile i32 0, i32* undef ; store volatile i32 0, i32 addrspace(5)* undef
; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x() ; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
; store volatile i32 %x.0, i32 addrspace(1)* undef ; store volatile i32 %x.0, i32 addrspace(1)* undef
; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y() ; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
Context not available.

test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
@var = addrspace(1) global float 0.0 @var = addrspace(1) global float 0.0

test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
; Exactly 1 wave per execution unit. ; Exactly 1 wave per execution unit.
; CHECK-LABEL: {{^}}empty_exactly_1: ; CHECK-LABEL: {{^}}empty_exactly_1:

test/CodeGen/AMDGPU/attr-unparseable.ll

; RUN: not llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: can't parse integer attribute amdgpu-num-sgpr ; CHECK: can't parse integer attribute amdgpu-num-sgpr
define amdgpu_kernel void @unparseable_single_0() #0 { define amdgpu_kernel void @unparseable_single_0() #0 {

test/CodeGen/AMDGPU/barrier-elimination.ll

; RUN: llc -march=amdgcn < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck %s
; CHECK-LABEL: {{^}}unknown_wgs: ; CHECK-LABEL: {{^}}unknown_wgs:
; CHECK: s_barrier ; CHECK: s_barrier

test/CodeGen/AMDGPU/basic-branch.ll

; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCNNOOPT -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCNNOOPT -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCNNOOPT -check-prefix=GCN %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCNOPT -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCNOPT -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCNOPT -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCNOPT -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_branch: ; GCN-LABEL: {{^}}test_branch:
; GCNNOOPT: v_writelane_b32 ; GCNNOOPT: v_writelane_b32

test/CodeGen/AMDGPU/basic-call-return.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
define void @void_func_void() #2 { define void @void_func_void() #2 {
ret void ret void

test/CodeGen/AMDGPU/basic-loop.ll

; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck %s ; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck %s
; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s ; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck %s
; CHECK-LABEL: {{^}}test_loop: ; CHECK-LABEL: {{^}}test_loop:
define amdgpu_kernel void @test_loop(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) nounwind { define amdgpu_kernel void @test_loop(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) nounwind {

test/CodeGen/AMDGPU/bfe-combine.ll

; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-sdwa-peephole=0 < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s
; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s
; GCN-LABEL: {{^}}bfe_combine8: ; GCN-LABEL: {{^}}bfe_combine8:
; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8

test/CodeGen/AMDGPU/bfe-patterns.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}v_ubfe_sub_i32: ; GCN-LABEL: {{^}}v_ubfe_sub_i32:
; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]

test/CodeGen/AMDGPU/bfe_uint.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; CHECK: {{^}}bfe_def: ; CHECK: {{^}}bfe_def:
; CHECK: BFE_UINT ; CHECK: BFE_UINT

test/CodeGen/AMDGPU/bfi_int.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck --check-prefix=R600 %s
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck --check-prefix=SI %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI %s
; BFI_INT Definition pattern from ISA docs ; BFI_INT Definition pattern from ISA docs
; (y & x) | (z & ~x) ; (y & x) | (z & ~x)

test/CodeGen/AMDGPU/bfm.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}bfm_pattern: ; FUNC-LABEL: {{^}}bfm_pattern:
; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} ; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}

test/CodeGen/AMDGPU/big_alu.ll

; RUN: llc -march=r600 -mcpu=cedar < %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cedar < %s
; This test ensures that R600 backend can handle ifcvt properly ; This test ensures that R600 backend can handle ifcvt properly

test/CodeGen/AMDGPU/bitcast-vector-extract.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; The bitcast should be pushed through the bitcasts so the vectors can ; The bitcast should be pushed through the bitcasts so the vectors can
; be broken down and the shared components can be CSEd ; be broken down and the shared components can be CSEd

test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Test that materialization constants that are the bit reversed of ; Test that materialization constants that are the bit reversed of
; inline immediates are replaced with bfrev of the inline immediate to ; inline immediates are replaced with bfrev of the inline immediate to

test/CodeGen/AMDGPU/bitreverse.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1

test/CodeGen/AMDGPU/br_cc.f16.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}br_cc_f16: ; GCN-LABEL: {{^}}br_cc_f16:
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/branch-condition-and.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; This used to crash because during intermediate control flow lowering, there ; This used to crash because during intermediate control flow lowering, there
; was a sequence ; was a sequence

test/CodeGen/AMDGPU/branch-relax-bundle.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 < %s | FileCheck -check-prefix=GCN %s
; Restrict maximum branch to between +15 and -16 dwords ; Restrict maximum branch to between +15 and -16 dwords

test/CodeGen/AMDGPU/branch-relax-spill.ll

; RUN: not llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s
; FIXME: This should be able to compile, but requires inserting an ; FIXME: This should be able to compile, but requires inserting an
; extra block to restore the scavenged register. ; extra block to restore the scavenged register.

test/CodeGen/AMDGPU/branch-relaxation.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -check-prefix=GCN %s
; FIXME: We should use llvm-mc for this, but we can't even parse our own output. ; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
; See PR33579. ; See PR33579.
; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s
; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s ; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
; OBJ: Relocations [ ; OBJ: Relocations [

test/CodeGen/AMDGPU/branch-uniformity.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; The branch instruction in LOOP49 has a uniform condition, but PHI instructions ; The branch instruction in LOOP49 has a uniform condition, but PHI instructions
; introduced by the structurizecfg pass previously caused a false divergence ; introduced by the structurizecfg pass previously caused a false divergence

test/CodeGen/AMDGPU/bswap.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.bswap.i32(i32) nounwind readnone declare i32 @llvm.bswap.i32(i32) nounwind readnone
declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone

test/CodeGen/AMDGPU/bug-vopc-commute.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; ;

test/CodeGen/AMDGPU/build_vector.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=R600
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck %s --check-prefix=SI
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI
; R600: {{^}}build_vector2: ; R600: {{^}}build_vector2:
; R600: MOV ; R600: MOV

test/CodeGen/AMDGPU/byval-frame-setup.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
target datalayout = "A5"
%struct.ByValStruct = type { [4 x i32] } %struct.ByValStruct = type { [4 x i32] }
Context not available.
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s5 offset:20{{$}} ; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s5 offset:20{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
define void @void_func_byval_struct(%struct.ByValStruct* byval noalias nocapture align 4 %arg0, %struct.ByValStruct* byval noalias nocapture align 4 %arg1) #1 { define void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1) #1 {
entry: entry:
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
%tmp = load volatile i32, i32* %arrayidx, align 4 %tmp = load volatile i32, i32 addrspace(5)* %arrayidx, align 4
%add = add nsw i32 %tmp, 1 %add = add nsw i32 %tmp, 1
store volatile i32 %add, i32* %arrayidx, align 4 store volatile i32 %add, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
%tmp1 = load volatile i32, i32* %arrayidx2, align 4 %tmp1 = load volatile i32, i32 addrspace(5)* %arrayidx2, align 4
%add3 = add nsw i32 %tmp1, 2 %add3 = add nsw i32 %tmp1, 2
store volatile i32 %add3, i32* %arrayidx2, align 4 store volatile i32 %add3, i32 addrspace(5)* %arrayidx2, align 4
store volatile i32 9, i32 addrspace(1)* null, align 4 store volatile i32 9, i32 addrspace(1)* null, align 4
ret void ret void
} }
Context not available.
; GCN: buffer_load_dword v33, ; GCN: buffer_load_dword v33,
; GCN: s_sub_u32 s32, s32, 0xb00{{$}} ; GCN: s_sub_u32 s32, s32, 0xb00{{$}}
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @void_func_byval_struct_non_leaf(%struct.ByValStruct* byval noalias nocapture align 4 %arg0, %struct.ByValStruct* byval noalias nocapture align 4 %arg1) #1 { define void @void_func_byval_struct_non_leaf(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1) #1 {
entry: entry:
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
%tmp = load volatile i32, i32* %arrayidx, align 4 %tmp = load volatile i32, i32 addrspace(5)* %arrayidx, align 4
%add = add nsw i32 %tmp, 1 %add = add nsw i32 %tmp, 1
store volatile i32 %add, i32* %arrayidx, align 4 store volatile i32 %add, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
%tmp1 = load volatile i32, i32* %arrayidx2, align 4 %tmp1 = load volatile i32, i32 addrspace(5)* %arrayidx2, align 4
%add3 = add nsw i32 %tmp1, 2 %add3 = add nsw i32 %tmp1, 2
call void @external_void_func_void() call void @external_void_func_void()
store volatile i32 %add3, i32* %arrayidx2, align 4 store volatile i32 %add3, i32 addrspace(5)* %arrayidx2, align 4
store volatile i32 9, i32 addrspace(1)* null, align 4 store volatile i32 9, i32 addrspace(1)* null, align 4
ret void ret void
} }
Context not available.
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @call_void_func_byval_struct_func() #0 { define void @call_void_func_byval_struct_func() #0 {
entry: entry:
%arg0 = alloca %struct.ByValStruct, align 4 %arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
%arg1 = alloca %struct.ByValStruct, align 4 %arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
%tmp = bitcast %struct.ByValStruct* %arg0 to i8* %tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.start.p0i8(i64 32, i8 addrspace(5)* %tmp)
%tmp1 = bitcast %struct.ByValStruct* %arg1 to i8* %tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.start.p0i8(i64 32, i8 addrspace(5)* %tmp1)
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
store volatile i32 9, i32* %arrayidx, align 4 store volatile i32 9, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
store volatile i32 13, i32* %arrayidx2, align 4 store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 4
call void @void_func_byval_struct(%struct.ByValStruct* byval nonnull align 4 %arg0, %struct.ByValStruct* byval nonnull align 4 %arg1) call void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.end.p0i8(i64 32, i8 addrspace(5)* %tmp1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.end.p0i8(i64 32, i8 addrspace(5)* %tmp)
ret void ret void
} }
Context not available.
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @call_void_func_byval_struct_kernel() #0 { define amdgpu_kernel void @call_void_func_byval_struct_kernel() #0 {
entry: entry:
%arg0 = alloca %struct.ByValStruct, align 4 %arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
%arg1 = alloca %struct.ByValStruct, align 4 %arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
%tmp = bitcast %struct.ByValStruct* %arg0 to i8* %tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.start.p0i8(i64 32, i8 addrspace(5)* %tmp)
%tmp1 = bitcast %struct.ByValStruct* %arg1 to i8* %tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.start.p0i8(i64 32, i8 addrspace(5)* %tmp1)
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
store volatile i32 9, i32* %arrayidx, align 4 store volatile i32 9, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
store volatile i32 13, i32* %arrayidx2, align 4 store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 4
call void @void_func_byval_struct(%struct.ByValStruct* byval nonnull align 4 %arg0, %struct.ByValStruct* byval nonnull align 4 %arg1) call void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.end.p0i8(i64 32, i8 addrspace(5)* %tmp1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.end.p0i8(i64 32, i8 addrspace(5)* %tmp)
ret void ret void
} }
; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel_no_frame_pointer_elim: ; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel_no_frame_pointer_elim:
define amdgpu_kernel void @call_void_func_byval_struct_kernel_no_frame_pointer_elim() #2 { define amdgpu_kernel void @call_void_func_byval_struct_kernel_no_frame_pointer_elim() #2 {
entry: entry:
%arg0 = alloca %struct.ByValStruct, align 4 %arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
%arg1 = alloca %struct.ByValStruct, align 4 %arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
%tmp = bitcast %struct.ByValStruct* %arg0 to i8* %tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.start.p0i8(i64 32, i8 addrspace(5)* %tmp)
%tmp1 = bitcast %struct.ByValStruct* %arg1 to i8* %tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.start.p0i8(i64 32, i8 addrspace(5)* %tmp1)
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
store volatile i32 9, i32* %arrayidx, align 4 store volatile i32 9, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
store volatile i32 13, i32* %arrayidx2, align 4 store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 4
call void @void_func_byval_struct(%struct.ByValStruct* byval nonnull align 4 %arg0, %struct.ByValStruct* byval nonnull align 4 %arg1) call void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.end.p0i8(i64 32, i8 addrspace(5)* %tmp1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.end.p0i8(i64 32, i8 addrspace(5)* %tmp)
ret void ret void
} }
declare void @external_void_func_void() #0 declare void @external_void_func_void() #0
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #3 declare void @llvm.lifetime.start.p0i8(i64, i8 addrspace(5)* nocapture) #3
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #3 declare void @llvm.lifetime.end.p0i8(i64, i8 addrspace(5)* nocapture) #3
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { noinline norecurse nounwind } attributes #1 = { noinline norecurse nounwind }
Context not available.

test/CodeGen/AMDGPU/call-encoding.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=fiji -d - | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=fiji -d - | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=gfx900 -d - | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=gfx900 -d - | FileCheck -check-prefixes=GCN,GFX9 %s
; XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=hawaii -d - | FileCheck -check-prefixes=GCN,CI %s ; XUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=hawaii -d - | FileCheck -check-prefixes=GCN,CI %s
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64

test/CodeGen/AMDGPU/call-graph-register-usage.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-NOBUG %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-NOBUG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-BUG %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=iceland -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-BUG %s
target datalayout = "A5"
; Make sure to run a GPU with the SGPR allocation bug. ; Make sure to run a GPU with the SGPR allocation bug.
Context not available.
; GCN-LABEL: {{^}}use_stack0: ; GCN-LABEL: {{^}}use_stack0:
; GCN: ScratchSize: 2052 ; GCN: ScratchSize: 2052
define void @use_stack0() #1 { define void @use_stack0() #1 {
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([512 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([512 x i32] addrspace(5)* %alloca) #0
ret void ret void
} }
; GCN-LABEL: {{^}}use_stack1: ; GCN-LABEL: {{^}}use_stack1:
; GCN: ScratchSize: 404 ; GCN: ScratchSize: 404
define void @use_stack1() #1 { define void @use_stack1() #1 {
%alloca = alloca [100 x i32], align 4 %alloca = alloca [100 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([100 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([100 x i32] addrspace(5)* %alloca) #0
ret void ret void
} }
; GCN-LABEL: {{^}}indirect_use_stack: ; GCN-LABEL: {{^}}indirect_use_stack:
; GCN: ScratchSize: 2124 ; GCN: ScratchSize: 2124
define void @indirect_use_stack() #1 { define void @indirect_use_stack() #1 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([16 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([16 x i32] addrspace(5)* %alloca) #0
call void @use_stack0() call void @use_stack0()
ret void ret void
} }
Context not available.
; GCN-LABEL: {{^}}direct_recursion_use_stack: ; GCN-LABEL: {{^}}direct_recursion_use_stack:
; GCN: ScratchSize: 2056 ; GCN: ScratchSize: 2056
define void @direct_recursion_use_stack(i32 %val) #2 { define void @direct_recursion_use_stack(i32 %val) #2 {
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([512 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([512 x i32] addrspace(5)* %alloca) #0
%cmp = icmp eq i32 %val, 0 %cmp = icmp eq i32 %val, 0
br i1 %cmp, label %ret, label %call br i1 %cmp, label %ret, label %call
Context not available.

test/CodeGen/AMDGPU/call-preserved-registers.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare void @external_void_func_void() #0 declare void @external_void_func_void() #0

test/CodeGen/AMDGPU/call_fs.ll

; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG %s
; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s
; EG: .long 257 ; EG: .long 257
; EG: {{^}}call_fs: ; EG: {{^}}call_fs:

test/CodeGen/AMDGPU/callee-frame-setup.ll

; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s
target datalayout = "A5"
; GCN-LABEL: {{^}}callee_no_stack: ; GCN-LABEL: {{^}}callee_no_stack:
; GCN: ; BB#0: ; GCN: ; BB#0:
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_with_stack() #0 { define void @callee_with_stack() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
ret void ret void
} }
Context not available.
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_and_call() #0 { define void @callee_with_stack_and_call() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
call void @external_void_func_void() call void @external_void_func_void()
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
target datalayout = "A5"
; GCN-LABEL: {{^}}use_dispatch_ptr: ; GCN-LABEL: {{^}}use_dispatch_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0
Context not available.
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]] ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]]
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]{{\]}}
define void @use_queue_ptr_addrspacecast() #1 { define void @use_queue_ptr_addrspacecast() #1 {
%asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32 addrspace(4)* %asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32*
store volatile i32 0, i32 addrspace(4)* %asc store volatile i32 0, i32* %asc
ret void ret void
} }
Context not available.
; GCN: ; use s6 ; GCN: ; use s6
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @use_stack_workgroup_id_x() #1 { define void @use_stack_workgroup_id_x() #1 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%val = call i32 @llvm.amdgcn.workgroup.id.x() %val = call i32 @llvm.amdgcn.workgroup.id.x()
call void asm sideeffect "; use $0", "s"(i32 %val) call void asm sideeffect "; use $0", "s"(i32 %val)
ret void ret void
Context not available.
; GCN: ; use s15 ; GCN: ; use s15
; GCN: ; use s16 ; GCN: ; use s16
define void @use_every_sgpr_input() #1 { define void @use_every_sgpr_input() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
Context not available.
; GCN-DAG: s_mov_b32 s8, s16 ; GCN-DAG: s_mov_b32 s8, s16
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 { define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
Context not available.
; GCN: ; use [[SAVE_Y]] ; GCN: ; use [[SAVE_Y]]
; GCN: ; use [[SAVE_Z]] ; GCN: ; use [[SAVE_Z]]
define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 { define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
call void @use_workgroup_id_xyz() call void @use_workgroup_id_xyz()
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
Context not available.

test/CodeGen/AMDGPU/callee-special-input-vgprs.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
target datalayout = "A5"
; GCN-LABEL: {{^}}use_workitem_id_x: ; GCN-LABEL: {{^}}use_workitem_id_x:
; GCN: s_waitcnt ; GCN: s_waitcnt
Context not available.
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32* byval %arg32) #1 { i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval %arg32) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x() %val = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
Context not available.
store volatile i32 %arg29, i32 addrspace(1)* undef store volatile i32 %arg29, i32 addrspace(1)* undef
store volatile i32 %arg30, i32 addrspace(1)* undef store volatile i32 %arg30, i32 addrspace(1)* undef
store volatile i32 %arg31, i32 addrspace(1)* undef store volatile i32 %arg31, i32 addrspace(1)* undef
%private = load volatile i32, i32* %arg32 %private = load volatile i32, i32 addrspace(5)* %arg32
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]], ; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]],
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 { define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 999, i32* %alloca store volatile i32 999, i32 addrspace(5)* %alloca
call void @too_many_args_use_workitem_id_x_byval( call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40, i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80, i32 50, i32 60, i32 70, i32 80,
Context not available.
i32 210, i32 220, i32 230, i32 240, i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280, i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320, i32 290, i32 300, i32 310, i32 320,
i32* %alloca) i32 addrspace(5)* %alloca)
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]], ; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]],
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 999, i32* %alloca store volatile i32 999, i32 addrspace(5)* %alloca
call void @too_many_args_use_workitem_id_x_byval( call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40, i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80, i32 50, i32 60, i32 70, i32 80,
Context not available.
i32 210, i32 220, i32 230, i32 240, i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280, i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320, i32 290, i32 300, i32 310, i32 320,
i32* %alloca) i32 addrspace(5)* %alloca)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/calling-conventions.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Make sure we don't crash or assert on spir_kernel calling convention. ; Make sure we don't crash or assert on spir_kernel calling convention.

test/CodeGen/AMDGPU/captured-frame-index.ll

; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
; GCN-LABEL: {{^}}store_fi_lifetime: ; GCN-LABEL: {{^}}store_fi_lifetime:
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%b = alloca i8 %b = alloca i8, addrspace(5)
call void @llvm.lifetime.start.p0i8(i64 1, i8* %b) call void @llvm.lifetime.start.p0i8(i64 1, i8 addrspace(5)* %b)
store volatile i8* %b, i8* addrspace(1)* undef store volatile i8 addrspace(5)* %b, i8 addrspace(5)* addrspace(1)* undef
call void @llvm.lifetime.end.p0i8(i64 1, i8* %b) call void @llvm.lifetime.end.p0i8(i64 1, i8 addrspace(5)* %b)
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 4{{$}}
; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] ; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]] ; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]]
define amdgpu_kernel void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_lds(float addrspace(5)* addrspace(3)* %ptr) #0 {
%tmp = alloca float %tmp = alloca float, addrspace(5)
store float 4.0, float *%tmp store float 4.0, float addrspace(5)*%tmp
store float* %tmp, float* addrspace(3)* %ptr store float addrspace(5)* %tmp, float addrspace(5)* addrspace(3)* %ptr
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}} ; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]] ; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]]
define amdgpu_kernel void @stored_fi_to_lds_2_small_objects(float* addrspace(3)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_lds_2_small_objects(float addrspace(5)* addrspace(3)* %ptr) #0 {
%tmp0 = alloca float %tmp0 = alloca float, addrspace(5)
%tmp1 = alloca float %tmp1 = alloca float, addrspace(5)
store float 4.0, float* %tmp0 store float 4.0, float addrspace(5)* %tmp0
store float 4.0, float* %tmp1 store float 4.0, float addrspace(5)* %tmp1
store volatile float* %tmp0, float* addrspace(3)* %ptr store volatile float addrspace(5)* %tmp0, float addrspace(5)* addrspace(3)* %ptr
store volatile float* %tmp1, float* addrspace(3)* %ptr store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(3)* %ptr
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}} ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[ZERO]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword [[ZERO]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @stored_fi_to_self() #0 { define amdgpu_kernel void @stored_fi_to_self() #0 {
%tmp = alloca i32* %tmp = alloca i32 addrspace(5)*, addrspace(5)
; Avoid optimizing everything out ; Avoid optimizing everything out
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp
%bitcast = bitcast i32** %tmp to i32* %bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp to i32 addrspace(5)*
store volatile i32* %bitcast, i32** %tmp store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x804{{$}} ; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x804{{$}}
; GCN: buffer_store_dword [[OFFSETK]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:2052{{$}} ; GCN: buffer_store_dword [[OFFSETK]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:2052{{$}}
define amdgpu_kernel void @stored_fi_to_self_offset() #0 { define amdgpu_kernel void @stored_fi_to_self_offset() #0 {
%tmp0 = alloca [512 x i32] %tmp0 = alloca [512 x i32], addrspace(5)
%tmp1 = alloca i32* %tmp1 = alloca i32 addrspace(5)*, addrspace(5)
; Avoid optimizing everything out ; Avoid optimizing everything out
%tmp0.cast = bitcast [512 x i32]* %tmp0 to i32* %tmp0.cast = bitcast [512 x i32] addrspace(5)* %tmp0 to i32 addrspace(5)*
store volatile i32 32, i32* %tmp0.cast store volatile i32 32, i32 addrspace(5)* %tmp0.cast
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp1 store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp1
%bitcast = bitcast i32** %tmp1 to i32* %bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp1 to i32 addrspace(5)*
store volatile i32* %bitcast, i32** %tmp1 store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp1
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}} ; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}}
; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}} ; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}}
define amdgpu_kernel void @stored_fi_to_fi() #0 { define amdgpu_kernel void @stored_fi_to_fi() #0 {
%tmp0 = alloca i32* %tmp0 = alloca i32 addrspace(5)*, addrspace(5)
%tmp1 = alloca i32* %tmp1 = alloca i32 addrspace(5)*, addrspace(5)
%tmp2 = alloca i32* %tmp2 = alloca i32 addrspace(5)*, addrspace(5)
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp0 store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp0
store volatile i32* inttoptr (i32 5678 to i32*), i32** %tmp1 store volatile i32 addrspace(5)* inttoptr (i32 5678 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp1
store volatile i32* inttoptr (i32 9999 to i32*), i32** %tmp2 store volatile i32 addrspace(5)* inttoptr (i32 9999 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp2
%bitcast1 = bitcast i32** %tmp1 to i32* %bitcast1 = bitcast i32 addrspace(5)* addrspace(5)* %tmp1 to i32 addrspace(5)*
%bitcast2 = bitcast i32** %tmp2 to i32* ; at offset 8 %bitcast2 = bitcast i32 addrspace(5)* addrspace(5)* %tmp2 to i32 addrspace(5)* ; at offset 8
store volatile i32* %bitcast1, i32** %tmp2 ; store offset 4 at offset 8 store volatile i32 addrspace(5)* %bitcast1, i32 addrspace(5)* addrspace(5)* %tmp2 ; store offset 4 at offset 8
store volatile i32* %bitcast2, i32** %tmp1 ; store offset 8 at offset 4 store volatile i32 addrspace(5)* %bitcast2, i32 addrspace(5)* addrspace(5)* %tmp1 ; store offset 8 at offset 4
ret void ret void
} }
Context not available.
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @stored_fi_to_global(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_global(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp = alloca float %tmp = alloca float, addrspace(5)
store float 0.0, float *%tmp store float 0.0, float addrspace(5)*%tmp
store float* %tmp, float* addrspace(1)* %ptr store float addrspace(5)* %tmp, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}} ; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}}
; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @stored_fi_to_global_2_small_objects(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_global_2_small_objects(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp0 = alloca float %tmp0 = alloca float, addrspace(5)
%tmp1 = alloca float %tmp1 = alloca float, addrspace(5)
%tmp2 = alloca float %tmp2 = alloca float, addrspace(5)
store volatile float 0.0, float *%tmp0 store volatile float 0.0, float addrspace(5)*%tmp0
store volatile float 0.0, float *%tmp1 store volatile float 0.0, float addrspace(5)*%tmp1
store volatile float 0.0, float *%tmp2 store volatile float 0.0, float addrspace(5)*%tmp2
store volatile float* %tmp1, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(1)* %ptr
store volatile float* %tmp2, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp2, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
Context not available.
; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} ; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}
; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @stored_fi_to_global_huge_frame_offset(i32* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_global_huge_frame_offset(i32 addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp0 = alloca [4096 x i32] %tmp0 = alloca [4096 x i32], addrspace(5)
%tmp1 = alloca [4096 x i32] %tmp1 = alloca [4096 x i32], addrspace(5)
%gep0.tmp0 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 0 %gep0.tmp0 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 0
store volatile i32 0, i32* %gep0.tmp0 store volatile i32 0, i32 addrspace(5)* %gep0.tmp0
%gep1.tmp0 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 4095 %gep1.tmp0 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 4095
store volatile i32 999, i32* %gep1.tmp0 store volatile i32 999, i32 addrspace(5)* %gep1.tmp0
%gep0.tmp1 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 14 %gep0.tmp1 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 14
store i32* %gep0.tmp1, i32* addrspace(1)* %ptr store i32 addrspace(5)* %gep0.tmp1, i32 addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
@g1 = external addrspace(1) global i32* @g1 = external addrspace(1) global i32 addrspace(5)*
; This was leaving a dead node around resulting in failing to select ; This was leaving a dead node around resulting in failing to select
; on the leftover AssertZext's ValueType operand. ; on the leftover AssertZext's ValueType operand.
Context not available.
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 { define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 {
entry: entry:
%b = alloca i32, align 4 %b = alloca i32, align 4, addrspace(5)
%tmp1 = load volatile i32*, i32* addrspace(1)* @g1, align 4 %tmp1 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* @g1, align 4
%arrayidx = getelementptr inbounds i32, i32* %tmp1, i32 %idx %arrayidx = getelementptr inbounds i32, i32 addrspace(5)* %tmp1, i32 %idx
%tmp2 = load i32, i32* %arrayidx, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx, align 4
store volatile i32* %b, i32* addrspace(1)* undef store volatile i32 addrspace(5)* %b, i32 addrspace(5)* addrspace(1)* undef
ret void ret void
} }
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8 addrspace(5)* nocapture) #1
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8 addrspace(5)* nocapture) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
Context not available.

test/CodeGen/AMDGPU/cayman-loop-bug.ll

; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: LOOP_START_DX10 ; CHECK: LOOP_START_DX10

test/CodeGen/AMDGPU/cf-loop-on-constant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -O0 < %s
; GCN-LABEL: {{^}}test_loop: ; GCN-LABEL: {{^}}test_loop:
; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: ; %for.body{{$}} ; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: ; %for.body{{$}}

test/CodeGen/AMDGPU/cf-stack-bug.ll

; RUN: llc -march=r600 -mcpu=redwood -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=BUG64 %s < %t ; RUN: FileCheck --check-prefix=BUG64 %s < %t
; RUN: llc -march=r600 -mcpu=sumo -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=sumo -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=BUG64 %s < %t ; RUN: FileCheck --check-prefix=BUG64 %s < %t
; RUN: llc -march=r600 -mcpu=barts -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=barts -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=BUG64 %s < %t ; RUN: FileCheck --check-prefix=BUG64 %s < %t
; RUN: llc -march=r600 -mcpu=turks -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=turks -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=BUG64 %s < %t ; RUN: FileCheck --check-prefix=BUG64 %s < %t
; RUN: llc -march=r600 -mcpu=caicos -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=caicos -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=BUG64 %s < %t ; RUN: FileCheck --check-prefix=BUG64 %s < %t
; RUN: llc -march=r600 -mcpu=cedar -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cedar -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=BUG32 %s < %t ; RUN: FileCheck --check-prefix=BUG32 %s < %t
; RUN: llc -march=r600 -mcpu=juniper -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=juniper -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=NOBUG %s < %t ; RUN: FileCheck --check-prefix=NOBUG %s < %t
; RUN: llc -march=r600 -mcpu=cypress -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=NOBUG %s < %t ; RUN: FileCheck --check-prefix=NOBUG %s < %t
; RUN: llc -march=r600 -mcpu=cayman -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
; RUN: FileCheck --check-prefix=NOBUG %s < %t ; RUN: FileCheck --check-prefix=NOBUG %s < %t
target datalayout = "A5"
; REQUIRES: asserts ; REQUIRES: asserts

test/CodeGen/AMDGPU/cf_end.ll

; RUN: llc < %s -march=r600 -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG %s
; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG %s
; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM %s
; EG: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80] ; EG: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80]
; CM: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88] ; CM: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88]

test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll

; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-CIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown-amdgiz -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-CIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-CIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown-amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-CIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown-amdgiz -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s
; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-scalarize-global-loads=false -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
target datalayout = "A5"
; OPT-LABEL: @test_no_sink_flat_small_offset_i32( ; OPT-LABEL: @test_no_sink_flat_small_offset_i32(
; OPT-CIVI: getelementptr i32, i32 addrspace(4)* %in ; OPT-CIVI: getelementptr i32, i32* %in
; OPT-CIVI: br i1 ; OPT-CIVI: br i1
; OPT-CIVI-NOT: ptrtoint ; OPT-CIVI-NOT: ptrtoint
; OPT-GFX9: br ; OPT-GFX9: br
; OPT-GFX9: %sunkaddr = getelementptr i8, i8 addrspace(4)* %0, i64 28 ; OPT-GFX9: %sunkaddr = getelementptr i8, i8* %0, i64 28
; OPT-GFX9: %1 = bitcast i8 addrspace(4)* %sunkaddr to i32 addrspace(4)* ; OPT-GFX9: %1 = bitcast i8* %sunkaddr to i32*
; OPT-GFX9: load i32, i32 addrspace(4)* %1 ; OPT-GFX9: load i32, i32* %1
; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32: ; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32:
; GCN: flat_load_dword ; GCN: flat_load_dword
; GCN: {{^}}BB0_2: ; GCN: {{^}}BB0_2:
define amdgpu_kernel void @test_no_sink_flat_small_offset_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { define amdgpu_kernel void @test_no_sink_flat_small_offset_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(4)* %in.gep %tmp1 = load i32, i32* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
Context not available.
} }
; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_global_i32( ; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_global_i32(
; OPT: getelementptr i32, i32 addrspace(4)* %out, ; OPT: getelementptr i32, i32* %out,
; rOPT-CI-NOT: getelementptr ; rOPT-CI-NOT: getelementptr
; OPT: br i1 ; OPT: br i1
Context not available.
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32: ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32:
; CI: buffer_load_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28 ; CI: buffer_load_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28
define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_global_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_global_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%cast = addrspacecast i32 addrspace(4)* %in.gep to i32 addrspace(1)* %cast = addrspacecast i32* %in.gep to i32 addrspace(1)*
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
Context not available.
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
Context not available.
} }
; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_constant_i32( ; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_constant_i32(
; OPT: getelementptr i32, i32 addrspace(4)* %out, ; OPT: getelementptr i32, i32* %out,
; OPT-CI-NOT: getelementptr ; OPT-CI-NOT: getelementptr
; OPT: br i1 ; OPT: br i1
Context not available.
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32: ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32:
; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%cast = addrspacecast i32 addrspace(4)* %in.gep to i32 addrspace(2)* %cast = addrspacecast i32* %in.gep to i32 addrspace(2)*
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
Context not available.
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
Context not available.
} }
; OPT-LABEL: @test_sink_flat_small_max_flat_offset( ; OPT-LABEL: @test_sink_flat_small_max_flat_offset(
; OPT-CIVI: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095 ; OPT-CIVI: %in.gep = getelementptr i8, i8* %in, i64 4095
; OPT-CIVI: br ; OPT-CIVI: br
; OPT-CIVI-NOT: getelementptr ; OPT-CIVI-NOT: getelementptr
; OPT-CIVI: load i8, i8 addrspace(4)* %in.gep ; OPT-CIVI: load i8, i8* %in.gep
; OPT-GFX9: br ; OPT-GFX9: br
; OPT-GFX9: %sunkaddr = getelementptr i8, i8 addrspace(4)* %in, i64 4095 ; OPT-GFX9: %sunkaddr = getelementptr i8, i8* %in, i64 4095
; OPT-GFX9: load i8, i8 addrspace(4)* %sunkaddr ; OPT-GFX9: load i8, i8* %sunkaddr
; GCN-LABEL: {{^}}test_sink_flat_small_max_flat_offset: ; GCN-LABEL: {{^}}test_sink_flat_small_max_flat_offset:
; GFX9: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
; CIVI: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} ; CIVI: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @test_sink_flat_small_max_flat_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in) #1 { define amdgpu_kernel void @test_sink_flat_small_max_flat_offset(i32* %out, i8* %in) #1 {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 %out.gep = getelementptr i32, i32* %out, i32 1024
%in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095 %in.gep = getelementptr i8, i8* %in, i64 4095
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i8, i8 addrspace(4)* %in.gep %tmp1 = load i8, i8* %in.gep
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp2, %if ], [ 0, %entry ] %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
Context not available.
} }
; OPT-LABEL: @test_sink_flat_small_max_plus_1_flat_offset( ; OPT-LABEL: @test_sink_flat_small_max_plus_1_flat_offset(
; OPT: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4096 ; OPT: %in.gep = getelementptr i8, i8* %in, i64 4096
; OPT: br ; OPT: br
; OPT-NOT: getelementptr ; OPT-NOT: getelementptr
; OPT: load i8, i8 addrspace(4)* %in.gep ; OPT: load i8, i8* %in.gep
; GCN-LABEL: {{^}}test_sink_flat_small_max_plus_1_flat_offset: ; GCN-LABEL: {{^}}test_sink_flat_small_max_plus_1_flat_offset:
; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @test_sink_flat_small_max_plus_1_flat_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in) #1 { define amdgpu_kernel void @test_sink_flat_small_max_plus_1_flat_offset(i32* %out, i8* %in) #1 {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 99999 %out.gep = getelementptr i32, i32* %out, i64 99999
%in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4096 %in.gep = getelementptr i8, i8* %in, i64 4096
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i8, i8 addrspace(4)* %in.gep %tmp1 = load i8, i8* %in.gep
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp2, %if ], [ 0, %entry ] %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
Context not available.
} }
; OPT-LABEL: @test_no_sink_flat_reg_offset( ; OPT-LABEL: @test_no_sink_flat_reg_offset(
; OPT: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 %reg ; OPT: %in.gep = getelementptr i8, i8* %in, i64 %reg
; OPT: br ; OPT: br
; OPT-NOT: getelementptr ; OPT-NOT: getelementptr
; OPT: load i8, i8 addrspace(4)* %in.gep ; OPT: load i8, i8* %in.gep
; GCN-LABEL: {{^}}test_no_sink_flat_reg_offset: ; GCN-LABEL: {{^}}test_no_sink_flat_reg_offset:
; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @test_no_sink_flat_reg_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in, i64 %reg) #1 { define amdgpu_kernel void @test_no_sink_flat_reg_offset(i32* %out, i8* %in, i64 %reg) #1 {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 %out.gep = getelementptr i32, i32* %out, i32 1024
%in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 %reg %in.gep = getelementptr i8, i8* %in, i64 %reg
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i8, i8 addrspace(4)* %in.gep %tmp1 = load i8, i8* %in.gep
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp2, %if ], [ 0, %entry ] %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
Context not available.

test/CodeGen/AMDGPU/cgp-bitfield-extract.ll

; RUN: opt -S -mtriple=amdgcn-- -codegenprepare < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -codegenprepare < %s | FileCheck -check-prefix=OPT %s
; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -codegenprepare < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -codegenprepare < %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; This particular case will actually be worse in terms of code size ; This particular case will actually be worse in terms of code size
; from sinking into both. ; from sinking into both.

test/CodeGen/AMDGPU/clamp-modifier.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s
; GCN-LABEL: {{^}}v_clamp_add_src_f32: ; GCN-LABEL: {{^}}v_clamp_add_src_f32:
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]

test/CodeGen/AMDGPU/clamp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s
; GCN-LABEL: {{^}}v_clamp_f32: ; GCN-LABEL: {{^}}v_clamp_f32:
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]

test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i1 @llvm.amdgcn.class.f32(float, i32) declare i1 @llvm.amdgcn.class.f32(float, i32)

test/CodeGen/AMDGPU/coalescer-subrange-crash.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; ;
; This testcase used to cause the following crash: ; This testcase used to cause the following crash:
; ;

test/CodeGen/AMDGPU/coalescer_remat.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -mtriple=amdgcn-- -o - %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs -mtriple=amdgcn---amdgiz -o - %s | FileCheck %s
declare float @llvm.fma.f32(float, float, float) declare float @llvm.fma.f32(float, float, float)

test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll

; RUN: opt -mtriple=amdgcn-- -codegenprepare -S < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn---amdgiz -codegenprepare -S < %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-LLC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-LLC %s
; OPT-LABEL: @test( ; OPT-LABEL: @test(
; OPT: mul nsw i32 ; OPT: mul nsw i32

test/CodeGen/AMDGPU/collapse-endcf.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}simple_nested_if: ; GCN-LABEL: {{^}}simple_nested_if:
; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]] ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
Context not available.
br i1 %tmp3, label %bb4, label %bb10 br i1 %tmp3, label %bb4, label %bb10
bb4: ; preds = %bb2 bb4: ; preds = %bb2
%tmp6 = load float, float* undef %tmp6 = load float, float addrspace(5)* undef
%tmp7 = fcmp olt float %tmp6, 0.0 %tmp7 = fcmp olt float %tmp6, 0.0
br i1 %tmp7, label %bb8, label %Flow br i1 %tmp7, label %bb8, label %Flow
Context not available.
br label %bb1 br label %bb1
bb12: ; preds = %bb10 bb12: ; preds = %bb10
store volatile <4 x float> %tmp11, <4 x float>* undef, align 16 store volatile <4 x float> %tmp11, <4 x float> addrspace(5)* undef, align 16
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/combine-and-sext-bool.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}and_i1_sext_bool: ; GCN-LABEL: {{^}}and_i1_sext_bool:
; GCN: v_cmp_{{gt|le}}_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_cmp_{{gt|le}}_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}

test/CodeGen/AMDGPU/combine-cond-add-sub.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}add1: ; GCN-LABEL: {{^}}add1:
; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}

test/CodeGen/AMDGPU/combine-ftrunc.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}combine_ftrunc_frint_f64: ; GCN-LABEL: {{^}}combine_ftrunc_frint_f64:
; GCN: v_rndne_f64_e32 [[RND:v\[[0-9:]+\]]], ; GCN: v_rndne_f64_e32 [[RND:v\[[0-9:]+\]]],

test/CodeGen/AMDGPU/commute-compares.ll

; RUN: llc -march=amdgcn -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
target datalayout = "A5"
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
Context not available.
; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]] ; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]]
define amdgpu_kernel void @commute_frameindex(i32 addrspace(1)* nocapture %out) #0 { define amdgpu_kernel void @commute_frameindex(i32 addrspace(1)* nocapture %out) #0 {
entry: entry:
%stack0 = alloca i32 %stack0 = alloca i32, addrspace(5)
%ptr0 = load volatile i32*, i32* addrspace(1)* undef %ptr0 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* undef
%eq = icmp eq i32* %ptr0, %stack0 %eq = icmp eq i32 addrspace(5)* %ptr0, %stack0
%ext = zext i1 %eq to i32 %ext = zext i1 %eq to i32
store volatile i32 %ext, i32 addrspace(1)* %out store volatile i32 %ext, i32 addrspace(1)* %out
ret void ret void
Context not available.

test/CodeGen/AMDGPU/commute-shifts.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}main: ; GCN-LABEL: {{^}}main:
; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} ; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

test/CodeGen/AMDGPU/commute_modifiers.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1

test/CodeGen/AMDGPU/complex-folding.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; CHECK: {{^}}main: ; CHECK: {{^}}main:
; CHECK-NOT: MOV ; CHECK-NOT: MOV

test/CodeGen/AMDGPU/concat_vectors.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_concat_v1i32: ; FUNC-LABEL: {{^}}test_concat_v1i32:
; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF

test/CodeGen/AMDGPU/constant-fold-mi-operands.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}fold_mi_v_and_0: ; GCN-LABEL: {{^}}fold_mi_v_and_0:
; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}

test/CodeGen/AMDGPU/control-flow-optnone.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; optnone disables AMDGPUAnnotateUniformValues, so no branch is known ; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
; to be uniform during instruction selection. The custom selection for ; to be uniform during instruction selection. The custom selection for

test/CodeGen/AMDGPU/convergent-inlineasm.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
; GCN-LABEL: {{^}}convergent_inlineasm: ; GCN-LABEL: {{^}}convergent_inlineasm:

test/CodeGen/AMDGPU/copy-illegal-type.ll

; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone

test/CodeGen/AMDGPU/copy-to-reg.ll

; RUN: llc -march=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-promote-alloca -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca -verify-machineinstrs < %s
target datalayout = "A5"
; Test that CopyToReg instructions don't have non-register operands prior ; Test that CopyToReg instructions don't have non-register operands prior
; to being emitted. ; to being emitted.
Context not available.
; CHECK-LABEL: {{^}}copy_to_reg_frameindex: ; CHECK-LABEL: {{^}}copy_to_reg_frameindex:
define amdgpu_kernel void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
entry: entry:
%alloca = alloca [16 x i32] %alloca = alloca [16 x i32], addrspace(5)
br label %loop br label %loop
loop: loop:
%inc = phi i32 [0, %entry], [%inc.i, %loop] %inc = phi i32 [0, %entry], [%inc.i, %loop]
%ptr = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %inc %ptr = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %inc
store i32 %inc, i32* %ptr store i32 %inc, i32 addrspace(5)* %ptr
%inc.i = add i32 %inc, 1 %inc.i = add i32 %inc, 1
%cnd = icmp uge i32 %inc.i, 16 %cnd = icmp uge i32 %inc.i, 16
br i1 %cnd, label %done, label %loop br i1 %cnd, label %done, label %loop
done: done:
%tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 0 %tmp0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
%tmp1 = load i32, i32* %tmp0 %tmp1 = load i32, i32 addrspace(5)* %tmp0
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/ctlz.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone
declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone

test/CodeGen/AMDGPU/ctlz_zero_undef.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone

test/CodeGen/AMDGPU/ctpop.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare i32 @llvm.ctpop.i32(i32) nounwind readnone declare i32 @llvm.ctpop.i32(i32) nounwind readnone
declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone

test/CodeGen/AMDGPU/ctpop64.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone declare i32 @llvm.r600.read.tidig.x() nounwind readnone

test/CodeGen/AMDGPU/cttz_zero_undef.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-NOSDWA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-NOSDWA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-SDWA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-SDWA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone
declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone

test/CodeGen/AMDGPU/cube.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare float @llvm.amdgcn.cubeid(float, float, float) #0 declare float @llvm.amdgcn.cubeid(float, float, float) #0
declare float @llvm.amdgcn.cubesc(float, float, float) #0 declare float @llvm.amdgcn.cubesc(float, float, float) #0

test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone

test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1 declare float @llvm.floor.f32(float) #1

test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1 declare float @llvm.floor.f32(float) #1

test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; We are only checking that instruction selection can succeed in this case. This ; We are only checking that instruction selection can succeed in this case. This
; cut down test results in no instructions, but that's fine. ; cut down test results in no instructions, but that's fine.

test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; Test for a bug where DAGCombiner::ReassociateOps() was creating adds ; Test for a bug where DAGCombiner::ReassociateOps() was creating adds
; with offset in the first operand and base pointers in the second. ; with offset in the first operand and base pointers in the second.

test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; This test is for a bug in ; This test is for a bug in
; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where ; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where

test/CodeGen/AMDGPU/debug.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; Test for a crash in the custom assembly dump code. ; Test for a crash in the custom assembly dump code.

test/CodeGen/AMDGPU/default-fp-mode.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_default_si: ; GCN-LABEL: {{^}}test_default_si:
; GCN: FloatMode: 192 ; GCN: FloatMode: 192

test/CodeGen/AMDGPU/disconnected-predset-break-bug.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; PRED_SET* instructions must be tied to any instruction that uses their ; PRED_SET addrspace(5)* instructions must be tied to any instruction that uses their
; result. This tests that there are no instructions between the PRED_SET* ; result. This tests that there are no instructions between the PRED_SET addrspace(5)*
; and the PREDICATE_BREAK in this loop. ; and the PREDICATE_BREAK in this loop.
; CHECK: {{^}}loop_ge: ; CHECK: {{^}}loop_ge:

test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; The memory operand was dropped from the buffer_load_dword_offset ; The memory operand was dropped from the buffer_load_dword_offset
; when replaced with the addr64 during operand legalization, resulting ; when replaced with the addr64 during operand legalization, resulting

test/CodeGen/AMDGPU/ds-combine-large-stride.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
; GCN-LABEL: ds_read32_combine_stride_400: ; GCN-LABEL: ds_read32_combine_stride_400:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
Context not available.
; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
define amdgpu_kernel void @ds_read32_combine_stride_400(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) { define amdgpu_kernel void @ds_read32_combine_stride_400(float addrspace(3)* nocapture readonly %arg, float addrspace(5)*nocapture %arg1) {
bb: bb:
%tmp = load float, float addrspace(3)* %arg, align 4 %tmp = load float, float addrspace(3)* %arg, align 4
%tmp2 = fadd float %tmp, 0.000000e+00 %tmp2 = fadd float %tmp, 0.000000e+00
Context not available.
%tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 700 %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
%tmp22 = load float, float addrspace(3)* %tmp21, align 4 %tmp22 = load float, float addrspace(3)* %tmp21, align 4
%tmp23 = fadd float %tmp20, %tmp22 %tmp23 = fadd float %tmp20, %tmp22
store float %tmp23, float *%arg1, align 4 store float %tmp23, float addrspace(5)*%arg1, align 4
ret void ret void
} }
Context not available.
; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
define amdgpu_kernel void @ds_read32_combine_stride_400_back(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) { define amdgpu_kernel void @ds_read32_combine_stride_400_back(float addrspace(3)* nocapture readonly %arg, float addrspace(5)*nocapture %arg1) {
bb: bb:
%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
%tmp2 = load float, float addrspace(3)* %tmp, align 4 %tmp2 = load float, float addrspace(3)* %tmp, align 4
Context not available.
%tmp21 = fadd float %tmp18, %tmp20 %tmp21 = fadd float %tmp18, %tmp20
%tmp22 = load float, float addrspace(3)* %arg, align 4 %tmp22 = load float, float addrspace(3)* %arg, align 4
%tmp23 = fadd float %tmp21, %tmp22 %tmp23 = fadd float %tmp21, %tmp22
store float %tmp23, float *%arg1, align 4 store float %tmp23, float addrspace(5)*%arg1, align 4
ret void ret void
} }
Context not available.
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224
define amdgpu_kernel void @ds_read32_combine_stride_8192(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) { define amdgpu_kernel void @ds_read32_combine_stride_8192(float addrspace(3)* nocapture readonly %arg, float addrspace(5)*nocapture %arg1) {
bb: bb:
%tmp = load float, float addrspace(3)* %arg, align 4 %tmp = load float, float addrspace(3)* %arg, align 4
%tmp2 = fadd float %tmp, 0.000000e+00 %tmp2 = fadd float %tmp, 0.000000e+00
Context not available.
%tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 14336 %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 14336
%tmp22 = load float, float addrspace(3)* %tmp21, align 4 %tmp22 = load float, float addrspace(3)* %tmp21, align 4
%tmp23 = fadd float %tmp20, %tmp22 %tmp23 = fadd float %tmp20, %tmp22
store float %tmp23, float *%arg1, align 4 store float %tmp23, float addrspace(5)*%arg1, align 4
ret void ret void
} }
Context not available.
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:32 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:32
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:32 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:32
define amdgpu_kernel void @ds_read32_combine_stride_8192_shifted(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) { define amdgpu_kernel void @ds_read32_combine_stride_8192_shifted(float addrspace(3)* nocapture readonly %arg, float addrspace(5)*nocapture %arg1) {
bb: bb:
%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
%tmp2 = load float, float addrspace(3)* %tmp, align 4 %tmp2 = load float, float addrspace(3)* %tmp, align 4
Context not available.
%tmp16 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10242 %tmp16 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10242
%tmp17 = load float, float addrspace(3)* %tmp16, align 4 %tmp17 = load float, float addrspace(3)* %tmp16, align 4
%tmp18 = fadd float %tmp15, %tmp17 %tmp18 = fadd float %tmp15, %tmp17
store float %tmp18, float *%arg1, align 4 store float %tmp18, float addrspace(5)*%arg1, align 4
ret void ret void
} }
Context not available.
; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150
; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250
; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:50 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:50
define amdgpu_kernel void @ds_read64_combine_stride_400(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) { define amdgpu_kernel void @ds_read64_combine_stride_400(double addrspace(3)* nocapture readonly %arg, double addrspace(5)*nocapture %arg1) {
bb: bb:
%tmp = load double, double addrspace(3)* %arg, align 8 %tmp = load double, double addrspace(3)* %arg, align 8
%tmp2 = fadd double %tmp, 0.000000e+00 %tmp2 = fadd double %tmp, 0.000000e+00
Context not available.
%tmp21 = getelementptr inbounds double, double addrspace(3)* %arg, i32 350 %tmp21 = getelementptr inbounds double, double addrspace(3)* %arg, i32 350
%tmp22 = load double, double addrspace(3)* %tmp21, align 8 %tmp22 = load double, double addrspace(3)* %tmp21, align 8
%tmp23 = fadd double %tmp20, %tmp22 %tmp23 = fadd double %tmp20, %tmp22
store double %tmp23, double *%arg1, align 8 store double %tmp23, double addrspace(5)*%arg1, align 8
ret void ret void
} }
Context not available.
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:16 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:16
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:16 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:16
define amdgpu_kernel void @ds_read64_combine_stride_8192_shifted(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) { define amdgpu_kernel void @ds_read64_combine_stride_8192_shifted(double addrspace(3)* nocapture readonly %arg, double addrspace(5)*nocapture %arg1) {
bb: bb:
%tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1 %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
%tmp2 = load double, double addrspace(3)* %tmp, align 8 %tmp2 = load double, double addrspace(3)* %tmp, align 8
Context not available.
%tmp16 = getelementptr inbounds double, double addrspace(3)* %arg, i32 5121 %tmp16 = getelementptr inbounds double, double addrspace(3)* %arg, i32 5121
%tmp17 = load double, double addrspace(3)* %tmp16, align 8 %tmp17 = load double, double addrspace(3)* %tmp16, align 8
%tmp18 = fadd double %tmp15, %tmp17 %tmp18 = fadd double %tmp15, %tmp17
store double %tmp18, double *%arg1, align 8 store double %tmp18, double addrspace(5)*%arg1, align 8
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare void @llvm.amdgcn.s.barrier() #1 declare void @llvm.amdgcn.s.barrier() #1

test/CodeGen/AMDGPU/ds-sub-offset.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0

test/CodeGen/AMDGPU/ds_read2.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
; FIXME: We don't get cases where the address was an SGPR because we ; FIXME: We don't get cases where the address was an SGPR because we
; get a copy to the address register for each one. ; get a copy to the address register for each one.

test/CodeGen/AMDGPU/ds_read2_offset_order.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4

test/CodeGen/AMDGPU/ds_read2_superreg.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI %s
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4
@lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4 @lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4

test/CodeGen/AMDGPU/ds_read2st64.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4
@lds.f64 = addrspace(3) global [512 x double] undef, align 8 @lds.f64 = addrspace(3) global [512 x double] undef, align 8
Context not available.
ret void ret void
} }
; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff ; The maximum is not the usual 0xff because 0xff addrspace(5)* 8 addrspace(5)* 64 > 0xffff
; SI-LABEL: @simple_read2st64_f64_max_offset ; SI-LABEL: @simple_read2st64_f64_max_offset
; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127 ; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127
; SI: s_waitcnt lgkmcnt(0) ; SI: s_waitcnt lgkmcnt(0)
Context not available.
ret void ret void
} }
; The stride of 8 elements is 8 * 8 bytes. We need to make sure the ; The stride of 8 elements is 8 addrspace(5)* 8 bytes. We need to make sure the
; stride in elements, not bytes, is a multiple of 64. ; stride in elements, not bytes, is a multiple of 64.
; SI-LABEL: @byte_size_only_divisible_64_read2_f64 ; SI-LABEL: @byte_size_only_divisible_64_read2_f64
Context not available.

test/CodeGen/AMDGPU/ds_write2.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4
@lds.f64 = addrspace(3) global [512 x double] undef, align 8 @lds.f64 = addrspace(3) global [512 x double] undef, align 8

test/CodeGen/AMDGPU/ds_write2st64.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4

test/CodeGen/AMDGPU/early-if-convert-cost.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Most of these cases that don't trigger because of broken cost ; FIXME: Most of these cases that don't trigger because of broken cost
; heuristics. Should not need -stress-early-ifcvt ; heuristics. Should not need -stress-early-ifcvt

test/CodeGen/AMDGPU/early-if-convert.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; XUN: llc -march=amdgcn -mcpu=tonga -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: This leaves behind a now unnecessary and with exec ; FIXME: This leaves behind a now unnecessary and with exec

test/CodeGen/AMDGPU/early-inline-alias.ll

; RUN: opt -mtriple=amdgcn-- -O1 -S -inline-threshold=1 %s | FileCheck %s ; RUN: opt -mtriple=amdgcn---amdgiz -O1 -S -inline-threshold=1 %s | FileCheck %s
; CHECK: @add1alias = alias i32 (i32), i32 (i32)* @add1 ; CHECK: @add1alias = alias i32 (i32), i32 (i32)* @add1
; CHECK: @add1alias2 = alias i32 (i32), i32 (i32)* @add1 ; CHECK: @add1alias2 = alias i32 (i32), i32 (i32)* @add1

test/CodeGen/AMDGPU/early-inline.ll

; RUN: opt -mtriple=amdgcn-- -O1 -S -inline-threshold=1 -amdgpu-early-inline-all %s | FileCheck %s ; RUN: opt -mtriple=amdgcn---amdgiz -O1 -S -inline-threshold=1 -amdgpu-early-inline-all %s | FileCheck %s
@c_alias = alias i32 (i32), i32 (i32)* @callee @c_alias = alias i32 (i32), i32 (i32)* @callee

test/CodeGen/AMDGPU/elf-header.ll

; RUN: llc -march=r600 -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s
; RUN: llc -mtriple=r600-- -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s ; RUN: llc -mtriple=r600---amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s
; RUN: llc -mtriple=r600-amd- -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s ; RUN: llc -mtriple=r600-amd--amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s
; RUN: llc -mtriple=r600-amd-unknown -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s ; RUN: llc -mtriple=r600-amd-unknown-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s
; RUN: llc -mtriple=r600-unknown-unknown -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s ; RUN: llc -mtriple=r600-unknown-unknown-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=R600 --check-prefix=R600-OSABI-NONE %s
; RUN: llc -march=amdgcn -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s
; RUN: llc -mtriple=amdgcn-- -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s ; RUN: llc -mtriple=amdgcn---amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s
; RUN: llc -mtriple=amdgcn-amd- -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s
; RUN: llc -mtriple=amdgcn-amd-unknown -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s ; RUN: llc -mtriple=amdgcn-amd-unknown-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s
; RUN: llc -mtriple=amdgcn-unknown-unknown -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s ; RUN: llc -mtriple=amdgcn-unknown-unknown-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-NONE %s
; RUN: llc -mtriple=amdgcn--amdhsa -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-HSA %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-HSA %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-HSA %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-HSA %s
; RUN: llc -mtriple=amdgcn-unknown-amdhsa -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-HSA %s ; RUN: llc -mtriple=amdgcn-unknown-amdhsa-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-HSA %s
; RUN: llc -mtriple=amdgcn--amdpal -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-PAL %s ; RUN: llc -mtriple=amdgcn--amdpal-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-PAL %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-PAL %s ; RUN: llc -mtriple=amdgcn-amd-amdpal-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-PAL %s
; RUN: llc -mtriple=amdgcn-unknown-amdpal -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-PAL %s ; RUN: llc -mtriple=amdgcn-unknown-amdpal-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-PAL %s
; RUN: llc -mtriple=amdgcn--mesa3d -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-MESA3D %s ; RUN: llc -mtriple=amdgcn--mesa3d-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-MESA3D %s
; RUN: llc -mtriple=amdgcn-amd-mesa3d -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-MESA3D %s ; RUN: llc -mtriple=amdgcn-amd-mesa3d-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-MESA3D %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-MESA3D %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -filetype=obj < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=GCN --check-prefix=GCN-OSABI-MESA3D %s
; R600: Format: ELF32-amdgpu ; R600: Format: ELF32-amdgpu
; R600: Arch: r600 ; R600: Arch: r600

test/CodeGen/AMDGPU/elf.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -march=amdgcn -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s
; RUN: llc < %s -march=amdgcn -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -march=amdgcn -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
; Test that we don't try to produce a COFF file on windows ; Test that we don't try to produce a COFF file on windows
; RUN: llc < %s -mtriple=amdgcn-pc-mingw -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -mtriple=amdgcn-pc-mingw-amdgiz -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s
; ELF: Format: ELF64-amdgpu ; ELF: Format: ELF64-amdgpu
; ELF: OS/ABI: SystemV (0x0) ; ELF: OS/ABI: SystemV (0x0)

test/CodeGen/AMDGPU/elf.r600.ll

; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s
; ELF: Format: ELF32-amdgpu ; ELF: Format: ELF32-amdgpu
; ELF: Name: .AMDGPU.config ; ELF: Name: .AMDGPU.config

test/CodeGen/AMDGPU/else.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}else_no_execfix: ; CHECK-LABEL: {{^}}else_no_execfix:
; CHECK: ; %Flow ; CHECK: ; %Flow

test/CodeGen/AMDGPU/empty-function.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; Make sure we don't assert on empty functions ; Make sure we don't assert on empty functions

test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll

; RUN: llc -march=amdgcn -enable-no-signed-zeros-fp-math=0 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -enable-no-signed-zeros-fp-math=0 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE %s
; RUN: llc -march=amdgcn -enable-no-signed-zeros-fp-math=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -enable-no-signed-zeros-fp-math=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s
; RUN: llc -march=amdgcn -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/endcf-loop-header.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck %s
; This tests that the llvm.SI.end.cf intrinsic is not inserted into the ; This tests that the llvm.SI.end.cf intrinsic is not inserted into the
; loop block. This intrinsic will be lowered to s_or_b64 by the code ; loop block. This intrinsic will be lowered to s_or_b64 by the code

test/CodeGen/AMDGPU/exceed-max-sgprs.ll

; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: error: scalar registers limit of 104 exceeded (106) in use_too_many_sgprs_tahiti ; ERROR: error: scalar registers limit of 104 exceeded (106) in use_too_many_sgprs_tahiti
define amdgpu_kernel void @use_too_many_sgprs_tahiti() #0 { define amdgpu_kernel void @use_too_many_sgprs_tahiti() #0 {

test/CodeGen/AMDGPU/extend-bit-ops-i16.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN
; GCN-LABEL: and_zext: ; GCN-LABEL: and_zext:
; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}

test/CodeGen/AMDGPU/extload-private.ll

; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
target datalayout = "A5"
; FUNC-LABEL: {{^}}load_i8_sext_private: ; FUNC-LABEL: {{^}}load_i8_sext_private:
; SI: buffer_load_sbyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_sbyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i8_sext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i8_sext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i8 %tmp0 = alloca i8, addrspace(5)
%tmp1 = load i8, i8* %tmp0 %tmp1 = load i8, i8 addrspace(5)* %tmp0
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
Context not available.
; SI: buffer_load_ubyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_ubyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i8_zext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i8_zext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i8 %tmp0 = alloca i8, addrspace(5)
%tmp1 = load i8, i8* %tmp0 %tmp1 = load i8, i8 addrspace(5)* %tmp0
%tmp2 = zext i8 %tmp1 to i32 %tmp2 = zext i8 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
Context not available.
; SI: buffer_load_sshort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_sshort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i16_sext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i16_sext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i16 %tmp0 = alloca i16, addrspace(5)
%tmp1 = load i16, i16* %tmp0 %tmp1 = load i16, i16 addrspace(5)* %tmp0
%tmp2 = sext i16 %tmp1 to i32 %tmp2 = sext i16 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
Context not available.
; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i16 %tmp0 = alloca i16, addrspace(5)
%tmp1 = load volatile i16, i16* %tmp0 %tmp1 = load volatile i16, i16 addrspace(5)* %tmp0
%tmp2 = zext i16 %tmp1 to i32 %tmp2 = zext i16 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
Context not available.

test/CodeGen/AMDGPU/extload.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=CI-HSA -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=CI-HSA -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FIXME: This seems to not ever actually become an extload ; FIXME: This seems to not ever actually become an extload
; FUNC-LABEL: {{^}}global_anyext_load_i8: ; FUNC-LABEL: {{^}}global_anyext_load_i8:

test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32: ; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32:
; GCN: buffer_load_dword ; GCN: buffer_load_dword

test/CodeGen/AMDGPU/extractelt-to-trunc.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/fabs.f16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; DAGCombiner will transform: ; DAGCombiner will transform:
; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF)) ; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))

test/CodeGen/AMDGPU/fabs.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/fabs.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; DAGCombiner will transform: ; DAGCombiner will transform:

test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll

; RUN: llc -march=amdgcn -mattr=+fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s
; RUN: llc -march=amdgcn -mattr=-fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s
; RUN: llc -march=amdgcn -mattr=+fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FASTFMA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FASTFMA %s
; RUN: llc -march=amdgcn -mattr=-fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SLOWFMA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SLOWFMA %s
; FIXME: This should also fold when fma is actually fast if an FMA ; FIXME: This should also fold when fma is actually fast if an FMA
; exists in the original program. ; exists in the original program.

test/CodeGen/AMDGPU/fadd.f16.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}fadd_f16 ; GCN-LABEL: {{^}}fadd_f16
; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]] ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fadd.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
; FUNC-LABEL: {{^}}fadd_f32: ; FUNC-LABEL: {{^}}fadd_f32:
; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W

test/CodeGen/AMDGPU/fadd64.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}v_fadd_f64: ; CHECK-LABEL: {{^}}v_fadd_f64:
; CHECK: v_add_f64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}} ; CHECK: v_add_f64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}

test/CodeGen/AMDGPU/fcanonicalize-elimination.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=-fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GCN-FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs -mattr=-fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GCN-FLUSH %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=-fp32-denormals,+fp-exceptions < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-EXCEPT -check-prefix=VI -check-prefix=GCN-FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs -mattr=-fp32-denormals,+fp-exceptions < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-EXCEPT -check-prefix=VI -check-prefix=GCN-FLUSH %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs -mattr=+fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX9-DENORM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs -mattr=+fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX9-DENORM %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs -mattr=-fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GCN-FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs -mattr=-fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GCN-FLUSH %s
; GCN-LABEL: {{^}}test_no_fold_canonicalize_loaded_value_f32: ; GCN-LABEL: {{^}}test_no_fold_canonicalize_loaded_value_f32:
; GCN-FLUSH: v_mul_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}} ; GCN-FLUSH: v_mul_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}

test/CodeGen/AMDGPU/fcanonicalize.f16.ll

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
declare half @llvm.fabs.f16(half) #0 declare half @llvm.fabs.f16(half) #0
declare half @llvm.canonicalize.f16(half) #0 declare half @llvm.canonicalize.f16(half) #0

test/CodeGen/AMDGPU/fcanonicalize.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0
declare float @llvm.canonicalize.f32(float) #0 declare float @llvm.canonicalize.f32(float) #0

test/CodeGen/AMDGPU/fceil.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare float @llvm.ceil.f32(float) nounwind readnone declare float @llvm.ceil.f32(float) nounwind readnone
declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone

test/CodeGen/AMDGPU/fceil64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
target datalayout = "A5"
declare double @llvm.ceil.f64(double) nounwind readnone declare double @llvm.ceil.f64(double) nounwind readnone
declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone

test/CodeGen/AMDGPU/fcmp-cnd.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;Not checking arguments 2 and 3 to CNDE, because they may change between ;Not checking arguments 2 and 3 to CNDE, because they may change between
;registers and literal.x depending on what the optimizer does. ;registers and literal.x depending on what the optimizer does.

test/CodeGen/AMDGPU/fcmp-cnde-int-args.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; This test checks a bug in R600TargetLowering::LowerSELECT_CC where the ; This test checks a bug in R600TargetLowering::LowerSELECT_CC where the
; chance to optimize the fcmp + select instructions to SET* was missed ; chance to optimize the fcmp + select instructions to SET addrspace(5)* was missed
; due to the fact that the operands to fcmp and select had different types ; due to the fact that the operands to fcmp and select had different types
; CHECK: SET{{[A-Z]+}}_DX10 ; CHECK: SET{{[A-Z]+}}_DX10

test/CodeGen/AMDGPU/fcmp.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}fcmp_f16_lt ; GCN-LABEL: {{^}}fcmp_f16_lt
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fcmp.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; CHECK: {{^}}fcmp_sext: ; CHECK: {{^}}fcmp_sext:
; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

test/CodeGen/AMDGPU/fcmp64.ll

; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: {{^}}flt_f64: ; CHECK-LABEL: {{^}}flt_f64:
; CHECK: v_cmp_nge_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} ; CHECK: v_cmp_nge_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}

test/CodeGen/AMDGPU/fconst64.ll

; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s
; CHECK: {{^}}fconst_f64: ; CHECK: {{^}}fconst_f64:
; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0x40140000 ; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0x40140000

test/CodeGen/AMDGPU/fcopysign.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX8 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX8 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
declare half @llvm.copysign.f16(half, half) declare half @llvm.copysign.f16(half, half)
declare float @llvm.copysign.f32(float, float) declare float @llvm.copysign.f32(float, float)

test/CodeGen/AMDGPU/fcopysign.f32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare float @llvm.copysign.f32(float, float) nounwind readnone declare float @llvm.copysign.f32(float, float) nounwind readnone
declare <2 x float> @llvm.copysign.v2f32(<2 x float>, <2 x float>) nounwind readnone declare <2 x float> @llvm.copysign.v2f32(<2 x float>, <2 x float>) nounwind readnone

test/CodeGen/AMDGPU/fcopysign.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
declare double @llvm.copysign.f64(double, double) nounwind readnone declare double @llvm.copysign.f64(double, double) nounwind readnone
declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind readnone

test/CodeGen/AMDGPU/fdiv.f16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=+fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -mattr=+fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Make sure fdiv is promoted to f32. ; Make sure fdiv is promoted to f32.

test/CodeGen/AMDGPU/fdiv.f64.ll

; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
; GCN-LABEL: {{^}}fdiv_f64: ; GCN-LABEL: {{^}}fdiv_f64:

test/CodeGen/AMDGPU/fdiv.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; These tests check that fdiv is expanded correctly and also test that the ; These tests check that fdiv is expanded correctly and also test that the
; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate ; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate

test/CodeGen/AMDGPU/fence-barrier.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
target datalayout = "A5"
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
Context not available.
; GCN-NEXT: s_barrier ; GCN-NEXT: s_barrier
; GCN: flat_store_dword ; GCN: flat_store_dword
define amdgpu_kernel void @test_local(i32 addrspace(1)*) { define amdgpu_kernel void @test_local(i32 addrspace(1)*) {
%2 = alloca i32 addrspace(1)*, align 4 %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %0, i32 addrspace(1)** %2, align 4 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
%3 = call i32 @llvm.amdgcn.workitem.id.x() %3 = call i32 @llvm.amdgcn.workitem.id.x()
%4 = zext i32 %3 to i64 %4 = zext i32 %3 to i64
%5 = icmp eq i64 %4, 0 %5 = icmp eq i64 %4, 0
Context not available.
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
fence syncscope("workgroup") acquire fence syncscope("workgroup") acquire
%8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4 %8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4
%9 = load i32 addrspace(1)*, i32 addrspace(1)** %2, align 4 %9 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%10 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %10 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
%11 = call i32 @llvm.amdgcn.workitem.id.x() %11 = call i32 @llvm.amdgcn.workitem.id.x()
%12 = call i32 @llvm.amdgcn.workgroup.id.x() %12 = call i32 @llvm.amdgcn.workgroup.id.x()
Context not available.
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GCN-NEXT: s_barrier ; GCN-NEXT: s_barrier
define amdgpu_kernel void @test_global(i32 addrspace(1)*) { define amdgpu_kernel void @test_global(i32 addrspace(1)*) {
%2 = alloca i32 addrspace(1)*, align 4 %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
%3 = alloca i32, align 4 %3 = alloca i32, align 4, addrspace(5)
store i32 addrspace(1)* %0, i32 addrspace(1)** %2, align 4 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
store i32 0, i32* %3, align 4 store i32 0, i32 addrspace(5)* %3, align 4
br label %4 br label %4
; <label>:4: ; preds = %58, %1 ; <label>:4: ; preds = %58, %1
%5 = load i32, i32* %3, align 4 %5 = load i32, i32 addrspace(5)* %3, align 4
%6 = sext i32 %5 to i64 %6 = sext i32 %5 to i64
%7 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %7 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
%8 = call i32 @llvm.amdgcn.workitem.id.x() %8 = call i32 @llvm.amdgcn.workitem.id.x()
Context not available.
%36 = add i64 %35, %33 %36 = add i64 %35, %33
%37 = add i64 %36, 2184 %37 = add i64 %36, 2184
%38 = trunc i64 %37 to i32 %38 = trunc i64 %37 to i32
%39 = load i32 addrspace(1)*, i32 addrspace(1)** %2, align 4 %39 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%40 = load i32, i32* %3, align 4 %40 = load i32, i32 addrspace(5)* %3, align 4
%41 = sext i32 %40 to i64 %41 = sext i32 %40 to i64
%42 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %42 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
%43 = call i32 @llvm.amdgcn.workitem.id.x() %43 = call i32 @llvm.amdgcn.workitem.id.x()
Context not available.
br label %58 br label %58
; <label>:58: ; preds = %22 ; <label>:58: ; preds = %22
%59 = load i32, i32* %3, align 4 %59 = load i32, i32 addrspace(5)* %3, align 4
%60 = add nsw i32 %59, 1 %60 = add nsw i32 %59, 1
store i32 %60, i32* %3, align 4 store i32 %60, i32 addrspace(5)* %3, align 4
br label %4 br label %4
; <label>:61: ; preds = %4 ; <label>:61: ; preds = %4
Context not available.
; GCN-NEXT: s_barrier ; GCN-NEXT: s_barrier
; GCN: flat_store_dword ; GCN: flat_store_dword
define amdgpu_kernel void @test_global_local(i32 addrspace(1)*) { define amdgpu_kernel void @test_global_local(i32 addrspace(1)*) {
%2 = alloca i32 addrspace(1)*, align 4 %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %0, i32 addrspace(1)** %2, align 4 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
%3 = load i32 addrspace(1)*, i32 addrspace(1)** %2, align 4 %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
%5 = call i32 @llvm.amdgcn.workitem.id.x() %5 = call i32 @llvm.amdgcn.workitem.id.x()
%6 = call i32 @llvm.amdgcn.workgroup.id.x() %6 = call i32 @llvm.amdgcn.workgroup.id.x()
Context not available.
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
fence syncscope("workgroup") acquire fence syncscope("workgroup") acquire
%24 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4 %24 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
%25 = load i32 addrspace(1)*, i32 addrspace(1)** %2, align 4 %25 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%26 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %26 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
%27 = call i32 @llvm.amdgcn.workitem.id.x() %27 = call i32 @llvm.amdgcn.workitem.id.x()
%28 = call i32 @llvm.amdgcn.workgroup.id.x() %28 = call i32 @llvm.amdgcn.workgroup.id.x()
Context not available.

test/CodeGen/AMDGPU/fetch-limits.r600.ll

; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=r600 | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=rs880 | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=rv670 | FileCheck %s
; R600 supports 8 fetches in a clause ; R600 supports 8 fetches in a clause
; CHECK: {{^}}fetch_limits_r600: ; CHECK: {{^}}fetch_limits_r600:

test/CodeGen/AMDGPU/fetch-limits.r700+.ll

; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=rv710 | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=rv730 | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=rv770 | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cedar | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=sumo | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=juniper | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cypress | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=barts | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=turks | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=caicos | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=caicos | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s
; r700+ supports 16 fetches in a clause ; r700+ supports 16 fetches in a clause
; CHECK: {{^}}fetch_limits_r700: ; CHECK: {{^}}fetch_limits_r700:

test/CodeGen/AMDGPU/ffloor.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
declare double @llvm.fabs.f64(double %Val) declare double @llvm.fabs.f64(double %Val)
declare double @llvm.floor.f64(double) nounwind readnone declare double @llvm.floor.f64(double) nounwind readnone

test/CodeGen/AMDGPU/ffloor.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}floor_f32: ; FUNC-LABEL: {{^}}floor_f32:
; SI: v_floor_f32_e32 ; SI: v_floor_f32_e32

test/CodeGen/AMDGPU/flat-address-space.ll

; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=CHECK,CIVI %s ; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d-amdgiz -mcpu=bonaire < %s | FileCheck -check-prefixes=CHECK,CIVI %s
; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI %s ; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d-amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI %s
; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,HSA %s ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,HSA %s
; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,HSA,GFX9 %s ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,HSA,GFX9 %s
target datalayout = "A5"
; Disable optimizations in case there are optimizations added that ; Disable optimizations in case there are optimizations added that
; specialize away generic pointer accesses. ; specialize away generic pointer accesses.
Context not available.
; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]] ; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]]
define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
store volatile i32 %x, i32 addrspace(4)* %fptr, align 4 store volatile i32 %x, i32* %fptr, align 4
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i64: ; CHECK-LABEL: {{^}}store_flat_i64:
; CHECK: flat_store_dwordx2 ; CHECK: flat_store_dwordx2
define amdgpu_kernel void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 { define amdgpu_kernel void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 {
%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* %fptr = addrspacecast i64 addrspace(1)* %gptr to i64*
store volatile i64 %x, i64 addrspace(4)* %fptr, align 8 store volatile i64 %x, i64* %fptr, align 8
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_v4i32: ; CHECK-LABEL: {{^}}store_flat_v4i32:
; CHECK: flat_store_dwordx4 ; CHECK: flat_store_dwordx4
define amdgpu_kernel void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 { define amdgpu_kernel void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 {
%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32>*
store volatile <4 x i32> %x, <4 x i32> addrspace(4)* %fptr, align 16 store volatile <4 x i32> %x, <4 x i32>* %fptr, align 16
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_trunc_i16: ; CHECK-LABEL: {{^}}store_flat_trunc_i16:
; CHECK: flat_store_short ; CHECK: flat_store_short
define amdgpu_kernel void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
%y = trunc i32 %x to i16 %y = trunc i32 %x to i16
store volatile i16 %y, i16 addrspace(4)* %fptr, align 2 store volatile i16 %y, i16* %fptr, align 2
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_trunc_i8: ; CHECK-LABEL: {{^}}store_flat_trunc_i8:
; CHECK: flat_store_byte ; CHECK: flat_store_byte
define amdgpu_kernel void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
%y = trunc i32 %x to i8 %y = trunc i32 %x to i8
store volatile i8 %y, i8 addrspace(4)* %fptr, align 2 store volatile i8 %y, i8* %fptr, align 2
ret void ret void
} }
Context not available.
; CHECK-LABEL: load_flat_i32: ; CHECK-LABEL: load_flat_i32:
; CHECK: flat_load_dword ; CHECK: flat_load_dword
define amdgpu_kernel void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
%fload = load volatile i32, i32 addrspace(4)* %fptr, align 4 %fload = load volatile i32, i32* %fptr, align 4
store i32 %fload, i32 addrspace(1)* %out, align 4 store i32 %fload, i32 addrspace(1)* %out, align 4
ret void ret void
} }
Context not available.
; CHECK-LABEL: load_flat_i64: ; CHECK-LABEL: load_flat_i64:
; CHECK: flat_load_dwordx2 ; CHECK: flat_load_dwordx2
define amdgpu_kernel void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* %fptr = addrspacecast i64 addrspace(1)* %gptr to i64*
%fload = load volatile i64, i64 addrspace(4)* %fptr, align 8 %fload = load volatile i64, i64* %fptr, align 8
store i64 %fload, i64 addrspace(1)* %out, align 8 store i64 %fload, i64 addrspace(1)* %out, align 8
ret void ret void
} }
Context not available.
; CHECK-LABEL: load_flat_v4i32: ; CHECK-LABEL: load_flat_v4i32:
; CHECK: flat_load_dwordx4 ; CHECK: flat_load_dwordx4
define amdgpu_kernel void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32>*
%fload = load volatile <4 x i32>, <4 x i32> addrspace(4)* %fptr, align 32 %fload = load volatile <4 x i32>, <4 x i32>* %fptr, align 32
store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8 store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
ret void ret void
} }
Context not available.
; CHECK-LABEL: sextload_flat_i8: ; CHECK-LABEL: sextload_flat_i8:
; CHECK: flat_load_sbyte ; CHECK: flat_load_sbyte
define amdgpu_kernel void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
%fload = load volatile i8, i8 addrspace(4)* %fptr, align 4 %fload = load volatile i8, i8* %fptr, align 4
%ext = sext i8 %fload to i32 %ext = sext i8 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
Context not available.
; CHECK-LABEL: zextload_flat_i8: ; CHECK-LABEL: zextload_flat_i8:
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
define amdgpu_kernel void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
%fload = load volatile i8, i8 addrspace(4)* %fptr, align 4 %fload = load volatile i8, i8* %fptr, align 4
%ext = zext i8 %fload to i32 %ext = zext i8 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
Context not available.
; CHECK-LABEL: sextload_flat_i16: ; CHECK-LABEL: sextload_flat_i16:
; CHECK: flat_load_sshort ; CHECK: flat_load_sshort
define amdgpu_kernel void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
%fload = load volatile i16, i16 addrspace(4)* %fptr, align 4 %fload = load volatile i16, i16* %fptr, align 4
%ext = sext i16 %fload to i32 %ext = sext i16 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
Context not available.
; CHECK-LABEL: zextload_flat_i16: ; CHECK-LABEL: zextload_flat_i16:
; CHECK: flat_load_ushort ; CHECK: flat_load_ushort
define amdgpu_kernel void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
%fload = load volatile i16, i16 addrspace(4)* %fptr, align 4 %fload = load volatile i16, i16* %fptr, align 4
%ext = zext i16 %fload to i32 %ext = zext i16 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
Context not available.
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
define amdgpu_kernel void @flat_scratch_unaligned_load() { define amdgpu_kernel void @flat_scratch_unaligned_load() {
%scratch = alloca i32 %scratch = alloca i32, addrspace(5)
%fptr = addrspacecast i32* %scratch to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(5)* %scratch to i32*
%ld = load volatile i32, i32 addrspace(4)* %fptr, align 1 %ld = load volatile i32, i32* %fptr, align 1
ret void ret void
} }
Context not available.
; CHECK: flat_store_byte ; CHECK: flat_store_byte
; CHECK: flat_store_byte ; CHECK: flat_store_byte
define amdgpu_kernel void @flat_scratch_unaligned_store() { define amdgpu_kernel void @flat_scratch_unaligned_store() {
%scratch = alloca i32 %scratch = alloca i32, addrspace(5)
%fptr = addrspacecast i32* %scratch to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(5)* %scratch to i32*
store volatile i32 0, i32 addrspace(4)* %fptr, align 1 store volatile i32 0, i32* %fptr, align 1
ret void ret void
} }
Context not available.
; HSA: flat_load_dword ; HSA: flat_load_dword
; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr ; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
define amdgpu_kernel void @flat_scratch_multidword_load() { define amdgpu_kernel void @flat_scratch_multidword_load() {
%scratch = alloca <2 x i32> %scratch = alloca <2 x i32>, addrspace(5)
%fptr = addrspacecast <2 x i32>* %scratch to <2 x i32> addrspace(4)* %fptr = addrspacecast <2 x i32> addrspace(5)* %scratch to <2 x i32>*
%ld = load volatile <2 x i32>, <2 x i32> addrspace(4)* %fptr %ld = load volatile <2 x i32>, <2 x i32>* %fptr
ret void ret void
} }
Context not available.
; HSA: flat_store_dword ; HSA: flat_store_dword
; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr ; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
define amdgpu_kernel void @flat_scratch_multidword_store() { define amdgpu_kernel void @flat_scratch_multidword_store() {
%scratch = alloca <2 x i32> %scratch = alloca <2 x i32>, addrspace(5)
%fptr = addrspacecast <2 x i32>* %scratch to <2 x i32> addrspace(4)* %fptr = addrspacecast <2 x i32> addrspace(5)* %scratch to <2 x i32>*
store volatile <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* %fptr store volatile <2 x i32> zeroinitializer, <2 x i32>* %fptr
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i8_max_offset: ; CHECK-LABEL: {{^}}store_flat_i8_max_offset:
; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}} ; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}}
define amdgpu_kernel void @store_flat_i8_max_offset(i8 addrspace(4)* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_max_offset(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4095 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
store volatile i8 %x, i8 addrspace(4)* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i8_max_offset_p1: ; CHECK-LABEL: {{^}}store_flat_i8_max_offset_p1:
; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @store_flat_i8_max_offset_p1(i8 addrspace(4)* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_max_offset_p1(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4096 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
store volatile i8 %x, i8 addrspace(4)* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i8_neg_offset: ; CHECK-LABEL: {{^}}store_flat_i8_neg_offset:
; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @store_flat_i8_neg_offset(i8 addrspace(4)* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_neg_offset(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 -2 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
store volatile i8 %x, i8 addrspace(4)* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_max_offset: ; CHECK-LABEL: {{^}}load_flat_i8_max_offset:
; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}}
; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
define amdgpu_kernel void @load_flat_i8_max_offset(i8 addrspace(4)* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_max_offset(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4095 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
%val = load volatile i8, i8 addrspace(4)* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1: ; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1:
; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8 addrspace(4)* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4096 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
%val = load volatile i8, i8 addrspace(4)* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_neg_offset: ; CHECK-LABEL: {{^}}load_flat_i8_neg_offset:
; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @load_flat_i8_neg_offset(i8 addrspace(4)* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_neg_offset(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 -2 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
%val = load volatile i8, i8 addrspace(4)* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-DEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-DEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-NODEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-NODEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefix=HSA-NOADDR64 -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=HSA-NOADDR64 -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=NOHSA-DEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn---amdgiz -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=NOHSA-DEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=NOHSA-NODEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn---amdgiz -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=NOHSA-NODEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefix=NOHSA-NOADDR64 -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=NOHSA-NOADDR64 -check-prefix=ALL %s
target datalayout = "A5"
; There are no stack objects even though flat is used by default, so ; There are no stack objects even though flat is used by default, so
Context not available.
; NOHSA-NOADDR64: flat_store_dword ; NOHSA-NOADDR64: flat_store_dword
define amdgpu_kernel void @test_addr64(i32 addrspace(1)* %out) { define amdgpu_kernel void @test_addr64(i32 addrspace(1)* %out) {
entry: entry:
%out.addr = alloca i32 addrspace(1)*, align 4 %out.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %out, i32 addrspace(1)** %out.addr, align 4 store i32 addrspace(1)* %out, i32 addrspace(1)* addrspace(5)* %out.addr, align 4
%ld0 = load i32 addrspace(1)*, i32 addrspace(1)** %out.addr, align 4 %ld0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %out.addr, align 4
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0
store i32 1, i32 addrspace(1)* %arrayidx, align 4 store i32 1, i32 addrspace(1)* %arrayidx, align 4
%ld1 = load i32 addrspace(1)*, i32 addrspace(1)** %out.addr, align 4 %ld1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %out.addr, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1
store i32 2, i32 addrspace(1)* %arrayidx1, align 4 store i32 2, i32 addrspace(1)* %arrayidx1, align 4
Context not available.

test/CodeGen/AMDGPU/flat-scratch-reg.ll

; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-CI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa-amdgiz -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-XNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa-amdgiz -mcpu=carrizo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-XNACK -check-prefix=GCN %s
; GCN-LABEL: {{^}}no_vcc_no_flat: ; GCN-LABEL: {{^}}no_vcc_no_flat:
; HSA-CI: is_xnack_enabled = 0 ; HSA-CI: is_xnack_enabled = 0

test/CodeGen/AMDGPU/flat_atomics.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}atomic_add_i32_offset: ; GCN-LABEL: {{^}}atomic_add_i32_offset:
; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_add_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_max_offset: ; GCN-LABEL: {{^}}atomic_add_i32_max_offset:
; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:4092{{$}} ; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:4092{{$}}
define amdgpu_kernel void @atomic_add_i32_max_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_max_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 1023 %gep = getelementptr i32, i32* %out, i32 1023
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_max_offset_p1: ; GCN-LABEL: {{^}}atomic_add_i32_max_offset_p1:
; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_add_i32_max_offset_p1(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_max_offset_p1(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 %gep = getelementptr i32, i32* %out, i32 1024
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_add_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset:
; CIVI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32: ; GCN-LABEL: {{^}}atomic_add_i32:
; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_add_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile add i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile add i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_ret: ; GCN-LABEL: {{^}}atomic_add_i32_ret:
; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_add_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile add i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile add i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_addr64: ; GCN-LABEL: {{^}}atomic_add_i32_addr64:
; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_add_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile add i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile add i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64:
; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile add i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile add i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_offset: ; GCN-LABEL: {{^}}atomic_and_i32_offset:
; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_and_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_and_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_and_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset:
; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32: ; GCN-LABEL: {{^}}atomic_and_i32:
; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_and_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_and_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile and i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile and i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_ret: ; GCN-LABEL: {{^}}atomic_and_i32_ret:
; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_and_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile and i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile and i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_addr64: ; GCN-LABEL: {{^}}atomic_and_i32_addr64:
; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_and_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile and i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile and i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64:
; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile and i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile and i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_offset: ; GCN-LABEL: {{^}}atomic_sub_i32_offset:
; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_sub_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_sub_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_sub_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset:
; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32: ; GCN-LABEL: {{^}}atomic_sub_i32:
; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_sub_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_sub_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile sub i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile sub i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_ret: ; GCN-LABEL: {{^}}atomic_sub_i32_ret:
; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_sub_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile sub i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile sub i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_addr64: ; GCN-LABEL: {{^}}atomic_sub_i32_addr64:
; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_sub_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile sub i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile sub i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64:
; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile sub i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile sub i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_offset: ; GCN-LABEL: {{^}}atomic_max_i32_offset:
; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_max_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_max_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_max_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset:
; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32: ; GCN-LABEL: {{^}}atomic_max_i32:
; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_max_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_max_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile max i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile max i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_ret: ; GCN-LABEL: {{^}}atomic_max_i32_ret:
; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_max_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile max i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile max i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_addr64: ; GCN-LABEL: {{^}}atomic_max_i32_addr64:
; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_max_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile max i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile max i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64:
; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile max i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile max i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_offset: ; GCN-LABEL: {{^}}atomic_umax_i32_offset:
; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umax_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umax_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umax_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset:
; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32: ; GCN-LABEL: {{^}}atomic_umax_i32:
; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umax_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umax_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile umax i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umax i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_ret: ; GCN-LABEL: {{^}}atomic_umax_i32_ret:
; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umax_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile umax i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umax i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_addr64: ; GCN-LABEL: {{^}}atomic_umax_i32_addr64:
; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umax_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umax i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umax i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64:
; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umax i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umax i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_offset: ; GCN-LABEL: {{^}}atomic_min_i32_offset:
; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_min_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_min_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_min_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset:
; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32: ; GCN-LABEL: {{^}}atomic_min_i32:
; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_min_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_min_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile min i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile min i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_ret: ; GCN-LABEL: {{^}}atomic_min_i32_ret:
; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_min_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile min i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile min i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_addr64: ; GCN-LABEL: {{^}}atomic_min_i32_addr64:
; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_min_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile min i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile min i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64:
; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile min i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile min i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_offset: ; GCN-LABEL: {{^}}atomic_umin_i32_offset:
; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umin_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umin_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umin_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset:
; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32: ; GCN-LABEL: {{^}}atomic_umin_i32:
; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umin_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umin_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile umin i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umin i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_ret: ; GCN-LABEL: {{^}}atomic_umin_i32_ret:
; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umin_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile umin i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umin i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_addr64: ; GCN-LABEL: {{^}}atomic_umin_i32_addr64:
; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umin_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umin i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umin i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64:
; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]{{$}}
define amdgpu_kernel void @atomic_umin_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umin i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umin i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_offset: ; GCN-LABEL: {{^}}atomic_or_i32_offset:
; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_or_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_or_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_or_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset:
; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32: ; GCN-LABEL: {{^}}atomic_or_i32:
; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_or_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_or_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile or i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile or i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_ret: ; GCN-LABEL: {{^}}atomic_or_i32_ret:
; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_or_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile or i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile or i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_addr64: ; GCN-LABEL: {{^}}atomic_or_i32_addr64:
; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_or_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile or i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile or i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64:
; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile or i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile or i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_offset: ; GCN-LABEL: {{^}}atomic_xchg_i32_offset:
; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xchg_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset:
; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32: ; GCN-LABEL: {{^}}atomic_xchg_i32:
; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_xchg_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_ret: ; GCN-LABEL: {{^}}atomic_xchg_i32_ret:
; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i32_addr64:
; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_xchg_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xchg i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64:
; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xchg i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
Context not available.
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset:
; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}} ; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(4)* %out, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32* %out, i32* %out2, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset:
; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}} ; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32* %out, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32:
; GCN: flat_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32(i32 addrspace(4)* %out, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32(i32* %out, i32 %in, i32 %old) {
entry: entry:
%val = cmpxchg volatile i32 addrspace(4)* %out, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %out, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret:
; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc ; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32* %out, i32* %out2, i32 %in, i32 %old) {
entry: entry:
%val = cmpxchg volatile i32 addrspace(4)* %out, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %out, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64:
; GCN: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32* %out, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = cmpxchg volatile i32 addrspace(4)* %ptr, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %ptr, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64:
; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = cmpxchg volatile i32 addrspace(4)* %ptr, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %ptr, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_offset: ; GCN-LABEL: {{^}}atomic_xor_i32_offset:
; CIVI: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CIVI: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GFX9: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xor_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xor_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xor_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset:
; CIVI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32: ; GCN-LABEL: {{^}}atomic_xor_i32:
; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_xor_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xor_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xor i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xor i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_ret: ; GCN-LABEL: {{^}}atomic_xor_i32_ret:
; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xor_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile xor i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xor i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_addr64: ; GCN-LABEL: {{^}}atomic_xor_i32_addr64:
; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_xor_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xor i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xor i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64:
; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xor i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xor i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
Context not available.
; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i32_offset(i32* %in, i32* %out) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %in, i32 4 %gep = getelementptr i32, i32* %in, i32 4
%val = load atomic i32, i32 addrspace(4)* %gep seq_cst, align 4 %val = load atomic i32, i32* %gep seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i32: ; GCN-LABEL: {{^}}atomic_load_i32:
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i32(i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in seq_cst, align 4 %val = load atomic i32, i32* %in seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32_addr64_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i32_addr64_offset(i32* %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %in, i64 %index %ptr = getelementptr i32, i32* %in, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = load atomic i32, i32 addrspace(4)* %gep seq_cst, align 4 %val = load atomic i32, i32* %gep seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i32_addr64: ; GCN-LABEL: {{^}}atomic_load_i32_addr64:
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32_addr64(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i32_addr64(i32* %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %in, i64 %index %ptr = getelementptr i32, i32* %in, i64 %index
%val = load atomic i32, i32 addrspace(4)* %ptr seq_cst, align 4 %val = load atomic i32, i32* %ptr seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32_offset: ; GCN-LABEL: {{^}}atomic_store_i32_offset:
; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}} ; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32* %out) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
store atomic i32 %in, i32 addrspace(4)* %gep seq_cst, align 4 store atomic i32 %in, i32* %gep seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32: ; GCN-LABEL: {{^}}atomic_store_i32:
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_store_i32(i32 %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i32(i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4 store atomic i32 %in, i32* %out seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset:
; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}} ; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
store atomic i32 %in, i32 addrspace(4)* %gep seq_cst, align 4 store atomic i32 %in, i32* %gep seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32_addr64: ; GCN-LABEL: {{^}}atomic_store_i32_addr64:
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
store atomic i32 %in, i32 addrspace(4)* %ptr seq_cst, align 4 store atomic i32 %in, i32* %ptr seq_cst, align 4
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/flat_atomics_i64.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}atomic_add_i64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_offset:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @atomic_add_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_add_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_add_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @atomic_add_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64: ; GCN-LABEL: {{^}}atomic_add_i64:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_add_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_add_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret: ; GCN-LABEL: {{^}}atomic_add_i64_ret:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_add_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_addr64: ; GCN-LABEL: {{^}}atomic_add_i64_addr64:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_add_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_offset: ; GCN-LABEL: {{^}}atomic_and_i64_offset:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_and_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_and_i64_ret_offset:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_and_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i64_addr64_offset:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64_offset:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64: ; GCN-LABEL: {{^}}atomic_and_i64:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_and_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret: ; GCN-LABEL: {{^}}atomic_and_i64_ret:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_and_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_addr64: ; GCN-LABEL: {{^}}atomic_and_i64_addr64:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_offset:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_sub_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_ret_offset:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_sub_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_addr64_offset:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64_offset:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64: ; GCN-LABEL: {{^}}atomic_sub_i64:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_sub_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret: ; GCN-LABEL: {{^}}atomic_sub_i64_ret:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_sub_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_addr64: ; GCN-LABEL: {{^}}atomic_sub_i64_addr64:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_offset: ; GCN-LABEL: {{^}}atomic_max_i64_offset:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_max_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_max_i64_ret_offset:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_max_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i64_addr64_offset:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64_offset:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64: ; GCN-LABEL: {{^}}atomic_max_i64:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_max_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret: ; GCN-LABEL: {{^}}atomic_max_i64_ret:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_max_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_addr64: ; GCN-LABEL: {{^}}atomic_max_i64_addr64:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_offset:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umax_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_ret_offset:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umax_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64_offset:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64: ; GCN-LABEL: {{^}}atomic_umax_i64:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umax_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret: ; GCN-LABEL: {{^}}atomic_umax_i64_ret:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umax_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_addr64: ; GCN-LABEL: {{^}}atomic_umax_i64_addr64:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_offset: ; GCN-LABEL: {{^}}atomic_min_i64_offset:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_min_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_min_i64_ret_offset:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_min_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i64_addr64_offset:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64_offset:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64: ; GCN-LABEL: {{^}}atomic_min_i64:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_min_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret: ; GCN-LABEL: {{^}}atomic_min_i64_ret:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_min_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_addr64: ; GCN-LABEL: {{^}}atomic_min_i64_addr64:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_offset:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umin_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_ret_offset:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umin_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_addr64_offset:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64_offset:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64: ; GCN-LABEL: {{^}}atomic_umin_i64:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umin_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret: ; GCN-LABEL: {{^}}atomic_umin_i64_ret:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umin_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_addr64: ; GCN-LABEL: {{^}}atomic_umin_i64_addr64:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_offset: ; GCN-LABEL: {{^}}atomic_or_i64_offset:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_or_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_or_i64_ret_offset:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_or_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i64_addr64_offset:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64_offset:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64: ; GCN-LABEL: {{^}}atomic_or_i64:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_or_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret: ; GCN-LABEL: {{^}}atomic_or_i64_ret:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_or_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_addr64: ; GCN-LABEL: {{^}}atomic_or_i64_addr64:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_offset:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret_offset:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_addr64_offset:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64_offset:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64: ; GCN-LABEL: {{^}}atomic_xchg_i64:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i64_addr64:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_offset:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xor_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_ret_offset:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xor_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_addr64_offset:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64_offset:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64: ; GCN-LABEL: {{^}}atomic_xor_i64:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xor_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret: ; GCN-LABEL: {{^}}atomic_xor_i64_ret:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xor_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_addr64: ; GCN-LABEL: {{^}}atomic_xor_i64_addr64:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_offset: ; GCN-LABEL: {{^}}atomic_load_i64_offset:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64_offset(i64 addrspace(4)* %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i64_offset(i64* %in, i64* %out) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %in, i64 4 %gep = getelementptr i64, i64* %in, i64 4
%val = load atomic i64, i64 addrspace(4)* %gep seq_cst, align 8 %val = load atomic i64, i64* %gep seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64: ; GCN-LABEL: {{^}}atomic_load_i64:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64(i64 addrspace(4)* %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i64(i64* %in, i64* %out) {
entry: entry:
%val = load atomic i64, i64 addrspace(4)* %in seq_cst, align 8 %val = load atomic i64, i64* %in seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_load_i64_addr64_offset:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64_addr64_offset(i64 addrspace(4)* %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i64_addr64_offset(i64* %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %in, i64 %index %ptr = getelementptr i64, i64* %in, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = load atomic i64, i64 addrspace(4)* %gep seq_cst, align 8 %val = load atomic i64, i64* %gep seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_addr64: ; GCN-LABEL: {{^}}atomic_load_i64_addr64:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64_addr64(i64 addrspace(4)* %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i64_addr64(i64* %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %in, i64 %index %ptr = getelementptr i64, i64* %in, i64 %index
%val = load atomic i64, i64 addrspace(4)* %ptr seq_cst, align 8 %val = load atomic i64, i64* %ptr seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64_offset: ; GCN-LABEL: {{^}}atomic_store_i64_offset:
; GCN: flat_store_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_store_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_store_i64_offset(i64 %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i64_offset(i64 %in, i64* %out) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
store atomic i64 %in, i64 addrspace(4)* %gep seq_cst, align 8 store atomic i64 %in, i64* %gep seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64: ; GCN-LABEL: {{^}}atomic_store_i64:
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}] ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}]
define amdgpu_kernel void @atomic_store_i64(i64 %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i64(i64 %in, i64* %out) {
entry: entry:
store atomic i64 %in, i64 addrspace(4)* %out seq_cst, align 8 store atomic i64 %in, i64* %out seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_store_i64_addr64_offset:
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
store atomic i64 %in, i64 addrspace(4)* %gep seq_cst, align 8 store atomic i64 %in, i64* %gep seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64_addr64: ; GCN-LABEL: {{^}}atomic_store_i64_addr64:
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
store atomic i64 %in, i64 addrspace(4)* %ptr seq_cst, align 8 store atomic i64 %in, i64* %ptr seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_offset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_offset(i64 addrspace(4)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_offset(i64* %out, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_soffset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_soffset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64 addrspace(4)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64* %out, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 9000 %gep = getelementptr i64, i64* %out, i64 9000
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64* %out, i64* %out2, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64(i64 addrspace(4)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64(i64* %out, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64 addrspace(4)* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64* %out, i64* %out2, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64 addrspace(4)* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%val = cmpxchg volatile i64 addrspace(4)* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%val = cmpxchg volatile i64 addrspace(4)* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }

test/CodeGen/AMDGPU/fma-combine.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-NOFMA -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-NOFMA -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-NOFMA -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-NOFMA -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast -enable-no-infs-fp-math -enable-unsafe-fp-math -mattr=+fp32-denormals < %s | FileCheck -check-prefix=SI-FMA -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -fp-contract=fast -enable-no-infs-fp-math -enable-unsafe-fp-math -mattr=+fp32-denormals < %s | FileCheck -check-prefix=SI-FMA -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
; Note: The SI-FMA conversions of type x * (y + 1) --> x * y + x would be ; Note: The SI-FMA conversions of type x addrspace(5)* (y + 1) --> x addrspace(5)* y + x would be
; beneficial even without fp32 denormals, but they do require no-infs-fp-math ; beneficial even without fp32 denormals, but they do require no-infs-fp-math
; for correctness. ; for correctness.

test/CodeGen/AMDGPU/fma.f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare double @llvm.fma.f64(double, double, double) nounwind readnone declare double @llvm.fma.f64(double, double, double) nounwind readnone
declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone

test/CodeGen/AMDGPU/fma.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare float @llvm.fma.f32(float, float, float) nounwind readnone declare float @llvm.fma.f32(float, float, float) nounwind readnone
declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone

test/CodeGen/AMDGPU/fmad.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

test/CodeGen/AMDGPU/fmax3.f64.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare double @llvm.maxnum.f64(double, double) nounwind readnone declare double @llvm.maxnum.f64(double, double) nounwind readnone

test/CodeGen/AMDGPU/fmax3.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}test_fmax3_olt_0_f32: ; GCN-LABEL: {{^}}test_fmax3_olt_0_f32:
; GCN: buffer_load_dword [[REGC:v[0-9]+]] ; GCN: buffer_load_dword [[REGC:v[0-9]+]]

test/CodeGen/AMDGPU/fmax_legacy.f64.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; Make sure we don't try to form FMAX_LEGACY nodes with f64 ; Make sure we don't try to form FMAX_LEGACY nodes with f64
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1

test/CodeGen/AMDGPU/fmax_legacy.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FIXME: Should replace unsafe-fp-math with no signed zeros. ; FIXME: Should replace unsafe-fp-math with no signed zeros.

test/CodeGen/AMDGPU/fmaxnum.f64.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare double @llvm.maxnum.f64(double, double) #0 declare double @llvm.maxnum.f64(double, double) #0
declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>) #0 declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>) #0

test/CodeGen/AMDGPU/fmaxnum.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.maxnum.f32(float, float) #0 declare float @llvm.maxnum.f32(float, float) #0
declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0 declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0

test/CodeGen/AMDGPU/fmed3.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
; GCN-LABEL: {{^}}v_test_nnan_input_fmed3_r_i_i_f32: ; GCN-LABEL: {{^}}v_test_nnan_input_fmed3_r_i_i_f32:

test/CodeGen/AMDGPU/fmin3.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}test_fmin3_olt_0_f32: ; GCN-LABEL: {{^}}test_fmin3_olt_0_f32:
; GCN: buffer_load_dword [[REGC:v[0-9]+]] ; GCN: buffer_load_dword [[REGC:v[0-9]+]]

test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN %s
; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-NONAN -check-prefix=GCN %s ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-NONAN -check-prefix=GCN %s
; FIXME: Should replace unsafe-fp-math with no signed zeros. ; FIXME: Should replace unsafe-fp-math with no signed zeros.

test/CodeGen/AMDGPU/fmin_legacy.f64.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1

test/CodeGen/AMDGPU/fminnum.f64.ll

; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare double @llvm.minnum.f64(double, double) #0 declare double @llvm.minnum.f64(double, double) #0
declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>) #0 declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>) #0

test/CodeGen/AMDGPU/fminnum.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare float @llvm.minnum.f32(float, float) #0 declare float @llvm.minnum.f32(float, float) #0
declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0

test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll

; XUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s
; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't ; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't

test/CodeGen/AMDGPU/fmul.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}fmul_f16 ; GCN-LABEL: {{^}}fmul_f16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fmul.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}fmul_f32: ; FUNC-LABEL: {{^}}fmul_f32:
; GCN: v_mul_f32 ; GCN: v_mul_f32

test/CodeGen/AMDGPU/fmul64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
; FUNC-LABEL: {{^}}fmul_f64: ; FUNC-LABEL: {{^}}fmul_f64:
; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} ; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}

test/CodeGen/AMDGPU/fmuladd.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-FLUSH,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-FLUSH,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-FLUSH,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-FLUSH,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-FLUSH,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-FLUSH,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-FLUSH,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-FLUSH,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-DENORM-STRICT,VI-DENORM,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-DENORM-STRICT,VI-DENORM,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-DENORM-STRICT,VI-DENORM,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI-DENORM-STRICT,VI-DENORM,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-DENORM-CONTRACT,VI-DENORM,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-DENORM-CONTRACT,VI-DENORM,VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-DENORM-CONTRACT,VI-DENORM,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI-DENORM-CONTRACT,VI-DENORM,VI %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare half @llvm.fmuladd.f16(half, half, half) #1 declare half @llvm.fmuladd.f16(half, half, half) #1

test/CodeGen/AMDGPU/fmuladd.f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICTSI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICTSI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI %s
; GCN-LABEL: {{^}}fmuladd_f64: ; GCN-LABEL: {{^}}fmuladd_f64:
; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} ; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}

test/CodeGen/AMDGPU/fmuladd.v2f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-FLUSH,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-FLUSH,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-FLUSH,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-FLUSH,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-FLUSH,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-FLUSH,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-FLUSH,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-FLUSH,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-DENORM-STRICT,GFX9-DENORM,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-DENORM-STRICT,GFX9-DENORM,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-DENORM-STRICT,GFX9-DENORM,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=on -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,GFX9-DENORM-STRICT,GFX9-DENORM,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-DENORM-CONTRACT,GFX9-DENORM,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-DENORM-CONTRACT,GFX9-DENORM,GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-DENORM-CONTRACT,GFX9-DENORM,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=+fp64-fp16-denormals -fp-contract=fast -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,GFX9-DENORM-CONTRACT,GFX9-DENORM,GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare <2 x half> @llvm.fmuladd.v2f16(<2 x half>, <2 x half>, <2 x half>) #1 declare <2 x half> @llvm.fmuladd.v2f16(<2 x half>, <2 x half>, <2 x half>) #1

test/CodeGen/AMDGPU/fnearbyint.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s
; This should have the exactly the same output as the test for rint, ; This should have the exactly the same output as the test for rint,
; so no need to check anything. ; so no need to check anything.

test/CodeGen/AMDGPU/fneg-combines.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -start-after=sink -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -start-after=sink -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -enable-no-signed-zeros-fp-math -march=amdgcn -mcpu=tahiti -start-after=sink -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NSZ -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -enable-no-signed-zeros-fp-math -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -start-after=sink -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NSZ -check-prefix=SI -check-prefix=FUNC %s
; -------------------------------------------------------------------------------- ; --------------------------------------------------------------------------------
; fadd tests ; fadd tests

test/CodeGen/AMDGPU/fneg-fabs.f16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=CIVI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=CIVI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GFX89 -check-prefix=GCN -check-prefix=CIVI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GFX89 -check-prefix=GCN -check-prefix=CIVI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=GCN %s
; GCN-LABEL: {{^}}fneg_fabs_fadd_f16: ; GCN-LABEL: {{^}}fneg_fabs_fadd_f16:
; CI: v_cvt_f32_f16_e32 ; CI: v_cvt_f32_f16_e32

test/CodeGen/AMDGPU/fneg-fabs.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; FIXME: Check something here. Currently it seems fabs + fneg aren't ; FIXME: Check something here. Currently it seems fabs + fneg aren't
; into 2 modifiers, although theoretically that should work. ; into 2 modifiers, although theoretically that should work.

test/CodeGen/AMDGPU/fneg-fabs.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32: ; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32:
; SI-NOT: and ; SI-NOT: and

test/CodeGen/AMDGPU/fneg.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,GFX89 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s
; FIXME: Should be able to do scalar op ; FIXME: Should be able to do scalar op
; GCN-LABEL: {{^}}s_fneg_f16: ; GCN-LABEL: {{^}}s_fneg_f16:

test/CodeGen/AMDGPU/fneg.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}fneg_f64: ; FUNC-LABEL: {{^}}fneg_f64:
; GCN: v_xor_b32 ; GCN: v_xor_b32

test/CodeGen/AMDGPU/fneg.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}s_fneg_f32: ; FUNC-LABEL: {{^}}s_fneg_f32:
; R600: -PV ; R600: -PV

test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}fold_mul_neg: ; GCN-LABEL: {{^}}fold_mul_neg:
; GCN: load_dword [[V:v[0-9]+]] ; GCN: load_dword [[V:v[0-9]+]]

test/CodeGen/AMDGPU/fp-classify.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1
declare double @llvm.fabs.f64(double) #1 declare double @llvm.fabs.f64(double) #1

test/CodeGen/AMDGPU/fp16_to_fp64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone

test/CodeGen/AMDGPU/fp32_to_fp16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone

test/CodeGen/AMDGPU/fp_to_sint.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare double @llvm.fabs.f64(double) #1 declare double @llvm.fabs.f64(double) #1

test/CodeGen/AMDGPU/fp_to_sint.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1

test/CodeGen/AMDGPU/fp_to_uint.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare double @llvm.fabs.f64(double) #1 declare double @llvm.fabs.f64(double) #1

test/CodeGen/AMDGPU/fp_to_uint.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,FUNC,SI ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,FUNC,SI
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,FUNC,VI ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,FUNC,VI
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=EG -check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s -check-prefix=EG -check-prefix=FUNC
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1

test/CodeGen/AMDGPU/fpext-free.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9,GFX9-F32FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9,GFX9-F32FLUSH %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9,GFX9-F32DENORM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9,GFX9-F32DENORM %s
; RUN: llc -march=amdgcn -mcpu=gfx803 -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI,VI-F32FLUSH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx803 -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI,VI-F32FLUSH %s
; RUN: llc -march=amdgcn -mcpu=gfx803 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI,VI-F32DENORM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx803 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI,VI-F32DENORM %s
; fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) ; fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)

test/CodeGen/AMDGPU/fpext.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
; GCN-LABEL: {{^}}fpext_f16_to_f32 ; GCN-LABEL: {{^}}fpext_f16_to_f32
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fpext.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}fpext_f32_to_f64: ; FUNC-LABEL: {{^}}fpext_f32_to_f64:
; SI: v_cvt_f64_f32_e32 {{v\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} ; SI: v_cvt_f64_f32_e32 {{v\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}

test/CodeGen/AMDGPU/fptosi.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}fptosi_f16_to_i16 ; GCN-LABEL: {{^}}fptosi_f16_to_i16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fptoui.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}fptoui_f16_to_i16 ; GCN-LABEL: {{^}}fptoui_f16_to_i16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fptrunc.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; GCN-LABEL: {{^}}fptrunc_f32_to_f16: ; GCN-LABEL: {{^}}fptrunc_f32_to_f16:
; GCN: buffer_load_dword v[[A_F32:[0-9]+]] ; GCN: buffer_load_dword v[[A_F32:[0-9]+]]

test/CodeGen/AMDGPU/fptrunc.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN-UNSAFE %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN-UNSAFE %s
; FUNC-LABEL: {{^}}fptrunc_f64_to_f32: ; FUNC-LABEL: {{^}}fptrunc_f64_to_f32:
; GCN: v_cvt_f32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} ; GCN: v_cvt_f32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}

test/CodeGen/AMDGPU/fract.f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=SI-UNSAFE -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=SI-UNSAFE -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=VI-UNSAFE -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=VI-UNSAFE -check-prefix=FUNC %s
declare double @llvm.fabs.f64(double) #0 declare double @llvm.fabs.f64(double) #0
declare double @llvm.floor.f64(double) #0 declare double @llvm.floor.f64(double) #0

test/CodeGen/AMDGPU/fract.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=GCN %s
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0
declare float @llvm.floor.f32(float) #0 declare float @llvm.floor.f32(float) #0

test/CodeGen/AMDGPU/frem.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}frem_f32: ; FUNC-LABEL: {{^}}frem_f32:
; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}} ; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}

test/CodeGen/AMDGPU/fsqrt.f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}v_safe_fsqrt_f64: ; FUNC-LABEL: {{^}}v_safe_fsqrt_f64:
; GCN: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} ; GCN: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}

test/CodeGen/AMDGPU/fsub.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
; GCN-LABEL: {{^}}fsub_f16: ; GCN-LABEL: {{^}}fsub_f16:
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/fsub.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}v_fsub_f32: ; FUNC-LABEL: {{^}}v_fsub_f32:
; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} ; SI: v_sub_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

test/CodeGen/AMDGPU/fsub64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare double @llvm.fabs.f64(double) #0 declare double @llvm.fabs.f64(double) #0

test/CodeGen/AMDGPU/ftrunc.f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
declare double @llvm.trunc.f64(double) nounwind readnone declare double @llvm.trunc.f64(double) nounwind readnone
declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone

test/CodeGen/AMDGPU/ftrunc.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG --check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG --check-prefix=FUNC %s
declare float @llvm.trunc.f32(float) nounwind readnone declare float @llvm.trunc.f32(float) nounwind readnone
declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone

test/CodeGen/AMDGPU/gep-address-space.ll

; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
define amdgpu_kernel void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind { define amdgpu_kernel void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
; CHECK-LABEL: {{^}}use_gep_address_space: ; CHECK-LABEL: {{^}}use_gep_address_space:

test/CodeGen/AMDGPU/global-constant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s
@private1 = private unnamed_addr addrspace(2) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0] @private1 = private unnamed_addr addrspace(2) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
@private2 = private unnamed_addr addrspace(2) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0] @private2 = private unnamed_addr addrspace(2) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]

test/CodeGen/AMDGPU/global-directive.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; Make sure the GlobalDirective isn't merged with the function name ; Make sure the GlobalDirective isn't merged with the function name

test/CodeGen/AMDGPU/global-extload-i16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; XUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FIXME: cypress is broken because the bigger testcases spill and it's not implemented ; FIXME: cypress is broken because the bigger testcases spill and it's not implemented
; FUNC-LABEL: {{^}}zextload_global_i16_to_i32: ; FUNC-LABEL: {{^}}zextload_global_i16_to_i32:

test/CodeGen/AMDGPU/global-smrd-unknown.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -memdep-block-scan-limit=1 -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -memdep-block-scan-limit=1 -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; GCN-LABEL: {{^}}unknown_memdep_analysis: ; GCN-LABEL: {{^}}unknown_memdep_analysis:
; GCN: flat_load_dword ; GCN: flat_load_dword

test/CodeGen/AMDGPU/global-variable-relocs.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji < %s | FileCheck %s
@private = private addrspace(1) global [256 x i32] zeroinitializer @private = private addrspace(1) global [256 x i32] zeroinitializer
@internal = internal addrspace(1) global [256 x i32] zeroinitializer @internal = internal addrspace(1) global [256 x i32] zeroinitializer

test/CodeGen/AMDGPU/global_atomics.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}atomic_add_i32_offset: ; GCN-LABEL: {{^}}atomic_add_i32_offset:
; SIVI: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} ; SIVI: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}

test/CodeGen/AMDGPU/global_atomics_i64.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}atomic_add_i64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_offset:
; CIVI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} ; CIVI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}}

test/CodeGen/AMDGPU/gv-const-addrspace.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
@b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2 @b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2

test/CodeGen/AMDGPU/gv-offset-folding.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -relocation-model=static < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -relocation-model=static < %s | FileCheck %s
@lds = external addrspace(3) global [4 x i32] @lds = external addrspace(3) global [4 x i32]

test/CodeGen/AMDGPU/half.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; half args should be promoted to float for SI and lower. ; half args should be promoted to float for SI and lower.

test/CodeGen/AMDGPU/hoist-cond.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; Check that invariant compare is hoisted out of the loop. ; Check that invariant compare is hoisted out of the loop.
; At the same time condition shall not be serialized into a VGPR and deserialized later ; At the same time condition shall not be serialized into a VGPR and deserialized later

test/CodeGen/AMDGPU/hsa-default-device.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz < %s | FileCheck %s
; Make sure that with an HSA triple, we don't default to an ; Make sure that with an HSA triple, we don't default to an
; unsupported device. ; unsupported device.

test/CodeGen/AMDGPU/hsa-fp-mode.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_default_ci: ; GCN-LABEL: {{^}}test_default_ci:
; GCN: float_mode = 192 ; GCN: float_mode = 192

test/CodeGen/AMDGPU/hsa-func-align.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=HSA %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri < %s | FileCheck -check-prefix=HSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj < %s | llvm-readobj -symbols -s -sd | FileCheck -check-prefix=ELF %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -filetype=obj < %s | llvm-readobj -symbols -s -sd | FileCheck -check-prefix=ELF %s
; ELF: Section { ; ELF: Section {
; ELF: Name: .text ; ELF: Name: .text

test/CodeGen/AMDGPU/hsa-globals.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=ASM %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri | FileCheck --check-prefix=ASM %s
@linkonce_odr_global_program = linkonce_odr addrspace(1) global i32 0 @linkonce_odr_global_program = linkonce_odr addrspace(1) global i32 0
@linkonce_global_program = linkonce addrspace(1) global i32 0 @linkonce_global_program = linkonce addrspace(1) global i32 0

test/CodeGen/AMDGPU/hsa-group-segment.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri | FileCheck --check-prefix=HSA %s
@internal_group = internal addrspace(3) global i32 undef @internal_group = internal addrspace(3) global i32 undef
@external_group = addrspace(3) global i32 undef @external_group = addrspace(3) global i32 undef

test/CodeGen/AMDGPU/hsa-metadata-deduce-ro-arg.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s
; CHECK: - Name: test_ro_arg ; CHECK: - Name: test_ro_arg
; CHECK-NEXT: SymbolName: 'test_ro_arg@kd' ; CHECK-NEXT: SymbolName: 'test_ro_arg@kd'
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'float*' ; CHECK-NEXT: - TypeName: 'float addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
Context not available.
; CHECK-NEXT: AccQual: ReadOnly ; CHECK-NEXT: AccQual: ReadOnly
; CHECK-NEXT: IsConst: true ; CHECK-NEXT: IsConst: true
; CHECK-NEXT: IsRestrict: true ; CHECK-NEXT: IsRestrict: true
; CHECK-NEXT: - TypeName: 'float*' ; CHECK-NEXT: - TypeName: 'float addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
Context not available.
!0 = !{i32 1, i32 1} !0 = !{i32 1, i32 1}
!1 = !{!"none", !"none"} !1 = !{!"none", !"none"}
!2 = !{!"float*", !"float*"} !2 = !{!"float addrspace(5)*", !"float addrspace(5)*"}
!3 = !{!"const restrict", !""} !3 = !{!"const restrict", !""}
Context not available.

test/CodeGen/AMDGPU/hsa-metadata-enqueu-kernel.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]

test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx700 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
%struct.A = type { i8, float } %struct.A = type { i8, float }
%opencl.image1d_t = type opaque %opencl.image1d_t = type opaque
Context not available.
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
Context not available.
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_struct(%struct.A* byval %a) define amdgpu_kernel void @test_struct(%struct.A addrspace(5)* byval %a)
!kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !20 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !20
!kernel_arg_base_type !20 !kernel_arg_type_qual !4 { !kernel_arg_base_type !20 !kernel_arg_type_qual !4 {
ret void ret void
Context not available.
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Constant ; CHECK-NEXT: AddrSpaceQual: Constant
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
Context not available.
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: IsVolatile: true ; CHECK-NEXT: IsVolatile: true
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
Context not available.
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: IsConst: true ; CHECK-NEXT: IsConst: true
; CHECK-NEXT: IsRestrict: true ; CHECK-NEXT: IsRestrict: true
; CHECK-NEXT: - TypeName: 'int *' ; CHECK-NEXT: - TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: Pipe ; CHECK-NEXT: ValueKind: Pipe
Context not available.
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'int **' ; CHECK-NEXT: - TypeName: 'int addrspace(5)* addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
Context not available.
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_arg_ptr_to_ptr(i32* addrspace(1)* %a) define amdgpu_kernel void @test_arg_ptr_to_ptr(i32 addrspace(5)* addrspace(1)* %a)
!kernel_arg_addr_space !81 !kernel_arg_access_qual !2 !kernel_arg_type !80 !kernel_arg_addr_space !81 !kernel_arg_access_qual !2 !kernel_arg_type !80
!kernel_arg_base_type !80 !kernel_arg_type_qual !4 { !kernel_arg_base_type !80 !kernel_arg_type_qual !4 {
ret void ret void
Context not available.
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_arg_struct_contains_ptr(%struct.B* byval %a) define amdgpu_kernel void @test_arg_struct_contains_ptr(%struct.B addrspace(5)* byval %a)
!kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !82 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !82
!kernel_arg_base_type !82 !kernel_arg_type_qual !4 { !kernel_arg_base_type !82 !kernel_arg_type_qual !4 {
ret void ret void
Context not available.
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'global int* __attribute__((ext_vector_type(2)))' ; CHECK-NEXT: - TypeName: 'global int addrspace(5)* __attribute__((ext_vector_type(2)))'
; CHECK-NEXT: Size: 16 ; CHECK-NEXT: Size: 16
; CHECK-NEXT: Align: 16 ; CHECK-NEXT: Align: 16
; CHECK-NEXT: ValueKind: ByValue ; CHECK-NEXT: ValueKind: ByValue
Context not available.
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - TypeName: 'long *' ; CHECK-NEXT: - TypeName: 'long addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'char *' ; CHECK-NEXT: - TypeName: 'char addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: PointeeAlign: 1 ; CHECK-NEXT: PointeeAlign: 1
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'char2 *' ; CHECK-NEXT: - TypeName: 'char2 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: PointeeAlign: 2 ; CHECK-NEXT: PointeeAlign: 2
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'char3 *' ; CHECK-NEXT: - TypeName: 'char3 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: PointeeAlign: 4 ; CHECK-NEXT: PointeeAlign: 4
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'char4 *' ; CHECK-NEXT: - TypeName: 'char4 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: PointeeAlign: 4 ; CHECK-NEXT: PointeeAlign: 4
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'char8 *' ; CHECK-NEXT: - TypeName: 'char8 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: PointeeAlign: 8 ; CHECK-NEXT: PointeeAlign: 8
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - TypeName: 'char16 *' ; CHECK-NEXT: - TypeName: 'char16 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
Context not available.
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @__test_block_invoke_kernel( define amdgpu_kernel void @__test_block_invoke_kernel(
<{ i32, i32, i8 addrspace(4)*, i8 addrspace(1)*, i8 }> %arg) #0 <{ i32, i32, i8*, i8 addrspace(1)*, i8 }> %arg) #0
!kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !110 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !110
!kernel_arg_base_type !110 !kernel_arg_type_qual !4 { !kernel_arg_base_type !110 !kernel_arg_type_qual !4 {
ret void ret void
Context not available.
!13 = !{!"half8"} !13 = !{!"half8"}
!14 = !{!"float16"} !14 = !{!"float16"}
!15 = !{!"double16"} !15 = !{!"double16"}
!16 = !{!"int *"} !16 = !{!"int addrspace(5)*"}
!17 = !{!"image2d_t"} !17 = !{!"image2d_t"}
!18 = !{!"sampler_t"} !18 = !{!"sampler_t"}
!19 = !{!"queue_t"} !19 = !{!"queue_t"}
Context not available.
!29 = !{i8 undef, i32 1} !29 = !{i8 undef, i32 1}
!30 = !{i16 undef, i32 1} !30 = !{i16 undef, i32 1}
!31 = !{i64 undef, i32 1} !31 = !{i64 undef, i32 1}
!32 = !{i32 *undef, i32 1} !32 = !{i32 addrspace(5)*undef, i32 1}
!50 = !{i32 1, i32 2, i32 3} !50 = !{i32 1, i32 2, i32 3}
!51 = !{!"int *", !"int *", !"int *"} !51 = !{!"int addrspace(5)*", !"int addrspace(5)*", !"int addrspace(5)*"}
!60 = !{i32 1, i32 1, i32 1} !60 = !{i32 1, i32 1, i32 1}
!61 = !{!"read_only", !"write_only", !"read_write"} !61 = !{!"read_only", !"write_only", !"read_write"}
!62 = !{!"image1d_t", !"image2d_t", !"image3d_t"} !62 = !{!"image1d_t", !"image2d_t", !"image3d_t"}
!70 = !{!"volatile", !"const restrict", !"pipe"} !70 = !{!"volatile", !"const restrict", !"pipe"}
!80 = !{!"int **"} !80 = !{!"int addrspace(5)* addrspace(5)*"}
!81 = !{i32 1} !81 = !{i32 1}
!82 = !{!"struct B"} !82 = !{!"struct B"}
!83 = !{!"global int* __attribute__((ext_vector_type(2)))"} !83 = !{!"global int addrspace(5)* __attribute__((ext_vector_type(2)))"}
!84 = !{!"clk_event_t"} !84 = !{!"clk_event_t"}
!opencl.ocl.version = !{!90} !opencl.ocl.version = !{!90}
!90 = !{i32 2, i32 0} !90 = !{i32 2, i32 0}
!91 = !{i32 0, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3} !91 = !{i32 0, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3}
!92 = !{!"none", !"none", !"none", !"none", !"none", !"none", !"none"} !92 = !{!"none", !"none", !"none", !"none", !"none", !"none", !"none"}
!93 = !{!"long *", !"char *", !"char2 *", !"char3 *", !"char4 *", !"char8 *", !"char16 *"} !93 = !{!"long addrspace(5)*", !"char addrspace(5)*", !"char2 addrspace(5)*", !"char3 addrspace(5)*", !"char4 addrspace(5)*", !"char8 addrspace(5)*", !"char16 addrspace(5)*"}
!94 = !{!"", !"", !"", !"", !"", !"", !""} !94 = !{!"", !"", !"", !"", !"", !"", !""}
!100 = !{!"1:1:4:%d\5Cn"} !100 = !{!"1:1:4:%d\5Cn"}
!101 = !{!"2:1:8:%g\5Cn"} !101 = !{!"2:1:8:%g\5Cn"}
Context not available.

test/CodeGen/AMDGPU/hsa-metadata-images.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
%opencl.image1d_t = type opaque %opencl.image1d_t = type opaque
%opencl.image1d_array_t = type opaque %opencl.image1d_array_t = type opaque

test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.

test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-2.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.

test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.

test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]

test/CodeGen/AMDGPU/hsa-note-no-func.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx600 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI600 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx600 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI600 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx601 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI601 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx601 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI601 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx700 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx701 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx702 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx703 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=mullins | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=hawaii | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kabini | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=tonga -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris10 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=polaris10 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris11 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=polaris11 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx800 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI800 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx800 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI800 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx801 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx801 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx802 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx802 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx803 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx803 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx804 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI804 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx804 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI804 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx810 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI810 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx810 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI810 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX900 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx900 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX900 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx901 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX901 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX901 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx902 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx903 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX903 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx903 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX903 %s
; HSA: .hsa_code_object_version 2,1 ; HSA: .hsa_code_object_version 2,1
; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU" ; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU"

test/CodeGen/AMDGPU/i1-copy-implicit-def.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SILowerI1Copies was not handling IMPLICIT_DEF ; SILowerI1Copies was not handling IMPLICIT_DEF
; SI-LABEL: {{^}}br_implicit_def: ; SI-LABEL: {{^}}br_implicit_def:

test/CodeGen/AMDGPU/i1-copy-phi.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}br_i1_phi: ; SI-LABEL: {{^}}br_i1_phi:
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}

test/CodeGen/AMDGPU/i8-to-double-to-float.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

test/CodeGen/AMDGPU/icmp-select-sete-reverse-args.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;Test that a select with reversed True/False values is correctly lowered ;Test that a select with reversed True/False values is correctly lowered
;to a SETNE_INT. There should only be one SETNE_INT instruction. ;to a SETNE_INT. There should only be one SETNE_INT instruction.

test/CodeGen/AMDGPU/icmp.i16.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s| FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s| FileCheck -check-prefix=GCN -check-prefix=SI %s
;;;==========================================================================;;; ;;;==========================================================================;;;
;; 16-bit integer comparisons ;; 16-bit integer comparisons

test/CodeGen/AMDGPU/icmp64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}test_i64_eq: ; SI-LABEL: {{^}}test_i64_eq:
; SI: v_cmp_eq_u64 ; SI: v_cmp_eq_u64

test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll

; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck -check-prefix=ERR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s 2>&1 | FileCheck -check-prefix=ERR %s
; RUN: not llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=GCN %s
; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
; GCN: ; illegal copy v1 to s9 ; GCN: ; illegal copy v1 to s9

test/CodeGen/AMDGPU/image-attributes.ll

; RUN: llc -march=r600 -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; === WIDTH ================================================================== ; === WIDTH ==================================================================
; 9 implicit args = 9 dwords to first image argument. ; 9 implicit args = 9 dwords to first image argument.
Context not available.
!10 = !{!"kernel_arg_addr_space", i32 1, i32 1} !10 = !{!"kernel_arg_addr_space", i32 1, i32 1}
!20 = !{!"kernel_arg_access_qual", !"read_only", !"none"} !20 = !{!"kernel_arg_access_qual", !"read_only", !"none"}
!21 = !{!"kernel_arg_access_qual", !"read_only", !"none"} !21 = !{!"kernel_arg_access_qual", !"read_only", !"none"}
!30 = !{!"kernel_arg_type", !"image2d_t", !"int*"} !30 = !{!"kernel_arg_type", !"image2d_t", !"int addrspace(5)*"}
!31 = !{!"kernel_arg_type", !"image3d_t", !"int*"} !31 = !{!"kernel_arg_type", !"image3d_t", !"int addrspace(5)*"}
!40 = !{!"kernel_arg_base_type", !"image2d_t", !"int*"} !40 = !{!"kernel_arg_base_type", !"image2d_t", !"int addrspace(5)*"}
!41 = !{!"kernel_arg_base_type", !"image3d_t", !"int*"} !41 = !{!"kernel_arg_base_type", !"image3d_t", !"int addrspace(5)*"}
!50 = !{!"kernel_arg_type_qual", !"", !""} !50 = !{!"kernel_arg_type_qual", !"", !""}
!12 = !{!"kernel_arg_addr_space", i32 1, i32 0, i32 1, i32 1} !12 = !{!"kernel_arg_addr_space", i32 1, i32 0, i32 1, i32 1}
!22 = !{!"kernel_arg_access_qual", !"read_only", !"none", !"write_only", !"none"} !22 = !{!"kernel_arg_access_qual", !"read_only", !"none", !"write_only", !"none"}
!32 = !{!"kernel_arg_type", !"image3d_t", !"sampler_t", !"image2d_t", !"int*"} !32 = !{!"kernel_arg_type", !"image3d_t", !"sampler_t", !"image2d_t", !"int addrspace(5)*"}
!42 = !{!"kernel_arg_base_type", !"image3d_t", !"sampler_t", !"image2d_t", !"int*"} !42 = !{!"kernel_arg_base_type", !"image3d_t", !"sampler_t", !"image2d_t", !"int addrspace(5)*"}
!52 = !{!"kernel_arg_type_qual", !"", !"", !"", !""} !52 = !{!"kernel_arg_type_qual", !"", !"", !"", !""}
Context not available.

test/CodeGen/AMDGPU/image-resource-id.ll

; RUN: llc -march=r600 -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; === 1 image arg, read_only =================================================== ; === 1 image arg, read_only ===================================================
Context not available.
!110 = !{!"kernel_arg_addr_space", i32 1, i32 1} !110 = !{!"kernel_arg_addr_space", i32 1, i32 1}
!120 = !{!"kernel_arg_access_qual", !"read_only", !"none"} !120 = !{!"kernel_arg_access_qual", !"read_only", !"none"}
!121 = !{!"kernel_arg_access_qual", !"write_only", !"none"} !121 = !{!"kernel_arg_access_qual", !"write_only", !"none"}
!130 = !{!"kernel_arg_type", !"image2d_t", !"int*"} !130 = !{!"kernel_arg_type", !"image2d_t", !"int addrspace(5)*"}
!131 = !{!"kernel_arg_type", !"image3d_t", !"int*"} !131 = !{!"kernel_arg_type", !"image3d_t", !"int addrspace(5)*"}
!140 = !{!"kernel_arg_base_type", !"image2d_t", !"int*"} !140 = !{!"kernel_arg_base_type", !"image2d_t", !"int addrspace(5)*"}
!141 = !{!"kernel_arg_base_type", !"image3d_t", !"int*"} !141 = !{!"kernel_arg_base_type", !"image3d_t", !"int addrspace(5)*"}
!150 = !{!"kernel_arg_type_qual", !"", !""} !150 = !{!"kernel_arg_type_qual", !"", !""}
!4 = !{void (%opencl.image2d_t addrspace(1)*, %opencl.image2d_t addrspace(1)*, !4 = !{void (%opencl.image2d_t addrspace(1)*, %opencl.image2d_t addrspace(1)*,
Context not available.
!112 = !{!"kernel_arg_addr_space", i32 1, i32 1, i32 1} !112 = !{!"kernel_arg_addr_space", i32 1, i32 1, i32 1}
!122 = !{!"kernel_arg_access_qual", !"read_only", !"read_only", !"none"} !122 = !{!"kernel_arg_access_qual", !"read_only", !"read_only", !"none"}
!123 = !{!"kernel_arg_access_qual", !"write_only", !"write_only", !"none"} !123 = !{!"kernel_arg_access_qual", !"write_only", !"write_only", !"none"}
!132 = !{!"kernel_arg_type", !"image2d_t", !"image2d_t", !"int*"} !132 = !{!"kernel_arg_type", !"image2d_t", !"image2d_t", !"int addrspace(5)*"}
!133 = !{!"kernel_arg_type", !"image3d_t", !"image3d_t", !"int*"} !133 = !{!"kernel_arg_type", !"image3d_t", !"image3d_t", !"int addrspace(5)*"}
!142 = !{!"kernel_arg_base_type", !"image2d_t", !"image2d_t", !"int*"} !142 = !{!"kernel_arg_base_type", !"image2d_t", !"image2d_t", !"int addrspace(5)*"}
!143 = !{!"kernel_arg_base_type", !"image3d_t", !"image3d_t", !"int*"} !143 = !{!"kernel_arg_base_type", !"image3d_t", !"image3d_t", !"int addrspace(5)*"}
!152 = !{!"kernel_arg_type_qual", !"", !"", !""} !152 = !{!"kernel_arg_type_qual", !"", !"", !""}
!12 = !{void (%opencl.image2d_t addrspace(1)*, %opencl.image3d_t addrspace(1)*, !12 = !{void (%opencl.image2d_t addrspace(1)*, %opencl.image3d_t addrspace(1)*,
Context not available.
!125 = !{!"kernel_arg_access_qual", !"write_only", !"write_only", !"write_only", !"none"} !125 = !{!"kernel_arg_access_qual", !"write_only", !"write_only", !"write_only", !"none"}
!126 = !{!"kernel_arg_access_qual", !"write_only", !"read_only", !"read_only", !"none"} !126 = !{!"kernel_arg_access_qual", !"write_only", !"read_only", !"read_only", !"none"}
!127 = !{!"kernel_arg_access_qual", !"write_only", !"read_only", !"write_only", !"none"} !127 = !{!"kernel_arg_access_qual", !"write_only", !"read_only", !"write_only", !"none"}
!134 = !{!"kernel_arg_type", !"image2d_t", !"image3d_t", !"image2d_t", !"int*"} !134 = !{!"kernel_arg_type", !"image2d_t", !"image3d_t", !"image2d_t", !"int addrspace(5)*"}
!135 = !{!"kernel_arg_type", !"image3d_t", !"image2d_t", !"image3d_t", !"int*"} !135 = !{!"kernel_arg_type", !"image3d_t", !"image2d_t", !"image3d_t", !"int addrspace(5)*"}
!144 = !{!"kernel_arg_base_type", !"image2d_t", !"image3d_t", !"image2d_t", !"int*"} !144 = !{!"kernel_arg_base_type", !"image2d_t", !"image3d_t", !"image2d_t", !"int addrspace(5)*"}
!145 = !{!"kernel_arg_base_type", !"image3d_t", !"image2d_t", !"image3d_t", !"int*"} !145 = !{!"kernel_arg_base_type", !"image3d_t", !"image2d_t", !"image3d_t", !"int addrspace(5)*"}
!154 = !{!"kernel_arg_type_qual", !"", !"", !"", !""} !154 = !{!"kernel_arg_type_qual", !"", !"", !"", !""}
Context not available.

test/CodeGen/AMDGPU/imm.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Use a 64-bit value with lo bits that can be represented as an inline constant ; Use a 64-bit value with lo bits that can be represented as an inline constant
; GCN-LABEL: {{^}}i64_imm_inline_lo: ; GCN-LABEL: {{^}}i64_imm_inline_lo:

test/CodeGen/AMDGPU/imm16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; FIXME: Merge into imm.ll ; FIXME: Merge into imm.ll

test/CodeGen/AMDGPU/immv216.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; FIXME: Merge into imm.ll ; FIXME: Merge into imm.ll
; GCN-LABEL: {{^}}store_inline_imm_neg_0.0_v2i16: ; GCN-LABEL: {{^}}store_inline_imm_neg_0.0_v2i16:

test/CodeGen/AMDGPU/indirect-addressing-si-noopt.ll

; RUN: llc -O0 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
; FIXME: Merge into indirect-addressing-si.ll ; FIXME: Merge into indirect-addressing-si.ll

test/CodeGen/AMDGPU/indirect-addressing-si.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MOVREL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=IDXMODE %s
; Tests for indirect addressing on SI, which is implemented using dynamic ; Tests for indirect addressing on SI, which is implemented using dynamic
; indexing of vectors. ; indexing of vectors.

test/CodeGen/AMDGPU/indirect-private-64.ll

; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA16 -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA16 -check-prefix=SI %s
; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA4 -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA4 -check-prefix=SI %s
; RUN: llc -march=amdgcn -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=CI-ALLOCA16 -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=CI-ALLOCA16 -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=CI-PROMOTE -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=CI-PROMOTE -check-prefix=SI %s
target datalayout = "A5"
declare void @llvm.amdgcn.s.barrier() #0 declare void @llvm.amdgcn.s.barrier() #0
Context not available.
; CI-PROMOTE: ds_read_b64 ; CI-PROMOTE: ds_read_b64
define amdgpu_kernel void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) #1 {
%val = load double, double addrspace(1)* %in, align 8 %val = load double, double addrspace(1)* %in, align 8
%array = alloca [8 x double], align 8 %array = alloca [8 x double], align 8, addrspace(5)
%ptr = getelementptr inbounds [8 x double], [8 x double]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [8 x double], [8 x double] addrspace(5)* %array, i32 0, i32 %b
store double %val, double* %ptr, align 8 store double %val, double addrspace(5)* %ptr, align 8
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load double, double* %ptr, align 8 %result = load double, double addrspace(5)* %ptr, align 8
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
} }
Context not available.
; CI-PROMOTE: ds_read2_b64 ; CI-PROMOTE: ds_read2_b64
define amdgpu_kernel void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) #1 {
%val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16 %val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16
%array = alloca [4 x <2 x double>], align 16 %array = alloca [4 x <2 x double>], align 16, addrspace(5)
%ptr = getelementptr inbounds [4 x <2 x double>], [4 x <2 x double>]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [4 x <2 x double>], [4 x <2 x double>] addrspace(5)* %array, i32 0, i32 %b
store <2 x double> %val, <2 x double>* %ptr, align 16 store <2 x double> %val, <2 x double> addrspace(5)* %ptr, align 16
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load <2 x double>, <2 x double>* %ptr, align 16 %result = load <2 x double>, <2 x double> addrspace(5)* %ptr, align 16
store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16 store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16
ret void ret void
} }
Context not available.
; CI-PROMOTE: ds_read_b64 ; CI-PROMOTE: ds_read_b64
define amdgpu_kernel void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) #1 {
%val = load i64, i64 addrspace(1)* %in, align 8 %val = load i64, i64 addrspace(1)* %in, align 8
%array = alloca [8 x i64], align 8 %array = alloca [8 x i64], align 8, addrspace(5)
%ptr = getelementptr inbounds [8 x i64], [8 x i64]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [8 x i64], [8 x i64] addrspace(5)* %array, i32 0, i32 %b
store i64 %val, i64* %ptr, align 8 store i64 %val, i64 addrspace(5)* %ptr, align 8
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load i64, i64* %ptr, align 8 %result = load i64, i64 addrspace(5)* %ptr, align 8
store i64 %result, i64 addrspace(1)* %out, align 8 store i64 %result, i64 addrspace(1)* %out, align 8
ret void ret void
} }
Context not available.
; CI-PROMOTE: ds_read2_b64 ; CI-PROMOTE: ds_read2_b64
define amdgpu_kernel void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) #1 {
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16 %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
%array = alloca [4 x <2 x i64>], align 16 %array = alloca [4 x <2 x i64>], align 16, addrspace(5)
%ptr = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>] addrspace(5)* %array, i32 0, i32 %b
store <2 x i64> %val, <2 x i64>* %ptr, align 16 store <2 x i64> %val, <2 x i64> addrspace(5)* %ptr, align 16
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load <2 x i64>, <2 x i64>* %ptr, align 16 %result = load <2 x i64>, <2 x i64> addrspace(5)* %ptr, align 16
store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16 store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll

; RUN: opt -mtriple=amdgcn--amdhsa -disable-output -disable-verify -debug-pass=Structure -O2 %s 2>&1 | FileCheck -check-prefix=GCN %s ; RUN: opt -mtriple=amdgcn--amdhsa-amdgiz -disable-output -disable-verify -debug-pass=Structure -O2 %s 2>&1 | FileCheck -check-prefix=GCN %s
; GCN: Function Integration/Inlining ; GCN: Function Integration/Inlining
; GCN: FunctionPass Manager ; GCN: FunctionPass Manager

test/CodeGen/AMDGPU/infinite-loop-evergreen.ll

; XFAIL: * ; XFAIL: *
; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck %s
define amdgpu_kernel void @inf_loop_irreducible_cfg() nounwind { define amdgpu_kernel void @inf_loop_irreducible_cfg() nounwind {
entry: entry:

test/CodeGen/AMDGPU/infinite-loop.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}infinite_loop: ; SI-LABEL: {{^}}infinite_loop:
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7

test/CodeGen/AMDGPU/inline-asm.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}inline_asm: ; CHECK-LABEL: {{^}}inline_asm:
; CHECK: s_endpgm ; CHECK: s_endpgm

test/CodeGen/AMDGPU/inline-attr.ll

; RUN: opt -mtriple=amdgcn--amdhsa -S -O3 -enable-unsafe-fp-math %s | FileCheck -check-prefix=GCN -check-prefix=UNSAFE %s ; RUN: opt -mtriple=amdgcn--amdhsa-amdgiz -S -O3 -enable-unsafe-fp-math %s | FileCheck -check-prefix=GCN -check-prefix=UNSAFE %s
; RUN: opt -mtriple=amdgcn--amdhsa -S -O3 -enable-no-nans-fp-math %s | FileCheck -check-prefix=GCN -check-prefix=NONANS %s ; RUN: opt -mtriple=amdgcn--amdhsa-amdgiz -S -O3 -enable-no-nans-fp-math %s | FileCheck -check-prefix=GCN -check-prefix=NONANS %s
; RUN: opt -mtriple=amdgcn--amdhsa -S -O3 -enable-no-infs-fp-math %s | FileCheck -check-prefix=GCN -check-prefix=NOINFS %s ; RUN: opt -mtriple=amdgcn--amdhsa-amdgiz -S -O3 -enable-no-infs-fp-math %s | FileCheck -check-prefix=GCN -check-prefix=NOINFS %s
; GCN: define float @foo(float %x) local_unnamed_addr #0 { ; GCN: define float @foo(float %x) local_unnamed_addr #0 {
; GCN: define amdgpu_kernel void @caller(float addrspace(1)* nocapture %p) local_unnamed_addr #1 { ; GCN: define amdgpu_kernel void @caller(float addrspace(1)* nocapture %p) local_unnamed_addr #1 {

test/CodeGen/AMDGPU/inline-calls.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s
; CHECK-NOT: {{^}}func: ; CHECK-NOT: {{^}}func:
define internal fastcc i32 @func(i32 %a) { define internal fastcc i32 @func(i32 %a) {

test/CodeGen/AMDGPU/inline-constraints.ll

; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}inline_reg_constraints: ; GCN-LABEL: {{^}}inline_reg_constraints:
; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]

test/CodeGen/AMDGPU/inlineasm-16.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: not llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s
; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s
target datalayout = "A5"
; GCN-LABEL: {{^}}s_input_output_i16: ; GCN-LABEL: {{^}}s_input_output_i16:
; SICI: error: couldn't allocate output register for constraint 's' ; SICI: error: couldn't allocate output register for constraint 's'

test/CodeGen/AMDGPU/inlineasm-illegal-type.ll

; RUN: not llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
target datalayout = "A5"
; GCN: error: couldn't allocate output register for constraint 's' ; GCN: error: couldn't allocate output register for constraint 's'
; GCN: error: couldn't allocate input reg for constraint 's' ; GCN: error: couldn't allocate input reg for constraint 's'

test/CodeGen/AMDGPU/inlineasm-packed.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
; GCN-LABEL: {{^}}inline_asm_input_v2i16: ; GCN-LABEL: {{^}}inline_asm_input_v2i16:
; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}} ; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}

test/CodeGen/AMDGPU/input-mods.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=EG
;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s --check-prefix=CM
;EG-LABEL: {{^}}test: ;EG-LABEL: {{^}}test:
;EG: EXP_IEEE * ;EG: EXP_IEEE *

test/CodeGen/AMDGPU/insert_subreg.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s
target datalayout = "A5"
; Test that INSERT_SUBREG instructions don't have non-register operands after ; Test that INSERT_SUBREG instructions don't have non-register operands after
; instruction selection. ; instruction selection.
Context not available.
; CHECK-LABEL: test: ; CHECK-LABEL: test:
define amdgpu_kernel void @test(i64 addrspace(1)* %out) { define amdgpu_kernel void @test(i64 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca [16 x i32] %tmp0 = alloca [16 x i32], addrspace(5)
%tmp1 = ptrtoint [16 x i32]* %tmp0 to i32 %tmp1 = ptrtoint [16 x i32] addrspace(5)* %tmp0 to i32
%tmp2 = sext i32 %tmp1 to i64 %tmp2 = sext i32 %tmp1 to i64
store i64 %tmp2, i64 addrspace(1)* %out store i64 %tmp2, i64 addrspace(1)* %out
ret void ret void
Context not available.

test/CodeGen/AMDGPU/internalize.ll

; RUN: opt -O1 -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ALL -check-prefix=OPT %s ; RUN: opt -O1 -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ALL -check-prefix=OPT %s
; RUN: opt -O0 -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ALL -check-prefix=OPTNONE %s ; RUN: opt -O0 -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ALL -check-prefix=OPTNONE %s
; OPT-NOT: gvar_unused ; OPT-NOT: gvar_unused
; OPTNONE: gvar_unused ; OPTNONE: gvar_unused

test/CodeGen/AMDGPU/invalid-addrspacecast.ll

; RUN: not llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -mattr=-promote-alloca < %s 2>&1 | FileCheck -check-prefix=ERROR %s
target datalayout = "A5"
; ERROR: error: <unknown>:0:0: in function use_group_to_global_addrspacecast void (i32 addrspace(3)*): invalid addrspacecast ; ERROR: error: <unknown>:0:0: in function use_group_to_global_addrspacecast void (i32 addrspace(3)*): invalid addrspacecast
define amdgpu_kernel void @use_group_to_global_addrspacecast(i32 addrspace(3)* %ptr) { define amdgpu_kernel void @use_group_to_global_addrspacecast(i32 addrspace(3)* %ptr) {

test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -amdgpu-load-store-vectorizer=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-load-store-vectorizer=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GatherAllAliases gives up on trying to analyze cases where the ; GatherAllAliases gives up on trying to analyze cases where the
; pointer may have been loaded from an aliased store, so make sure ; pointer may have been loaded from an aliased store, so make sure

test/CodeGen/AMDGPU/ipra.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -enable-ipra -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs -enable-ipra -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN %s
; Kernels are not called, so there is no call preserved mask. ; Kernels are not called, so there is no call preserved mask.
; GCN-LABEL: {{^}}kernel: ; GCN-LABEL: {{^}}kernel:

test/CodeGen/AMDGPU/jump-address.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; CHECK: JUMP @6 ; CHECK: JUMP @6
; CHECK: EXPORT ; CHECK: EXPORT

test/CodeGen/AMDGPU/kcache-fold.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s
; CHECK: {{^}}main1: ; CHECK: {{^}}main1:
; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}} ; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}}

test/CodeGen/AMDGPU/kernarg-stack-alignment.ll

; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
target datalayout = "A5"
; Test that the alignment of kernel arguments does not impact the ; Test that the alignment of kernel arguments does not impact the
; alignment of the stack ; alignment of the stack
Context not available.
; CHECK-LABEL: {{^}}no_args: ; CHECK-LABEL: {{^}}no_args:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @no_args() { define amdgpu_kernel void @no_args() {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align32: ; CHECK-LABEL: {{^}}force_align32:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align32(<8 x i32>) { define amdgpu_kernel void @force_align32(<8 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align64: ; CHECK-LABEL: {{^}}force_align64:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align64(<16 x i32>) { define amdgpu_kernel void @force_align64(<16 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align128: ; CHECK-LABEL: {{^}}force_align128:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align128(<32 x i32>) { define amdgpu_kernel void @force_align128(<32 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align256: ; CHECK-LABEL: {{^}}force_align256:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align256(<64 x i32>) { define amdgpu_kernel void @force_align256(<64 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/kernel-args.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GCN,MESA-GCN,FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GCN,MESA-GCN,FUNC
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,HSA-VI,FUNC ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,HSA-VI,FUNC
; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefix=EG --check-prefix=FUNC
; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -verify-machineinstrs | FileCheck %s --check-prefix=EG --check-prefix=FUNC
; FUNC-LABEL: {{^}}i8_arg: ; FUNC-LABEL: {{^}}i8_arg:
; HSA-VI: kernarg_segment_alignment = 4 ; HSA-VI: kernarg_segment_alignment = 4

test/CodeGen/AMDGPU/knownbits-recursion.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=GCN %s
; Check we can compile this test without infinite loop in the ; Check we can compile this test without infinite loop in the
; DAG.computeKnownBits() due to missing (Depth + 1) argument in ; DAG.computeKnownBits() due to missing (Depth + 1) argument in

test/CodeGen/AMDGPU/large-alloca-compute.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa-amdgiz < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa-amdgiz -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
target datalayout = "A5"
; FIXME: align on alloca seems to be ignored for private_segment_alignment ; FIXME: align on alloca seems to be ignored for private_segment_alignment
Context not available.
; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen ; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen
; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen ; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen
; Scratch size = alloca size + emergency stack slot ; Scratch size = alloca size + emergency stack slot, addrspace(5)
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 { define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32 addrspace(5)* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/large-alloca-graphics.ll

; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=carrizo -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s
target datalayout = "A5"
; ALL-LABEL: {{^}}large_alloca_pixel_shader: ; ALL-LABEL: {{^}}large_alloca_pixel_shader:
; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
Context not available.
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 { define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32 addrspace(5)* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
Context not available.
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 { define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32 addrspace(5)* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/large-constant-initializer.ll

; RUN: llc -march=amdgcn -mcpu=tahiti < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s
; CHECK: s_endpgm ; CHECK: s_endpgm
@gv = external unnamed_addr addrspace(2) constant [239 x i32], align 4 @gv = external unnamed_addr addrspace(2) constant [239 x i32], align 4

test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll

; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck --check-prefix=SI --check-prefix=ALL %s ; RUN: opt -S -mtriple=amdgcn-unknown-unknown-amdgiz -amdgpu-promote-alloca < %s | FileCheck --check-prefix=SI --check-prefix=ALL %s
; RUN: opt -S -mcpu=tonga -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck --check-prefix=CI --check-prefix=ALL %s ; RUN: opt -S -mcpu=tonga -mtriple=amdgcn-unknown-unknown-amdgiz -amdgpu-promote-alloca < %s | FileCheck --check-prefix=CI --check-prefix=ALL %s
target datalayout = "A5"
; SI-NOT: @promote_alloca_size_63.stack = internal unnamed_addr addrspace(3) global [63 x [5 x i32]] undef, align 4 ; SI-NOT: @promote_alloca_size_63.stack = internal unnamed_addr addrspace(3) global [63 x [5 x i32]] undef, align 4
; CI: @promote_alloca_size_63.stack = internal unnamed_addr addrspace(3) global [63 x [5 x i32]] undef, align 4 ; CI: @promote_alloca_size_63.stack = internal unnamed_addr addrspace(3) global [63 x [5 x i32]] undef, align 4
define amdgpu_kernel void @promote_alloca_size_63(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define amdgpu_kernel void @promote_alloca_size_63(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
Context not available.
define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #1 { define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #1 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
Context not available.
define amdgpu_kernel void @promote_alloca_size_1600(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #2 { define amdgpu_kernel void @promote_alloca_size_1600(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #2 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
Context not available.
; SI: alloca [5 x i32] ; SI: alloca [5 x i32]
define amdgpu_kernel void @occupancy_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #3 { define amdgpu_kernel void @occupancy_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #3 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
Context not available.
; SI: alloca [5 x i32] ; SI: alloca [5 x i32]
define amdgpu_kernel void @occupancy_max(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #4 { define amdgpu_kernel void @occupancy_max(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #4 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
Context not available.
; CI-NOT: alloca ; CI-NOT: alloca
define amdgpu_kernel void @occupancy_6(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #5 { define amdgpu_kernel void @occupancy_6(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #5 {
entry: entry:
%stack = alloca [42 x i8], align 4 %stack = alloca [42 x i8], align 4, addrspace(5)
%tmp = load i8, i8 addrspace(1)* %in, align 1 %tmp = load i8, i8 addrspace(1)* %in, align 1
%tmp4 = sext i8 %tmp to i64 %tmp4 = sext i8 %tmp to i64
%arrayidx1 = getelementptr inbounds [42 x i8], [42 x i8]* %stack, i64 0, i64 %tmp4 %arrayidx1 = getelementptr inbounds [42 x i8], [42 x i8] addrspace(5)* %stack, i64 0, i64 %tmp4
store i8 4, i8* %arrayidx1, align 1 store i8 4, i8 addrspace(5)* %arrayidx1, align 1
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1
%tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1 %tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1
%tmp5 = sext i8 %tmp1 to i64 %tmp5 = sext i8 %tmp1 to i64
%arrayidx3 = getelementptr inbounds [42 x i8], [42 x i8]* %stack, i64 0, i64 %tmp5 %arrayidx3 = getelementptr inbounds [42 x i8], [42 x i8] addrspace(5)* %stack, i64 0, i64 %tmp5
store i8 5, i8* %arrayidx3, align 1 store i8 5, i8 addrspace(5)* %arrayidx3, align 1
%arrayidx10 = getelementptr inbounds [42 x i8], [42 x i8]* %stack, i64 0, i64 0 %arrayidx10 = getelementptr inbounds [42 x i8], [42 x i8] addrspace(5)* %stack, i64 0, i64 0
%tmp2 = load i8, i8* %arrayidx10, align 1 %tmp2 = load i8, i8 addrspace(5)* %arrayidx10, align 1
store i8 %tmp2, i8 addrspace(1)* %out, align 1 store i8 %tmp2, i8 addrspace(1)* %out, align 1
%arrayidx12 = getelementptr inbounds [42 x i8], [42 x i8]* %stack, i64 0, i64 1 %arrayidx12 = getelementptr inbounds [42 x i8], [42 x i8] addrspace(5)* %stack, i64 0, i64 1
%tmp3 = load i8, i8* %arrayidx12, align 1 %tmp3 = load i8, i8 addrspace(5)* %arrayidx12, align 1
%arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1 %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1 store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1
ret void ret void
Context not available.
; ALL: alloca [43 x i8] ; ALL: alloca [43 x i8]
define amdgpu_kernel void @occupancy_6_over(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #5 { define amdgpu_kernel void @occupancy_6_over(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #5 {
entry: entry:
%stack = alloca [43 x i8], align 4 %stack = alloca [43 x i8], align 4, addrspace(5)
%tmp = load i8, i8 addrspace(1)* %in, align 1 %tmp = load i8, i8 addrspace(1)* %in, align 1
%tmp4 = sext i8 %tmp to i64 %tmp4 = sext i8 %tmp to i64
%arrayidx1 = getelementptr inbounds [43 x i8], [43 x i8]* %stack, i64 0, i64 %tmp4 %arrayidx1 = getelementptr inbounds [43 x i8], [43 x i8] addrspace(5)* %stack, i64 0, i64 %tmp4
store i8 4, i8* %arrayidx1, align 1 store i8 4, i8 addrspace(5)* %arrayidx1, align 1
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1
%tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1 %tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1
%tmp5 = sext i8 %tmp1 to i64 %tmp5 = sext i8 %tmp1 to i64
%arrayidx3 = getelementptr inbounds [43 x i8], [43 x i8]* %stack, i64 0, i64 %tmp5 %arrayidx3 = getelementptr inbounds [43 x i8], [43 x i8] addrspace(5)* %stack, i64 0, i64 %tmp5
store i8 5, i8* %arrayidx3, align 1 store i8 5, i8 addrspace(5)* %arrayidx3, align 1
%arrayidx10 = getelementptr inbounds [43 x i8], [43 x i8]* %stack, i64 0, i64 0 %arrayidx10 = getelementptr inbounds [43 x i8], [43 x i8] addrspace(5)* %stack, i64 0, i64 0
%tmp2 = load i8, i8* %arrayidx10, align 1 %tmp2 = load i8, i8 addrspace(5)* %arrayidx10, align 1
store i8 %tmp2, i8 addrspace(1)* %out, align 1 store i8 %tmp2, i8 addrspace(1)* %out, align 1
%arrayidx12 = getelementptr inbounds [43 x i8], [43 x i8]* %stack, i64 0, i64 1 %arrayidx12 = getelementptr inbounds [43 x i8], [43 x i8] addrspace(5)* %stack, i64 0, i64 1
%tmp3 = load i8, i8* %arrayidx12, align 1 %tmp3 = load i8, i8 addrspace(5)* %arrayidx12, align 1
%arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1 %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1 store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1
ret void ret void
Context not available.
; CI-NOT: alloca ; CI-NOT: alloca
define amdgpu_kernel void @occupancy_8(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #6 { define amdgpu_kernel void @occupancy_8(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #6 {
entry: entry:
%stack = alloca [32 x i8], align 4 %stack = alloca [32 x i8], align 4, addrspace(5)
%tmp = load i8, i8 addrspace(1)* %in, align 1 %tmp = load i8, i8 addrspace(1)* %in, align 1
%tmp4 = sext i8 %tmp to i64 %tmp4 = sext i8 %tmp to i64
%arrayidx1 = getelementptr inbounds [32 x i8], [32 x i8]* %stack, i64 0, i64 %tmp4 %arrayidx1 = getelementptr inbounds [32 x i8], [32 x i8] addrspace(5)* %stack, i64 0, i64 %tmp4
store i8 4, i8* %arrayidx1, align 1 store i8 4, i8 addrspace(5)* %arrayidx1, align 1
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1
%tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1 %tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1
%tmp5 = sext i8 %tmp1 to i64 %tmp5 = sext i8 %tmp1 to i64
%arrayidx3 = getelementptr inbounds [32 x i8], [32 x i8]* %stack, i64 0, i64 %tmp5 %arrayidx3 = getelementptr inbounds [32 x i8], [32 x i8] addrspace(5)* %stack, i64 0, i64 %tmp5
store i8 5, i8* %arrayidx3, align 1 store i8 5, i8 addrspace(5)* %arrayidx3, align 1
%arrayidx10 = getelementptr inbounds [32 x i8], [32 x i8]* %stack, i64 0, i64 0 %arrayidx10 = getelementptr inbounds [32 x i8], [32 x i8] addrspace(5)* %stack, i64 0, i64 0
%tmp2 = load i8, i8* %arrayidx10, align 1 %tmp2 = load i8, i8 addrspace(5)* %arrayidx10, align 1
store i8 %tmp2, i8 addrspace(1)* %out, align 1 store i8 %tmp2, i8 addrspace(1)* %out, align 1
%arrayidx12 = getelementptr inbounds [32 x i8], [32 x i8]* %stack, i64 0, i64 1 %arrayidx12 = getelementptr inbounds [32 x i8], [32 x i8] addrspace(5)* %stack, i64 0, i64 1
%tmp3 = load i8, i8* %arrayidx12, align 1 %tmp3 = load i8, i8 addrspace(5)* %arrayidx12, align 1
%arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1 %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1 store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1
ret void ret void
Context not available.
; ALL: alloca [33 x i8] ; ALL: alloca [33 x i8]
define amdgpu_kernel void @occupancy_8_over(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #6 { define amdgpu_kernel void @occupancy_8_over(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #6 {
entry: entry:
%stack = alloca [33 x i8], align 4 %stack = alloca [33 x i8], align 4, addrspace(5)
%tmp = load i8, i8 addrspace(1)* %in, align 1 %tmp = load i8, i8 addrspace(1)* %in, align 1
%tmp4 = sext i8 %tmp to i64 %tmp4 = sext i8 %tmp to i64
%arrayidx1 = getelementptr inbounds [33 x i8], [33 x i8]* %stack, i64 0, i64 %tmp4 %arrayidx1 = getelementptr inbounds [33 x i8], [33 x i8] addrspace(5)* %stack, i64 0, i64 %tmp4
store i8 4, i8* %arrayidx1, align 1 store i8 4, i8 addrspace(5)* %arrayidx1, align 1
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1
%tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1 %tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1
%tmp5 = sext i8 %tmp1 to i64 %tmp5 = sext i8 %tmp1 to i64
%arrayidx3 = getelementptr inbounds [33 x i8], [33 x i8]* %stack, i64 0, i64 %tmp5 %arrayidx3 = getelementptr inbounds [33 x i8], [33 x i8] addrspace(5)* %stack, i64 0, i64 %tmp5
store i8 5, i8* %arrayidx3, align 1 store i8 5, i8 addrspace(5)* %arrayidx3, align 1
%arrayidx10 = getelementptr inbounds [33 x i8], [33 x i8]* %stack, i64 0, i64 0 %arrayidx10 = getelementptr inbounds [33 x i8], [33 x i8] addrspace(5)* %stack, i64 0, i64 0
%tmp2 = load i8, i8* %arrayidx10, align 1 %tmp2 = load i8, i8 addrspace(5)* %arrayidx10, align 1
store i8 %tmp2, i8 addrspace(1)* %out, align 1 store i8 %tmp2, i8 addrspace(1)* %out, align 1
%arrayidx12 = getelementptr inbounds [33 x i8], [33 x i8]* %stack, i64 0, i64 1 %arrayidx12 = getelementptr inbounds [33 x i8], [33 x i8] addrspace(5)* %stack, i64 0, i64 1
%tmp3 = load i8, i8* %arrayidx12, align 1 %tmp3 = load i8, i8 addrspace(5)* %arrayidx12, align 1
%arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1 %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1 store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1
ret void ret void
Context not available.
; CI-NOT: alloca ; CI-NOT: alloca
define amdgpu_kernel void @occupancy_9(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #7 { define amdgpu_kernel void @occupancy_9(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #7 {
entry: entry:
%stack = alloca [28 x i8], align 4 %stack = alloca [28 x i8], align 4, addrspace(5)
%tmp = load i8, i8 addrspace(1)* %in, align 1 %tmp = load i8, i8 addrspace(1)* %in, align 1
%tmp4 = sext i8 %tmp to i64 %tmp4 = sext i8 %tmp to i64
%arrayidx1 = getelementptr inbounds [28 x i8], [28 x i8]* %stack, i64 0, i64 %tmp4 %arrayidx1 = getelementptr inbounds [28 x i8], [28 x i8] addrspace(5)* %stack, i64 0, i64 %tmp4
store i8 4, i8* %arrayidx1, align 1 store i8 4, i8 addrspace(5)* %arrayidx1, align 1
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1
%tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1 %tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1
%tmp5 = sext i8 %tmp1 to i64 %tmp5 = sext i8 %tmp1 to i64
%arrayidx3 = getelementptr inbounds [28 x i8], [28 x i8]* %stack, i64 0, i64 %tmp5 %arrayidx3 = getelementptr inbounds [28 x i8], [28 x i8] addrspace(5)* %stack, i64 0, i64 %tmp5
store i8 5, i8* %arrayidx3, align 1 store i8 5, i8 addrspace(5)* %arrayidx3, align 1
%arrayidx10 = getelementptr inbounds [28 x i8], [28 x i8]* %stack, i64 0, i64 0 %arrayidx10 = getelementptr inbounds [28 x i8], [28 x i8] addrspace(5)* %stack, i64 0, i64 0
%tmp2 = load i8, i8* %arrayidx10, align 1 %tmp2 = load i8, i8 addrspace(5)* %arrayidx10, align 1
store i8 %tmp2, i8 addrspace(1)* %out, align 1 store i8 %tmp2, i8 addrspace(1)* %out, align 1
%arrayidx12 = getelementptr inbounds [28 x i8], [28 x i8]* %stack, i64 0, i64 1 %arrayidx12 = getelementptr inbounds [28 x i8], [28 x i8] addrspace(5)* %stack, i64 0, i64 1
%tmp3 = load i8, i8* %arrayidx12, align 1 %tmp3 = load i8, i8 addrspace(5)* %arrayidx12, align 1
%arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1 %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1 store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1
ret void ret void
Context not available.
; ALL: alloca [29 x i8] ; ALL: alloca [29 x i8]
define amdgpu_kernel void @occupancy_9_over(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #7 { define amdgpu_kernel void @occupancy_9_over(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %in) #7 {
entry: entry:
%stack = alloca [29 x i8], align 4 %stack = alloca [29 x i8], align 4, addrspace(5)
%tmp = load i8, i8 addrspace(1)* %in, align 1 %tmp = load i8, i8 addrspace(1)* %in, align 1
%tmp4 = sext i8 %tmp to i64 %tmp4 = sext i8 %tmp to i64
%arrayidx1 = getelementptr inbounds [29 x i8], [29 x i8]* %stack, i64 0, i64 %tmp4 %arrayidx1 = getelementptr inbounds [29 x i8], [29 x i8] addrspace(5)* %stack, i64 0, i64 %tmp4
store i8 4, i8* %arrayidx1, align 1 store i8 4, i8 addrspace(5)* %arrayidx1, align 1
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 1
%tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1 %tmp1 = load i8, i8 addrspace(1)* %arrayidx2, align 1
%tmp5 = sext i8 %tmp1 to i64 %tmp5 = sext i8 %tmp1 to i64
%arrayidx3 = getelementptr inbounds [29 x i8], [29 x i8]* %stack, i64 0, i64 %tmp5 %arrayidx3 = getelementptr inbounds [29 x i8], [29 x i8] addrspace(5)* %stack, i64 0, i64 %tmp5
store i8 5, i8* %arrayidx3, align 1 store i8 5, i8 addrspace(5)* %arrayidx3, align 1
%arrayidx10 = getelementptr inbounds [29 x i8], [29 x i8]* %stack, i64 0, i64 0 %arrayidx10 = getelementptr inbounds [29 x i8], [29 x i8] addrspace(5)* %stack, i64 0, i64 0
%tmp2 = load i8, i8* %arrayidx10, align 1 %tmp2 = load i8, i8 addrspace(5)* %arrayidx10, align 1
store i8 %tmp2, i8 addrspace(1)* %out, align 1 store i8 %tmp2, i8 addrspace(1)* %out, align 1
%arrayidx12 = getelementptr inbounds [29 x i8], [29 x i8]* %stack, i64 0, i64 1 %arrayidx12 = getelementptr inbounds [29 x i8], [29 x i8] addrspace(5)* %stack, i64 0, i64 1
%tmp3 = load i8, i8* %arrayidx12, align 1 %tmp3 = load i8, i8 addrspace(5)* %arrayidx12, align 1
%arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1 %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 1
store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1 store i8 %tmp3, i8 addrspace(1)* %arrayidx13, align 1
ret void ret void
Context not available.

test/CodeGen/AMDGPU/lds-alignment.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz < %s | FileCheck -check-prefix=HSA -check-prefix=FUNC %s
@lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
@lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
Context not available.
ret void ret void
} }
; (7 * 8) + (39 * 4) = 212 ; (7 addrspace(5)* 8) + (39 addrspace(5)* 4) = 212
; HSA-LABEL: {{^}}test_missing_alignment_size_2_order0: ; HSA-LABEL: {{^}}test_missing_alignment_size_2_order0:
; HSA: workgroup_group_segment_byte_size = 212 ; HSA: workgroup_group_segment_byte_size = 212
; HSA: group_segment_alignment = 4 ; HSA: group_segment_alignment = 4
Context not available.
ret void ret void
} }
; (39 * 4) + (4 pad) + (7 * 8) = 216 ; (39 addrspace(5)* 4) + (4 pad) + (7 addrspace(5)* 8) = 216
; HSA-LABEL: {{^}}test_missing_alignment_size_2_order1: ; HSA-LABEL: {{^}}test_missing_alignment_size_2_order1:
; HSA: workgroup_group_segment_byte_size = 216 ; HSA: workgroup_group_segment_byte_size = 216
; HSA: group_segment_alignment = 4 ; HSA: group_segment_alignment = 4
Context not available.

test/CodeGen/AMDGPU/lds-initializer.ll

; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s 2>&1 | FileCheck %s
; CHECK: in function load_init_lds_global{{.*}}: unsupported initializer for address space ; CHECK: in function load_init_lds_global{{.*}}: unsupported initializer for address space

test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Make sure that m0 is not reinitialized in the loop. ; Make sure that m0 is not reinitialized in the loop.

test/CodeGen/AMDGPU/lds-oqap-crash.ll

; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs | FileCheck %s
; The test is for a bug in R600EmitClauseMarkers.cpp where this pass ; The test is for a bug in R600EmitClauseMarkers.cpp where this pass
; was searching for a use of the OQAP register in order to determine ; was searching for a use of the OQAP register in order to determine

test/CodeGen/AMDGPU/lds-output-queue.ll

; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s
; ;
; This test checks that the lds input queue will is empty at the end of ; This test checks that the lds input queue will is empty at the end of
; the ALU clause. ; the ALU clause.

test/CodeGen/AMDGPU/lds-size.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=ALL -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=ALL -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s
; This test makes sure we do not double count global values when they are ; This test makes sure we do not double count global values when they are
; used in different basic blocks. ; used in different basic blocks.

test/CodeGen/AMDGPU/lds-zero-initializer.ll

; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s 2>&1 | FileCheck %s
; CHECK: in function load_zeroinit_lds_global{{.*}}: unsupported initializer for address space ; CHECK: in function load_zeroinit_lds_global{{.*}}: unsupported initializer for address space

test/CodeGen/AMDGPU/legalizedag-bug-expand-setcc.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; This tests a bug where LegalizeDAG was not checking the target's ; This tests a bug where LegalizeDAG was not checking the target's
; BooleanContents value and always using one for true, when expanding ; BooleanContents value and always using one for true, when expanding

test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}kill_gs_const: ; SI-LABEL: {{^}}kill_gs_const:
; SI-NOT: v_cmpx_le_f32 ; SI-NOT: v_cmpx_le_f32

test/CodeGen/AMDGPU/llvm.SI.load.dword.ll

; RUN: llc -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
; Example of a simple geometry shader loading vertex attributes from the ; Example of a simple geometry shader loading vertex attributes from the
; ESGS ring buffer ; ESGS ring buffer

test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}test1: ;CHECK-LABEL: {{^}}test1:
;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:32 glc slc ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:32 glc slc

test/CodeGen/AMDGPU/llvm.amdgcn.alignb.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.alignbit(i32, i32, i32) #0 declare i32 @llvm.amdgcn.alignbit(i32, i32, i32) #0
declare i32 @llvm.amdgcn.alignbyte(i32, i32, i32) #0 declare i32 @llvm.amdgcn.alignbyte(i32, i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* nocapture, i32, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* nocapture, i64, i32, i32, i1) #2
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
Context not available.
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32* %out, i32* %ptr) #0 {
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32* %out, i32* %ptr) #0 {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i32: ; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i32:
; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32* %ptr) nounwind {
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i32_offset: ; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32* %ptr) nounwind {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 %id %out.gep = getelementptr i32, i32* %out, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out.gep store i32 %result, i32* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(4)* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* nocapture, i32, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* nocapture, i64, i32, i32, i1) #2
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
Context not available.
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32* %out, i32* %ptr) #0 {
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32* %out, i32* %ptr) #0 {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i32: ; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i32:
; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32* %ptr) nounwind {
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i32_offset: ; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32* %ptr) nounwind {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 %id %out.gep = getelementptr i32, i32* %out, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out.gep store i32 %result, i32* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(4)* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
target datalayout = "A5"
;CHECK-LABEL: {{^}}test1: ;CHECK-LABEL: {{^}}test1:
;CHECK-NOT: s_waitcnt ;CHECK-NOT: s_waitcnt

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
;CHECK-LABEL: {{^}}buffer_load: ;CHECK-LABEL: {{^}}buffer_load:
;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 ;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
;CHECK-LABEL: {{^}}buffer_load: ;CHECK-LABEL: {{^}}buffer_load:
;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s
target datalayout = "A5"
;CHECK-LABEL: {{^}}buffer_store: ;CHECK-LABEL: {{^}}buffer_store:
;CHECK-NOT: s_waitcnt ;CHECK-NOT: s_waitcnt

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s
target datalayout = "A5"
;CHECK-LABEL: {{^}}buffer_store: ;CHECK-LABEL: {{^}}buffer_store:
;CHECK-NOT: s_waitcnt ;CHECK-NOT: s_waitcnt

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare void @llvm.amdgcn.buffer.wbinvl1() #0 declare void @llvm.amdgcn.buffer.wbinvl1() #0

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=SI %s
declare void @llvm.amdgcn.buffer.wbinvl1.sc() #0 declare void @llvm.amdgcn.buffer.wbinvl1.sc() #0

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare void @llvm.amdgcn.buffer.wbinvl1.vol() #0 declare void @llvm.amdgcn.buffer.wbinvl1.vol() #0

test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.fabs.f16(half %a) declare half @llvm.fabs.f16(half %a)
declare i1 @llvm.amdgcn.class.f16(half %a, i32 %b) declare i1 @llvm.amdgcn.class.f16(half %a, i32 %b)

test/CodeGen/AMDGPU/llvm.amdgcn.class.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare i1 @llvm.amdgcn.class.f32(float, i32) #1 declare i1 @llvm.amdgcn.class.f32(float, i32) #1
declare i1 @llvm.amdgcn.class.f64(double, i32) #1 declare i1 @llvm.amdgcn.class.f64(double, i32) #1

test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.cos.f16(half %a) declare half @llvm.amdgcn.cos.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
declare float @llvm.amdgcn.cos.f32(float) #0 declare float @llvm.amdgcn.cos.f32(float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare float @llvm.amdgcn.cubeid(float, float, float) #0 declare float @llvm.amdgcn.cubeid(float, float, float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare float @llvm.amdgcn.cubema(float, float, float) #0 declare float @llvm.amdgcn.cubema(float, float, float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare float @llvm.amdgcn.cubesc(float, float, float) #0 declare float @llvm.amdgcn.cubesc(float, float, float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare float @llvm.amdgcn.cubetc(float, float, float) #0 declare float @llvm.amdgcn.cubetc(float, float, float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
; GCN-LABEL: {{^}}s_cvt_pkrtz_v2f16_f32: ; GCN-LABEL: {{^}}s_cvt_pkrtz_v2f16_f32:
; GCN-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x{{b|2c}} ; GCN-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x{{b|2c}}

test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.dispatch.id() #1 declare i64 @llvm.amdgcn.dispatch.id() #1

test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown-amdgiz -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target

test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c) declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)

test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone
declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone

test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s
; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s
; FIXME: Enable for VI. ; FIXME: Enable for VI.

test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) #1 declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) #1

test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.amdgcn.ds.bpermute(i32, i32) #0 declare i32 @llvm.amdgcn.ds.bpermute(i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.amdgcn.ds.permute(i32, i32) #0 declare i32 @llvm.amdgcn.ds.permute(i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0 declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #0 declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #0

test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1

test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) #0 declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) #0
declare i64 @llvm.amdgcn.fcmp.f64(double, double, i32) #0 declare i64 @llvm.amdgcn.fcmp.f64(double, double, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
declare float @llvm.amdgcn.fdiv.fast(float, float) #0 declare float @llvm.amdgcn.fdiv.fast(float, float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_fmed3_f16: ; GCN-LABEL: {{^}}test_fmed3_f16:
; GCN: v_med3_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_med3_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}

test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_fmed3: ; GCN-LABEL: {{^}}test_fmed3:
; GCN: v_med3_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_med3_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}

test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_mul_legacy_f32: ; GCN-LABEL: {{^}}test_mul_legacy_f32:

test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.fract.f16(half %a) declare half @llvm.amdgcn.fract.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
declare float @llvm.amdgcn.fract.f32(float) #0 declare float @llvm.amdgcn.fract.f32(float) #0
declare double @llvm.amdgcn.fract.f64(double) #0 declare double @llvm.amdgcn.fract.f64(double) #0

test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a) declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0
declare double @llvm.fabs.f64(double) #0 declare double @llvm.fabs.f64(double) #0

test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.frexp.mant.f16(half %a) declare half @llvm.amdgcn.frexp.mant.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0
declare double @llvm.fabs.f64(double) #0 declare double @llvm.fabs.f64(double) #0

test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
@lds0 = addrspace(3) global [512 x float] undef, align 4 @lds0 = addrspace(3) global [512 x float] undef, align 4
@lds1 = addrspace(3) global [256 x float] undef, align 4 @lds1 = addrspace(3) global [256 x float] undef, align 4

test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0 declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0 declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI
;CHECK-LABEL: {{^}}image_atomic_swap: ;CHECK-LABEL: {{^}}image_atomic_swap:
;CHECK-NOT: s_waitcnt ;CHECK-NOT: s_waitcnt

test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}gather4_v2: ; GCN-LABEL: {{^}}gather4_v2:
; GCN: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da ; GCN: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da

test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}getlod: ; GCN-LABEL: {{^}}getlod:
; GCN: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf da ; GCN: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf da

test/CodeGen/AMDGPU/llvm.amdgcn.image.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
target datalayout = "A5"
; GCN-LABEL: {{^}}image_load_v4i32: ; GCN-LABEL: {{^}}image_load_v4i32:
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt

test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}sample: ; GCN-LABEL: {{^}}sample:
; GCN: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf ; GCN: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf

test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}sample: ; GCN-LABEL: {{^}}sample:
; GCN: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf ; GCN: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf

test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.hsa.ll

; RUN: not llc -mtriple=amdgcn-amd-amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-amd-amdhsa-amdgiz < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target ; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target
define amdgpu_kernel void @test_kernel(i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @test_kernel(i32 addrspace(1)* %out) #1 {

test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
; FIXME: Requires stack object to not assert ; FIXME: Requires stack object to not assert
; GCN-LABEL: {{^}}test_ps: ; GCN-LABEL: {{^}}test_ps:
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: ; return ; GCN-NEXT: ; return
define amdgpu_ps i32 @test_ps() #1 { define amdgpu_ps i32 @test_ps() #1 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr()
%buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)*
%value = load volatile i32, i32 addrspace(2)* %buffer_ptr %value = load volatile i32, i32 addrspace(2)* %buffer_ptr
Context not available.
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:4 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:4
; GCN: s_load_dword s0, s[0:1], 0x0 ; GCN: s_load_dword s0, s[0:1], 0x0
define amdgpu_cs i32 @test_cs() #1 { define amdgpu_cs i32 @test_cs() #1 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr()
%buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)*
%value = load volatile i32, i32 addrspace(2)* %buffer_ptr %value = load volatile i32, i32 addrspace(2)* %buffer_ptr
Context not available.

test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty: ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1 ; GCN: enable_sgpr_kernarg_segment_ptr = 1

test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll

;RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GCN ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GCN
; GCN-LABEL: {{^}}full_mask: ; GCN-LABEL: {{^}}full_mask:
; GCN: s_mov_b64 exec, -1 ; GCN: s_mov_b64 exec, -1

test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -march=amdgcn -mcpu=kabini -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,16BANK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=kabini -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,16BANK %s
; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,16BANK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,16BANK %s
; GCN-LABEL: {{^}}v_interp: ; GCN-LABEL: {{^}}v_interp:
; GCN-NOT: s_wqm ; GCN-NOT: s_wqm

test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
; SI-LABEL: {{^}}gs_const: ; SI-LABEL: {{^}}gs_const:
; SI-NOT: v_cmpx ; SI-NOT: v_cmpx

test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.ldexp.f16(half %a, i32 %b) declare half @llvm.amdgcn.ldexp.f16(half %a, i32 %b)

test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare float @llvm.amdgcn.ldexp.f32(float, i32) nounwind readnone declare float @llvm.amdgcn.ldexp.f32(float, i32) nounwind readnone
declare double @llvm.amdgcn.ldexp.f64(double, i32) nounwind readnone declare double @llvm.amdgcn.ldexp.f64(double, i32) nounwind readnone

test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.lerp(i32, i32, i32) #0 declare i32 @llvm.amdgcn.lerp(i32, i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s
; ERR: intrinsic not supported on subtarget ; ERR: intrinsic not supported on subtarget

test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}mbcnt_intrinsics: ; GCN-LABEL: {{^}}mbcnt_intrinsics:
; GCN: v_mbcnt_lo_u32_b32{{(_e64)*}} [[LO:v[0-9]+]], -1, 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e64)*}} [[LO:v[0-9]+]], -1, 0

test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s
target datalayout = "A5"
; FIXME: The register allocator / scheduler should be able to avoid these hazards. ; FIXME: The register allocator / scheduler should be able to avoid these hazards.

test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64, i32, i64) #0 declare i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64, i32, i64) #0

test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64, i32, <4 x i32>) #0 declare <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64, i32, <4 x i32>) #0

test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.msad.u8(i32, i32, i32) #0 declare i32 @llvm.amdgcn.msad.u8(i32, i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test1: ; CHECK-LABEL: {{^}}test1:
; CHECK: s_mov_b64 s[0:1], exec ; CHECK: s_mov_b64 s[0:1], exec

test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.qsad.pk.u16.u8(i64, i32, i64) #0 declare i64 @llvm.amdgcn.qsad.pk.u16.u8(i64, i32, i64) #0

test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown-amdgiz -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target

test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.rcp.f16(half %a) declare half @llvm.amdgcn.rcp.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: error: <unknown>:0:0: in function rcp_legacy_f32 void (float addrspace(1)*, float): intrinsic not supported on subtarget ; ERROR: error: <unknown>:0:0: in function rcp_legacy_f32 void (float addrspace(1)*, float): intrinsic not supported on subtarget

test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.amdgcn.rcp.f32(float) #0 declare float @llvm.amdgcn.rcp.f32(float) #0
declare double @llvm.amdgcn.rcp.f64(double) #0 declare double @llvm.amdgcn.rcp.f64(double) #0

test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.amdgcn.readfirstlane(i32) #0 declare i32 @llvm.amdgcn.readfirstlane(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.amdgcn.readlane(i32, i32) #0 declare i32 @llvm.amdgcn.readlane(i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
declare float @llvm.amdgcn.rsq.clamp.f32(float) #1 declare float @llvm.amdgcn.rsq.clamp.f32(float) #1
declare double @llvm.amdgcn.rsq.clamp.f64(double) #1 declare double @llvm.amdgcn.rsq.clamp.f64(double) #1

test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.rsq.f16(half %a) declare half @llvm.amdgcn.rsq.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.amdgcn.rsq.legacy(float) #0 declare float @llvm.amdgcn.rsq.legacy(float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.amdgcn.rsq.f32(float) #0 declare float @llvm.amdgcn.rsq.f32(float) #0
declare double @llvm.amdgcn.rsq.f64(double) #0 declare double @llvm.amdgcn.rsq.f64(double) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=NOAUTO %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=NOAUTO %s
; RUN: llc -march=amdgcn -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=AUTO %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=AUTO %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=NOAUTO %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=NOAUTO %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=AUTO %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=AUTO %s
; GCN-LABEL: {{^}}test_barrier: ; GCN-LABEL: {{^}}test_barrier:
; GFX8: buffer_store_dword ; GFX8: buffer_store_dword

test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.inv() #0 declare void @llvm.amdgcn.s.dcache.inv() #0
declare void @llvm.amdgcn.s.waitcnt(i32) #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.inv.vol() #0 declare void @llvm.amdgcn.s.dcache.inv.vol() #0
declare void @llvm.amdgcn.s.waitcnt(i32) #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll

; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.wb() #0 declare void @llvm.amdgcn.s.dcache.wb() #0
declare void @llvm.amdgcn.s.waitcnt(i32) #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll

; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.wb.vol() #0 declare void @llvm.amdgcn.s.dcache.wb.vol() #0
declare void @llvm.amdgcn.s.waitcnt(i32) #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare void @llvm.amdgcn.s.decperflevel(i32) #0 declare void @llvm.amdgcn.s.decperflevel(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.s.getpc() #0 declare i64 @llvm.amdgcn.s.getpc() #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}s_getreg_test: ; GCN-LABEL: {{^}}s_getreg_test:
; GCN: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23) ; GCN: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23)

test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare void @llvm.amdgcn.s.incperflevel(i32) #0 declare void @llvm.amdgcn.s.incperflevel(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
declare i64 @llvm.amdgcn.s.memrealtime() #0 declare i64 @llvm.amdgcn.s.memrealtime() #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
declare i64 @llvm.amdgcn.s.memtime() #0 declare i64 @llvm.amdgcn.s.memtime() #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare void @llvm.amdgcn.s.sleep(i32) #0 declare void @llvm.amdgcn.s.sleep(i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test1: ; CHECK-LABEL: {{^}}test1:
; CHECK-NOT: s_waitcnt ; CHECK-NOT: s_waitcnt

test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.sad.hi.u8(i32, i32, i32) #0 declare i32 @llvm.amdgcn.sad.hi.u8(i32, i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.sad.u16(i32, i32, i32) #0 declare i32 @llvm.amdgcn.sad.u16(i32, i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.sad.u8(i32, i32, i32) #0 declare i32 @llvm.amdgcn.sad.u8(i32, i32, i32) #0

test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}bfe_i32_arg_arg_arg: ; GCN-LABEL: {{^}}bfe_i32_arg_arg_arg:
; GCN: v_bfe_i32 ; GCN: v_bfe_i32

test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll

;RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ;RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ;RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}test_interrupt: ; GCN-LABEL: {{^}}test_interrupt:
; GCN: s_mov_b32 m0, 0 ; GCN: s_mov_b32 m0, 0

test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; GCN-LABEL: {{^}}set_inactive: ; GCN-LABEL: {{^}}set_inactive:

test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.sffbh.i32(i32) #1 declare i32 @llvm.amdgcn.sffbh.i32(i32) #1

test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.amdgcn.sin.f16(half %a) declare half @llvm.amdgcn.sin.f16(half %a)

test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
declare float @llvm.amdgcn.sin.f32(float) #0 declare float @llvm.amdgcn.sin.f32(float) #0

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}tbuffer_load: ; GCN-LABEL: {{^}}tbuffer_load:
; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 ; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
; GCN-LABEL: {{^}}tbuffer_store: ; GCN-LABEL: {{^}}tbuffer_store:
; GCN: tbuffer_store_format_xyzw v[0:3], off, s[0:3], dfmt:12, nfmt:2, 0 ; GCN: tbuffer_store_format_xyzw v[0:3], off, s[0:3], dfmt:12, nfmt:2, 0

test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone

test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}bfe_u32_arg_arg_arg: ; GCN-LABEL: {{^}}bfe_u32_arg_arg_arg:
; GCN: v_bfe_u32 ; GCN: v_bfe_u32

test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s
; VI-LABEL: {{^}}dpp_test: ; VI-LABEL: {{^}}dpp_test:
; VI: v_mov_b32_e32 v0, s{{[0-9]+}} ; VI: v_mov_b32_e32 v0, s{{[0-9]+}}

test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_wave_barrier: ; GCN-LABEL: {{^}}test_wave_barrier:
; GCN-DAG: ; wave barrier ; GCN-DAG: ; wave barrier

test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0

test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0

test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CHECK %s
;CHECK-LABEL: {{^}}ret: ;CHECK-LABEL: {{^}}ret:
;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1 ;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1

test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}kilp_gs_const: ; SI-LABEL: {{^}}kilp_gs_const:
; SI: s_mov_b64 exec, 0 ; SI: s_mov_b64 exec, 0

test/CodeGen/AMDGPU/llvm.ceil.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.ceil.f16(half %a) declare half @llvm.ceil.f16(half %a)
declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a) declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.cos.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.cos.f16(half %a) declare half @llvm.cos.f16(half %a)
declare <2 x half> @llvm.cos.v2f16(<2 x half> %a) declare <2 x half> @llvm.cos.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.dbg.value.ll

; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -mattr=-flat-for-global < %s | FileCheck %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -verify-machineinstrs -mattr=-flat-for-global < %s | FileCheck %s
; CHECK-LABEL: {{^}}test_debug_value: ; CHECK-LABEL: {{^}}test_debug_value:
; CHECK: s_load_dwordx2 s[4:5] ; CHECK: s_load_dwordx2 s[4:5]

test/CodeGen/AMDGPU/llvm.exp2.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.exp2.f16(half %a) declare half @llvm.exp2.f16(half %a)
declare <2 x half> @llvm.exp2.v2f16(<2 x half> %a) declare <2 x half> @llvm.exp2.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.exp2.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
;RUN: llc < %s -march=amdgcn | FileCheck %s --check-prefix=SI --check-prefix=FUNC ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz | FileCheck %s --check-prefix=SI --check-prefix=FUNC
;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC
;FUNC-LABEL: {{^}}test: ;FUNC-LABEL: {{^}}test:
;EG: EXP_IEEE ;EG: EXP_IEEE

test/CodeGen/AMDGPU/llvm.floor.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.floor.f16(half %a) declare half @llvm.floor.f16(half %a)
declare <2 x half> @llvm.floor.v2f16(<2 x half> %a) declare <2 x half> @llvm.floor.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.fma.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.fma.f16(half %a, half %b, half %c) declare half @llvm.fma.f16(half %a, half %b, half %c)
declare <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) declare <2 x half> @llvm.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)

test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-FLUSH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-FLUSH %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -mattr=+fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-DENORM %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SI-DENORM %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s
declare half @llvm.fmuladd.f16(half %a, half %b, half %c) declare half @llvm.fmuladd.f16(half %a, half %b, half %c)
declare <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) declare <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)

test/CodeGen/AMDGPU/llvm.log2.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.log2.f16(half %a) declare half @llvm.log2.f16(half %a)
declare <2 x half> @llvm.log2.v2f16(<2 x half> %a) declare <2 x half> @llvm.log2.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.log2.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
;RUN: llc < %s -march=amdgcn -mcpu=tahiti | FileCheck %s --check-prefix=SI --check-prefix=FUNC ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti | FileCheck %s --check-prefix=SI --check-prefix=FUNC
;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC
;FUNC-LABEL: {{^}}test: ;FUNC-LABEL: {{^}}test:
;EG: LOG_IEEE ;EG: LOG_IEEE

test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.maxnum.f16(half %a, half %b) declare half @llvm.maxnum.f16(half %a, half %b)
declare <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b) declare <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)

test/CodeGen/AMDGPU/llvm.memcpy.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare void @llvm.memcpy.p3i8.p3i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(3)* nocapture, i32, i32, i1) nounwind declare void @llvm.memcpy.p3i8.p3i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(3)* nocapture, i32, i32, i1) nounwind
declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind

test/CodeGen/AMDGPU/llvm.minnum.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.minnum.f16(half %a, half %b) declare half @llvm.minnum.f16(half %a, half %b)
declare <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b) declare <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)

test/CodeGen/AMDGPU/llvm.pow.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK-LABEL: test1: ;CHECK-LABEL: test1:
;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},

test/CodeGen/AMDGPU/llvm.r600.dot4.ll

; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s
declare float @llvm.r600.dot4(<4 x float>, <4 x float>) nounwind readnone declare float @llvm.r600.dot4(<4 x float>, <4 x float>) nounwind readnone

test/CodeGen/AMDGPU/llvm.r600.group.barrier.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
; EG-LABEL: {{^}}test_group_barrier: ; EG-LABEL: {{^}}test_group_barrier:
; EG: GROUP_BARRIER ; EG: GROUP_BARRIER

test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}local_size_x: ; FUNC-LABEL: {{^}}local_size_x:

test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
declare float @llvm.r600.recipsqrt.clamped.f32(float) nounwind readnone declare float @llvm.r600.recipsqrt.clamped.f32(float) nounwind readnone

test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
declare float @llvm.r600.recipsqrt.ieee.f32(float) nounwind readnone declare float @llvm.r600.recipsqrt.ieee.f32(float) nounwind readnone

test/CodeGen/AMDGPU/llvm.r600.tex.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN

test/CodeGen/AMDGPU/llvm.rint.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=GFX89 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s
declare half @llvm.rint.f16(half %a) declare half @llvm.rint.f16(half %a)
declare <2 x half> @llvm.rint.v2f16(<2 x half> %a) declare <2 x half> @llvm.rint.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.rint.f64.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}rint_f64: ; FUNC-LABEL: {{^}}rint_f64:
; CI: v_rndne_f64_e32 ; CI: v_rndne_f64_e32

test/CodeGen/AMDGPU/llvm.rint.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
; FUNC-LABEL: {{^}}rint_f32: ; FUNC-LABEL: {{^}}rint_f32:
; R600: RNDNE ; R600: RNDNE

test/CodeGen/AMDGPU/llvm.round.f64.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}round_f64: ; FUNC-LABEL: {{^}}round_f64:
; SI: s_endpgm ; SI: s_endpgm

test/CodeGen/AMDGPU/llvm.round.ll

; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}round_f32: ; FUNC-LABEL: {{^}}round_f32:
; GCN-DAG: s_load_dword [[SX:s[0-9]+]] ; GCN-DAG: s_load_dword [[SX:s[0-9]+]]

test/CodeGen/AMDGPU/llvm.sin.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.sin.f16(half %a) declare half @llvm.sin.f16(half %a)
declare <2 x half> @llvm.sin.v2f16(<2 x half> %a) declare <2 x half> @llvm.sin.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.sqrt.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.sqrt.f16(half %a) declare half @llvm.sqrt.f16(half %a)
declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a) declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/llvm.trunc.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare half @llvm.trunc.f16(half %a) declare half @llvm.trunc.f16(half %a)
declare <2 x half> @llvm.trunc.v2f16(<2 x half> %a) declare <2 x half> @llvm.trunc.v2f16(<2 x half> %a)

test/CodeGen/AMDGPU/load-constant-f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_f64: ; FUNC-LABEL: {{^}}constant_load_f64:
; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}] ; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}]

test/CodeGen/AMDGPU/load-constant-i16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i16: ; FUNC-LABEL: {{^}}constant_load_i16:
; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}} ; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}}

test/CodeGen/AMDGPU/load-constant-i32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i32: ; FUNC-LABEL: {{^}}constant_load_i32:
; GCN: s_load_dword s{{[0-9]+}} ; GCN: s_load_dword s{{[0-9]+}}

test/CodeGen/AMDGPU/load-constant-i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=VI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i64: ; FUNC-LABEL: {{^}}constant_load_i64:

test/CodeGen/AMDGPU/load-constant-i8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i8: ; FUNC-LABEL: {{^}}constant_load_i8:

test/CodeGen/AMDGPU/load-global-f32.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_f32: ; FUNC-LABEL: {{^}}global_load_f32:
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}} ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}

test/CodeGen/AMDGPU/load-global-f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_f64: ; FUNC-LABEL: {{^}}global_load_f64:
; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]

test/CodeGen/AMDGPU/load-global-i16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-HSA,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-HSA,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=EGCM -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=EGCM -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=EGCM -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=EGCM -check-prefix=FUNC %s
; FIXME: r600 is broken because the bigger testcases spill and it's not implemented ; FIXME: r600 is broken because the bigger testcases spill and it's not implemented

test/CodeGen/AMDGPU/load-global-i32.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_i32: ; FUNC-LABEL: {{^}}global_load_i32:

test/CodeGen/AMDGPU/load-global-i64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_i64: ; FUNC-LABEL: {{^}}global_load_i64:
; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]

test/CodeGen/AMDGPU/load-global-i8.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-HSA,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-HSA,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,VI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_i8: ; FUNC-LABEL: {{^}}global_load_i8:

test/CodeGen/AMDGPU/load-hi16.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; GCN-LABEL: {{^}}load_local_hi_v2i16_undeflo: ; GCN-LABEL: {{^}}load_local_hi_v2i16_undeflo:
; GCN: s_waitcnt ; GCN: s_waitcnt
Context not available.
; VI: flat_load_ushort v{{[0-9]+}} ; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2i16_reglo_vreg(i16 addrspace(4)* %in, i16 %reg) #0 { define void @load_flat_hi_v2i16_reglo_vreg(i16* %in, i16 %reg) #0 {
entry: entry:
%load = load i16, i16 addrspace(4)* %in %load = load i16, i16* %in
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
Context not available.
; VI: flat_load_ushort v{{[0-9]+}} ; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2f16_reglo_vreg(half addrspace(4)* %in, half %reg) #0 { define void @load_flat_hi_v2f16_reglo_vreg(half* %in, half %reg) #0 {
entry: entry:
%load = load half, half addrspace(4)* %in %load = load half, half* %in
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
Context not available.
; VI: flat_load_ubyte v{{[0-9]+}} ; VI: flat_load_ubyte v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(4)* %in, i16 %reg) #0 { define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8* %in, i16 %reg) #0 {
entry: entry:
%load = load i8, i8 addrspace(4)* %in %load = load i8, i8* %in
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
Context not available.
; VI: flat_load_sbyte v{{[0-9]+}} ; VI: flat_load_sbyte v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(4)* %in, i16 %reg) #0 { define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8* %in, i16 %reg) #0 {
entry: entry:
%load = load i8, i8 addrspace(4)* %in %load = load i8, i8* %in
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg(i16* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16* %in, i64 2047 %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2047
%load = load i16, i16* %gep %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg(half* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* %in, half %reg) #0 {
entry: entry:
%gep = getelementptr inbounds half, half* %in, i64 2047 %gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2047
%load = load half, half* %gep %load = load half, half addrspace(5)* %gep
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff(i16* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i16, i16* inttoptr (i32 4094 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff(half* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, half %reg) #0 {
entry: entry:
%load = load volatile half, half* inttoptr (i32 4094 to half*) %load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v{{[0-9]+}}, v0, s[0:3], s4 offen offset:2047{{$}} ; VI: buffer_load_ubyte v{{[0-9]+}}, v0, s[0:3], s4 offen offset:2047{{$}}
define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i8, i8* %in, i64 2047 %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 2047
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v{{[0-9]+}}, v0, s[0:3], s4 offen offset:2047{{$}} ; VI: buffer_load_sbyte v{{[0-9]+}}, v0, s[0:3], s4 offen offset:2047{{$}}
define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i8, i8* %in, i64 2047 %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 2047
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
Context not available.
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, half %reg) #0 {
entry: entry:
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%bc.ext = bitcast i16 %ext to half %bc.ext = bitcast i16 %ext to half
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
Context not available.

test/CodeGen/AMDGPU/load-input-fold.ll

;RUN: llc < %s -march=r600 -mcpu=cayman ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) { define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
main_body: main_body:

test/CodeGen/AMDGPU/load-local-f32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}load_f32_local: ; FUNC-LABEL: {{^}}load_f32_local:
; GCN: s_mov_b32 m0 ; GCN: s_mov_b32 m0

test/CodeGen/AMDGPU/load-local-f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}local_load_f64: ; FUNC-LABEL: {{^}}local_load_f64:
; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}} ; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}

test/CodeGen/AMDGPU/load-local-i16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}local_load_i16: ; FUNC-LABEL: {{^}}local_load_i16:
; GCN: ds_read_u16 v{{[0-9]+}} ; GCN: ds_read_u16 v{{[0-9]+}}

test/CodeGen/AMDGPU/load-local-i32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}local_load_i32: ; FUNC-LABEL: {{^}}local_load_i32:

test/CodeGen/AMDGPU/load-local-i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}local_load_i64: ; FUNC-LABEL: {{^}}local_load_i64:
; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}} ; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}

test/CodeGen/AMDGPU/load-weird-sizes.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=CI-HSA -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=CI-HSA -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=CM -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=CM -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}load_i24: ; FUNC-LABEL: {{^}}load_i24:
; SI-DAG: {{flat|buffer}}_load_ubyte ; SI-DAG: {{flat|buffer}}_load_ubyte

test/CodeGen/AMDGPU/local-64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=BOTH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=BOTH %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
; BOTH-LABEL: {{^}}local_i32_load ; BOTH-LABEL: {{^}}local_i32_load
; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 ; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28

test/CodeGen/AMDGPU/local-atomics.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32: ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32:
; EG: LDS_WRXCHG_RET * ; EG: LDS_WRXCHG_RET *

test/CodeGen/AMDGPU/local-atomics64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
; GCN-LABEL: {{^}}lds_atomic_xchg_ret_i64: ; GCN-LABEL: {{^}}lds_atomic_xchg_ret_i64:
; GCN: ds_wrxchg_rtn_b64 ; GCN: ds_wrxchg_rtn_b64

test/CodeGen/AMDGPU/local-memory.amdgcn.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4

test/CodeGen/AMDGPU/local-memory.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4

test/CodeGen/AMDGPU/local-memory.r600.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4

test/CodeGen/AMDGPU/local-stack-slot-offset.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
target datalayout = "A5"
; Allocate two stack slots of 2052 bytes each requiring a total of 4104 bytes. ; Allocate two stack slots of 2052 bytes each requiring a total of 4104 bytes.
; Extracting the last element of each does not fit into the offset field of ; Extracting the last element of each does not fit into the offset field of
Context not available.
; CHECK: buffer_load_dword ; CHECK: buffer_load_dword
define amdgpu_gs float @main(float %v1, float %v2, i32 %idx1, i32 %idx2) { define amdgpu_gs float @main(float %v1, float %v2, i32 %idx1, i32 %idx2) {
main_body: main_body:
%m1 = alloca [513 x float] %m1 = alloca [513 x float], addrspace(5)
%m2 = alloca [513 x float] %m2 = alloca [513 x float], addrspace(5)
%gep1.store = getelementptr [513 x float], [513 x float]* %m1, i32 0, i32 %idx1 %gep1.store = getelementptr [513 x float], [513 x float] addrspace(5)* %m1, i32 0, i32 %idx1
store float %v1, float* %gep1.store store float %v1, float addrspace(5)* %gep1.store
%gep2.store = getelementptr [513 x float], [513 x float]* %m2, i32 0, i32 %idx2 %gep2.store = getelementptr [513 x float], [513 x float] addrspace(5)* %m2, i32 0, i32 %idx2
store float %v2, float* %gep2.store store float %v2, float addrspace(5)* %gep2.store
; This used to use a base reg equal to 0. ; This used to use a base reg equal to 0.
%gep1.load = getelementptr [513 x float], [513 x float]* %m1, i32 0, i32 0 %gep1.load = getelementptr [513 x float], [513 x float] addrspace(5)* %m1, i32 0, i32 0
%out1 = load float, float* %gep1.load %out1 = load float, float addrspace(5)* %gep1.load
; This used to attempt to re-use the base reg at 0, generating an out-of-bounds instruction offset. ; This used to attempt to re-use the base reg at 0, generating an out-of-bounds instruction offset.
%gep2.load = getelementptr [513 x float], [513 x float]* %m2, i32 0, i32 512 %gep2.load = getelementptr [513 x float], [513 x float] addrspace(5)* %m2, i32 0, i32 512
%out2 = load float, float* %gep2.load %out2 = load float, float addrspace(5)* %gep2.load
%r = fadd float %out1, %out2 %r = fadd float %out1, %out2
ret float %r ret float %r
Context not available.

test/CodeGen/AMDGPU/loop-address.ll

;RUN: llc < %s -march=r600 -mcpu=redwood < %s | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s
;CHECK: ALU_PUSH ;CHECK: ALU_PUSH
;CHECK: LOOP_START_DX10 @11 ;CHECK: LOOP_START_DX10 @11

test/CodeGen/AMDGPU/loop-idiom.ll

; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s ; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
; RUN: opt -basicaa -loop-idiom -S < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: opt -basicaa -loop-idiom -S < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: opt -basicaa -loop-idiom -S < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: opt -basicaa -loop-idiom -S < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
target datalayout = "A5"
; Make sure loop-idiom doesn't create memcpy or memset. There are no library ; Make sure loop-idiom doesn't create memcpy or memset. There are no library
Context not available.
; SI-NOT: {{^}}llvm.memcpy ; SI-NOT: {{^}}llvm.memcpy
define amdgpu_kernel void @no_memcpy(i8 addrspace(3)* %in, i32 %size) { define amdgpu_kernel void @no_memcpy(i8 addrspace(3)* %in, i32 %size) {
entry: entry:
%dest = alloca i8, i32 32 %dest = alloca i8, i32 32, addrspace(5)
br label %for.body br label %for.body
for.body: for.body:
%0 = phi i32 [0, %entry], [%4, %for.body] %0 = phi i32 [0, %entry], [%4, %for.body]
%1 = getelementptr i8, i8 addrspace(3)* %in, i32 %0 %1 = getelementptr i8, i8 addrspace(3)* %in, i32 %0
%2 = getelementptr i8, i8* %dest, i32 %0 %2 = getelementptr i8, i8 addrspace(5)* %dest, i32 %0
%3 = load i8, i8 addrspace(3)* %1 %3 = load i8, i8 addrspace(3)* %1
store i8 %3, i8* %2 store i8 %3, i8 addrspace(5)* %2
%4 = add i32 %0, 1 %4 = add i32 %0, 1
%5 = icmp eq i32 %4, %size %5 = icmp eq i32 %4, %size
br i1 %5, label %for.end, label %for.body br i1 %5, label %for.end, label %for.body
Context not available.
; SI-NOT: {{^}}memset_pattern16: ; SI-NOT: {{^}}memset_pattern16:
define amdgpu_kernel void @no_memset(i32 %size) { define amdgpu_kernel void @no_memset(i32 %size) {
entry: entry:
%dest = alloca i8, i32 32 %dest = alloca i8, i32 32, addrspace(5)
br label %for.body br label %for.body
for.body: for.body:
%0 = phi i32 [0, %entry], [%2, %for.body] %0 = phi i32 [0, %entry], [%2, %for.body]
%1 = getelementptr i8, i8* %dest, i32 %0 %1 = getelementptr i8, i8 addrspace(5)* %dest, i32 %0
store i8 0, i8* %1 store i8 0, i8 addrspace(5)* %1
%2 = add i32 %0, 1 %2 = add i32 %0, 1
%3 = icmp eq i32 %2, %size %3 = icmp eq i32 %2, %size
br i1 %3, label %for.end, label %for.body br i1 %3, label %for.end, label %for.body
Context not available.

test/CodeGen/AMDGPU/loop_break.ll

; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn---amdgiz -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Uses llvm.amdgcn.break ; Uses llvm.amdgcn.break

test/CodeGen/AMDGPU/lower-kernel-calls.ll

; RUN: opt -amdgpu-lower-kernel-calls -mtriple=amdgcn--amdhsa -mcpu=fiji -S < %s | FileCheck %s ; RUN: opt -amdgpu-lower-kernel-calls -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -S < %s | FileCheck %s
define amdgpu_kernel void @test_kernel_to_call(i32 addrspace(1)* %p) #0 { define amdgpu_kernel void @test_kernel_to_call(i32 addrspace(1)* %p) #0 {
entry: entry:
store i32 2, i32 addrspace(1)* %p, align 4 store i32 2, i32 addrspace(1)* %p, align 4

test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz < %s | FileCheck %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown-amdgiz < %s | FileCheck %s
; and can be eliminated ; and can be eliminated
; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range: ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:

test/CodeGen/AMDGPU/lshl64-to-32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}zext_shl64_to_32: ; GCN-LABEL: {{^}}zext_shl64_to_32:
; GCN: s_lshl_b32 ; GCN: s_lshl_b32

test/CodeGen/AMDGPU/lshr.v2i16.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
; GCN-LABEL: {{^}}s_lshr_v2i16: ; GCN-LABEL: {{^}}s_lshr_v2i16:
; GFX9: s_load_dword [[LHS:s[0-9]+]] ; GFX9: s_load_dword [[LHS:s[0-9]+]]

test/CodeGen/AMDGPU/mad-combine.ll

; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma. ; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=SI-STD-SAFE -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=SI-STD-SAFE -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=SI-STD-SAFE -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=SI-STD-SAFE -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=SI-STD-UNSAFE -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=SI-STD-UNSAFE -check-prefix=FUNC %s
; Make sure we don't form mad with denormals ; Make sure we don't form mad with denormals
; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=SI-DENORM-FASTFMAF -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=SI-DENORM-FASTFMAF -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=SI-DENORM-SLOWFMAF -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=SI-DENORM-SLOWFMAF -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0

test/CodeGen/AMDGPU/mad-mix-hi.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo: ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
; GFX9: s_waitcnt ; GFX9: s_waitcnt

test/CodeGen/AMDGPU/mad-mix-lo.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
; GCN-LABEL: mixlo_simple: ; GCN-LABEL: mixlo_simple:
; GCN: s_waitcnt ; GCN: s_waitcnt

test/CodeGen/AMDGPU/mad-mix.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo: ; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo:
; GFX9: v_mad_mix_f32 v0, v0, v1, v2 ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c] ; GFX9: v_mad_mix_f32 v0, v0, v1, v2 ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]

test/CodeGen/AMDGPU/mad24-get-global-id.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; If the workgroup id range is restricted, we should be able to use ; If the workgroup id range is restricted, we should be able to use
; mad24 for the usual indexing pattern. ; mad24 for the usual indexing pattern.

test/CodeGen/AMDGPU/mad_64_32.ll

; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; GCN-LABEL: {{^}}mad_i64_i32_sextops: ; GCN-LABEL: {{^}}mad_i64_i32_sextops:
; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3] ; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]

test/CodeGen/AMDGPU/mad_int24.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
; FUNC-LABEL: {{^}}i32_mad24: ; FUNC-LABEL: {{^}}i32_mad24:
; Signed 24-bit multiply is not supported on pre-Cayman GPUs. ; Signed 24-bit multiply is not supported on pre-Cayman GPUs.

test/CodeGen/AMDGPU/mad_uint24.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
declare i32 @llvm.r600.read.tidig.x() nounwind readnone declare i32 @llvm.r600.read.tidig.x() nounwind readnone

test/CodeGen/AMDGPU/madak.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; FIXME: Enable VI ; FIXME: Enable VI

test/CodeGen/AMDGPU/madmk.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; FIXME: None of these trigger madmk emission anymore. It is still ; FIXME: None of these trigger madmk emission anymore. It is still
; possible, but requires the correct registers to be used which is ; possible, but requires the correct registers to be used which is

test/CodeGen/AMDGPU/max.i16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VIPLUS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VIPLUS %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=VIPLUS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=VIPLUS %s
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_imax_sge_i16: ; GCN-LABEL: {{^}}v_test_imax_sge_i16:

test/CodeGen/AMDGPU/max.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}v_test_imax_sge_i32: ; FUNC-LABEL: {{^}}v_test_imax_sge_i32:

test/CodeGen/AMDGPU/max3.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}v_test_imax3_sgt_i32: ; GCN-LABEL: {{^}}v_test_imax3_sgt_i32:
; GCN: v_max3_i32 ; GCN: v_max3_i32

test/CodeGen/AMDGPU/mem-builtins.ll

; RUN: not llc -march=r600 < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=r600 -mtriple=r600---amdgiz < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=GCN %s
declare i32 @memcmp(i8 addrspace(1)* readonly nocapture, i8 addrspace(1)* readonly nocapture, i64) #0 declare i32 @memcmp(i8 addrspace(1)* readonly nocapture, i8 addrspace(1)* readonly nocapture, i64) #0
declare i8 addrspace(1)* @memchr(i8 addrspace(1)* readonly nocapture, i32, i64) #1 declare i8 addrspace(1)* @memchr(i8 addrspace(1)* readonly nocapture, i32, i64) #1
declare i8* @strcpy(i8* nocapture, i8* readonly nocapture) #0 declare i8 addrspace(5)* @strcpy(i8 addrspace(5)* nocapture, i8 addrspace(5)* readonly nocapture) #0
declare i32 @strlen(i8* nocapture) #1 declare i32 @strlen(i8 addrspace(5)* nocapture) #1
declare i32 @strnlen(i8* nocapture, i32) #1 declare i32 @strnlen(i8 addrspace(5)* nocapture, i32) #1
declare i32 @strcmp(i8* nocapture, i8* nocapture) #1 declare i32 @strcmp(i8 addrspace(5)* nocapture, i8 addrspace(5)* nocapture) #1
; ERROR: error: <unknown>:0:0: in function test_memcmp void (i8 addrspace(1)*, i8 addrspace(1)*, i32*): unsupported call to function memcmp ; ERROR: error: <unknown>:0:0: in function test_memcmp void (i8 addrspace(1)*, i8 addrspace(1)*, i32 addrspace(5)*): unsupported call to function memcmp
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, memcmp@rel32@hi+4
define amdgpu_kernel void @test_memcmp(i8 addrspace(1)* %x, i8 addrspace(1)* %y, i32* nocapture %p) #0 { define amdgpu_kernel void @test_memcmp(i8 addrspace(1)* %x, i8 addrspace(1)* %y, i32 addrspace(5)* nocapture %p) #0 {
entry: entry:
%cmp = tail call i32 @memcmp(i8 addrspace(1)* %x, i8 addrspace(1)* %y, i64 2) %cmp = tail call i32 @memcmp(i8 addrspace(1)* %x, i8 addrspace(1)* %y, i64 2)
store volatile i32 %cmp, i32 addrspace(1)* undef store volatile i32 %cmp, i32 addrspace(1)* undef
Context not available.
ret void ret void
} }
; ERROR: error: <unknown>:0:0: in function test_strcpy void (i8*, i8*): unsupported call to function strcpy ; ERROR: error: <unknown>:0:0: in function test_strcpy void (i8 addrspace(5)*, i8 addrspace(5)*): unsupported call to function strcpy
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcpy@rel32@hi+4
define amdgpu_kernel void @test_strcpy(i8* %dst, i8* %src) #0 { define amdgpu_kernel void @test_strcpy(i8 addrspace(5)* %dst, i8 addrspace(5)* %src) #0 {
%res = call i8* @strcpy(i8* %dst, i8* %src) %res = call i8 addrspace(5)* @strcpy(i8 addrspace(5)* %dst, i8 addrspace(5)* %src)
store volatile i8* %res, i8* addrspace(1)* undef store volatile i8 addrspace(5)* %res, i8 addrspace(5)* addrspace(1)* undef
ret void ret void
} }
; ERROR: error: <unknown>:0:0: in function test_strcmp void (i8*, i8*): unsupported call to function strcmp ; ERROR: error: <unknown>:0:0: in function test_strcmp void (i8 addrspace(5)*, i8 addrspace(5)*): unsupported call to function strcmp
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strcmp@rel32@hi+4
define amdgpu_kernel void @test_strcmp(i8* %src0, i8* %src1) #0 { define amdgpu_kernel void @test_strcmp(i8 addrspace(5)* %src0, i8 addrspace(5)* %src1) #0 {
%res = call i32 @strcmp(i8* %src0, i8* %src1) %res = call i32 @strcmp(i8 addrspace(5)* %src0, i8 addrspace(5)* %src1)
store volatile i32 %res, i32 addrspace(1)* undef store volatile i32 %res, i32 addrspace(1)* undef
ret void ret void
} }
; ERROR: error: <unknown>:0:0: in function test_strlen void (i8*): unsupported call to function strlen ; ERROR: error: <unknown>:0:0: in function test_strlen void (i8 addrspace(5)*): unsupported call to function strlen
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strlen@rel32@hi+4
define amdgpu_kernel void @test_strlen(i8* %src) #0 { define amdgpu_kernel void @test_strlen(i8 addrspace(5)* %src) #0 {
%res = call i32 @strlen(i8* %src) %res = call i32 @strlen(i8 addrspace(5)* %src)
store volatile i32 %res, i32 addrspace(1)* undef store volatile i32 %res, i32 addrspace(1)* undef
ret void ret void
} }
; ERROR: error: <unknown>:0:0: in function test_strnlen void (i8*, i32): unsupported call to function strnlen ; ERROR: error: <unknown>:0:0: in function test_strnlen void (i8 addrspace(5)*, i32): unsupported call to function strnlen
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strnlen@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, strnlen@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strnlen@rel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, strnlen@rel32@hi+4
define amdgpu_kernel void @test_strnlen(i8* %src, i32 %size) #0 { define amdgpu_kernel void @test_strnlen(i8 addrspace(5)* %src, i32 %size) #0 {
%res = call i32 @strnlen(i8* %src, i32 %size) %res = call i32 @strnlen(i8 addrspace(5)* %src, i32 %size)
store volatile i32 %res, i32 addrspace(1)* undef store volatile i32 %res, i32 addrspace(1)* undef
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/memory-legalizer-atomic-cmpxchg.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}system_monotonic_monotonic ; CHECK-LABEL: {{^}}system_monotonic_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_monotonic_monotonic( define amdgpu_kernel void @system_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in monotonic monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acquire_monotonic( define amdgpu_kernel void @system_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acquire monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_release_monotonic( define amdgpu_kernel void @system_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in release monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acq_rel_monotonic( define amdgpu_kernel void @system_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acq_rel monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst_monotonic( define amdgpu_kernel void @system_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acquire_acquire( define amdgpu_kernel void @system_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acquire acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_release_acquire( define amdgpu_kernel void @system_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in release acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acq_rel_acquire( define amdgpu_kernel void @system_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acq_rel acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst_acquire( define amdgpu_kernel void @system_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst_seq_cst( define amdgpu_kernel void @system_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_monotonic_monotonic( define amdgpu_kernel void @singlethread_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") monotonic monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acquire_monotonic( define amdgpu_kernel void @singlethread_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acquire monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_release_monotonic( define amdgpu_kernel void @singlethread_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") release monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acq_rel_monotonic( define amdgpu_kernel void @singlethread_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst_monotonic( define amdgpu_kernel void @singlethread_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acquire_acquire( define amdgpu_kernel void @singlethread_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acquire acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_release_acquire( define amdgpu_kernel void @singlethread_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") release acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acq_rel_acquire( define amdgpu_kernel void @singlethread_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst_acquire( define amdgpu_kernel void @singlethread_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst_seq_cst( define amdgpu_kernel void @singlethread_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_monotonic_monotonic( define amdgpu_kernel void @agent_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") monotonic monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acquire_monotonic( define amdgpu_kernel void @agent_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acquire monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_release_monotonic( define amdgpu_kernel void @agent_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") release monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acq_rel_monotonic( define amdgpu_kernel void @agent_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acq_rel monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst_monotonic( define amdgpu_kernel void @agent_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") seq_cst monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acquire_acquire( define amdgpu_kernel void @agent_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acquire acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_release_acquire( define amdgpu_kernel void @agent_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") release acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acq_rel_acquire( define amdgpu_kernel void @agent_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acq_rel acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst_acquire( define amdgpu_kernel void @agent_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") seq_cst acquire
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst_seq_cst( define amdgpu_kernel void @agent_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_monotonic_monotonic( define amdgpu_kernel void @workgroup_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") monotonic monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acquire_monotonic( define amdgpu_kernel void @workgroup_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acquire monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_release_monotonic( define amdgpu_kernel void @workgroup_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") release monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acq_rel_monotonic( define amdgpu_kernel void @workgroup_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst_monotonic( define amdgpu_kernel void @workgroup_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acquire_acquire( define amdgpu_kernel void @workgroup_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acquire acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_release_acquire( define amdgpu_kernel void @workgroup_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") release acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acq_rel_acquire( define amdgpu_kernel void @workgroup_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst_acquire( define amdgpu_kernel void @workgroup_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst_seq_cst( define amdgpu_kernel void @workgroup_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_monotonic_monotonic( define amdgpu_kernel void @wavefront_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") monotonic monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acquire_monotonic( define amdgpu_kernel void @wavefront_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acquire monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_release_monotonic( define amdgpu_kernel void @wavefront_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") release monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acq_rel_monotonic( define amdgpu_kernel void @wavefront_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst_monotonic( define amdgpu_kernel void @wavefront_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acquire_acquire( define amdgpu_kernel void @wavefront_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acquire acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_release_acquire( define amdgpu_kernel void @wavefront_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") release acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acq_rel_acquire( define amdgpu_kernel void @wavefront_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst_acquire( define amdgpu_kernel void @wavefront_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst_seq_cst( define amdgpu_kernel void @wavefront_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst seq_cst
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/memory-legalizer-atomic-fence.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX6 %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX6 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX8 %s
; FUNC-LABEL: {{^}}system_acquire ; FUNC-LABEL: {{^}}system_acquire
; GCN: BB#0 ; GCN: BB#0

test/CodeGen/AMDGPU/memory-legalizer-atomic-rmw.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}system_monotonic ; CHECK-LABEL: {{^}}system_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_monotonic( define amdgpu_kernel void @system_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acquire( define amdgpu_kernel void @system_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in acquire %val = atomicrmw volatile xchg i32* %out, i32 %in acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_release( define amdgpu_kernel void @system_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in release %val = atomicrmw volatile xchg i32* %out, i32 %in release
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acq_rel( define amdgpu_kernel void @system_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in acq_rel
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst( define amdgpu_kernel void @system_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_monotonic( define amdgpu_kernel void @singlethread_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acquire( define amdgpu_kernel void @singlethread_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_release( define amdgpu_kernel void @singlethread_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") release
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acq_rel( define amdgpu_kernel void @singlethread_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") acq_rel
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst( define amdgpu_kernel void @singlethread_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_monotonic( define amdgpu_kernel void @agent_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") monotonic
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acquire( define amdgpu_kernel void @agent_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_release( define amdgpu_kernel void @agent_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") release
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acq_rel( define amdgpu_kernel void @agent_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") acq_rel
ret void ret void
} }
Context not available.
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst( define amdgpu_kernel void @agent_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_monotonic( define amdgpu_kernel void @workgroup_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acquire( define amdgpu_kernel void @workgroup_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_release( define amdgpu_kernel void @workgroup_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") release
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acq_rel( define amdgpu_kernel void @workgroup_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") acq_rel
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst( define amdgpu_kernel void @workgroup_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") seq_cst
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_monotonic( define amdgpu_kernel void @wavefront_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") monotonic
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acquire( define amdgpu_kernel void @wavefront_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") acquire
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_release( define amdgpu_kernel void @wavefront_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") release
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acq_rel( define amdgpu_kernel void @wavefront_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") acq_rel
ret void ret void
} }
Context not available.
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst( define amdgpu_kernel void @wavefront_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") seq_cst
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll

; RUN: not llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: error: <unknown>:0:0: in function invalid_fence void (): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_fence void (): Unsupported synchronization scope
define amdgpu_kernel void @invalid_fence() { define amdgpu_kernel void @invalid_fence() {
Context not available.
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_load void (i32 addrspace(4)*, i32 addrspace(4)*): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_load void (i32*, i32*): Unsupported synchronization scope
define amdgpu_kernel void @invalid_load( define amdgpu_kernel void @invalid_load(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("invalid") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("invalid") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_store void (i32, i32 addrspace(4)*): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_store void (i32, i32*): Unsupported synchronization scope
define amdgpu_kernel void @invalid_store( define amdgpu_kernel void @invalid_store(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("invalid") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("invalid") seq_cst, align 4
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_cmpxchg void (i32 addrspace(4)*, i32, i32): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_cmpxchg void (i32*, i32, i32): Unsupported synchronization scope
define amdgpu_kernel void @invalid_cmpxchg( define amdgpu_kernel void @invalid_cmpxchg(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("invalid") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("invalid") seq_cst seq_cst
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_rmw void (i32 addrspace(4)*, i32): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_rmw void (i32*, i32): Unsupported synchronization scope
define amdgpu_kernel void @invalid_rmw( define amdgpu_kernel void @invalid_rmw(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("invalid") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("invalid") seq_cst
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/memory-legalizer-load.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_unordered( define amdgpu_kernel void @system_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in unordered, align 4 %val = load atomic i32, i32* %in unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_monotonic( define amdgpu_kernel void @system_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in monotonic, align 4 %val = load atomic i32, i32* %in monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_acquire( define amdgpu_kernel void @system_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in acquire, align 4 %val = load atomic i32, i32* %in acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_seq_cst( define amdgpu_kernel void @system_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in seq_cst, align 4 %val = load atomic i32, i32* %in seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_unordered( define amdgpu_kernel void @singlethread_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") unordered, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_monotonic( define amdgpu_kernel void @singlethread_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_acquire( define amdgpu_kernel void @singlethread_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") acquire, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_seq_cst( define amdgpu_kernel void @singlethread_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_unordered( define amdgpu_kernel void @agent_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") unordered, align 4 %val = load atomic i32, i32* %in syncscope("agent") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_monotonic( define amdgpu_kernel void @agent_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("agent") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_acquire( define amdgpu_kernel void @agent_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") acquire, align 4 %val = load atomic i32, i32* %in syncscope("agent") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_seq_cst( define amdgpu_kernel void @agent_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("agent") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_unordered( define amdgpu_kernel void @workgroup_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") unordered, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_monotonic( define amdgpu_kernel void @workgroup_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_acquire( define amdgpu_kernel void @workgroup_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") acquire, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_seq_cst( define amdgpu_kernel void @workgroup_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_unordered( define amdgpu_kernel void @wavefront_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") unordered, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_monotonic( define amdgpu_kernel void @wavefront_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_acquire( define amdgpu_kernel void @wavefront_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") acquire, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_seq_cst( define amdgpu_kernel void @wavefront_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_0 ; GCN-LABEL: {{^}}nontemporal_private_0
; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_0( define amdgpu_kernel void @nontemporal_private_0(
i32* %in, i32 addrspace(4)* %out) { i32 addrspace(5)* %in, i32* %out) {
entry: entry:
%val = load i32, i32* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_1 ; GCN-LABEL: {{^}}nontemporal_private_1
; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_1( define amdgpu_kernel void @nontemporal_private_1(
i32* %in, i32 addrspace(4)* %out) { i32 addrspace(5)* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
%val = load i32, i32* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_0 ; GCN-LABEL: {{^}}nontemporal_global_0
; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}}
define amdgpu_kernel void @nontemporal_global_0( define amdgpu_kernel void @nontemporal_global_0(
i32 addrspace(1)* %in, i32 addrspace(4)* %out) { i32 addrspace(1)* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.
; GFX8: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GFX8: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
; GFX9: global_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], off glc slc{{$}} ; GFX9: global_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], off glc slc{{$}}
define amdgpu_kernel void @nontemporal_global_1( define amdgpu_kernel void @nontemporal_global_1(
i32 addrspace(1)* %in, i32 addrspace(4)* %out) { i32 addrspace(1)* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
%val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_0 ; GCN-LABEL: {{^}}nontemporal_local_0
; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_0( define amdgpu_kernel void @nontemporal_local_0(
i32 addrspace(3)* %in, i32 addrspace(4)* %out) { i32 addrspace(3)* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_1 ; GCN-LABEL: {{^}}nontemporal_local_1
; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_1( define amdgpu_kernel void @nontemporal_local_1(
i32 addrspace(3)* %in, i32 addrspace(4)* %out) { i32 addrspace(3)* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid
%val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_0 ; GCN-LABEL: {{^}}nontemporal_flat_0
; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_0( define amdgpu_kernel void @nontemporal_flat_0(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4, !nontemporal !0 %val = load i32, i32* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_1 ; GCN-LABEL: {{^}}nontemporal_flat_1
; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_1( define amdgpu_kernel void @nontemporal_flat_1(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32* %in, i32 %tid
%val = load i32, i32 addrspace(4)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/memory-legalizer-store.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd--amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_unordered( define amdgpu_kernel void @system_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out unordered, align 4 store atomic i32 %in, i32* %out unordered, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_monotonic( define amdgpu_kernel void @system_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out monotonic, align 4 store atomic i32 %in, i32* %out monotonic, align 4
ret void ret void
} }
Context not available.
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_release( define amdgpu_kernel void @system_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out release, align 4 store atomic i32 %in, i32* %out release, align 4
ret void ret void
} }
Context not available.
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_seq_cst( define amdgpu_kernel void @system_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4 store atomic i32 %in, i32* %out seq_cst, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_unordered( define amdgpu_kernel void @singlethread_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") unordered, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") unordered, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_monotonic( define amdgpu_kernel void @singlethread_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") monotonic, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_release( define amdgpu_kernel void @singlethread_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") release, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") release, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_seq_cst( define amdgpu_kernel void @singlethread_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") seq_cst, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_unordered( define amdgpu_kernel void @agent_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") unordered, align 4 store atomic i32 %in, i32* %out syncscope("agent") unordered, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_monotonic( define amdgpu_kernel void @agent_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("agent") monotonic, align 4
ret void ret void
} }
Context not available.
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_release( define amdgpu_kernel void @agent_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") release, align 4 store atomic i32 %in, i32* %out syncscope("agent") release, align 4
ret void ret void
} }
Context not available.
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_seq_cst( define amdgpu_kernel void @agent_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("agent") seq_cst, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_unordered( define amdgpu_kernel void @workgroup_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") unordered, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") unordered, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_monotonic( define amdgpu_kernel void @workgroup_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") monotonic, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_release( define amdgpu_kernel void @workgroup_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") release, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") release, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_seq_cst( define amdgpu_kernel void @workgroup_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") seq_cst, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_unordered( define amdgpu_kernel void @wavefront_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") unordered, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") unordered, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_monotonic( define amdgpu_kernel void @wavefront_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") monotonic, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_release( define amdgpu_kernel void @wavefront_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") release, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") release, align 4
ret void ret void
} }
Context not available.
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_seq_cst( define amdgpu_kernel void @wavefront_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_0 ; GCN-LABEL: {{^}}nontemporal_private_0
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_0( define amdgpu_kernel void @nontemporal_private_0(
i32 addrspace(4)* %in, i32* %out) { i32* %in, i32 addrspace(5)* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32* %out, !nontemporal !0 store i32 %val, i32 addrspace(5)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_1 ; GCN-LABEL: {{^}}nontemporal_private_1
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_1( define amdgpu_kernel void @nontemporal_private_1(
i32 addrspace(4)* %in, i32* %out) { i32* %in, i32 addrspace(5)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
store i32 %val, i32* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0
ret void ret void
} }
Context not available.
; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}} ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
define amdgpu_kernel void @nontemporal_global_0( define amdgpu_kernel void @nontemporal_global_0(
i32 addrspace(4)* %in, i32 addrspace(1)* %out) { i32* %in, i32 addrspace(1)* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32 addrspace(1)* %out, !nontemporal !0 store i32 %val, i32 addrspace(1)* %out, !nontemporal !0
ret void ret void
} }
Context not available.
; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}} ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
define amdgpu_kernel void @nontemporal_global_1( define amdgpu_kernel void @nontemporal_global_1(
i32 addrspace(4)* %in, i32 addrspace(1)* %out) { i32* %in, i32 addrspace(1)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0
ret void ret void
Context not available.
; GCN-LABEL: {{^}}nontemporal_local_0 ; GCN-LABEL: {{^}}nontemporal_local_0
; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_0( define amdgpu_kernel void @nontemporal_local_0(
i32 addrspace(4)* %in, i32 addrspace(3)* %out) { i32* %in, i32 addrspace(3)* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32 addrspace(3)* %out, !nontemporal !0 store i32 %val, i32 addrspace(3)* %out, !nontemporal !0
ret void ret void
} }
Context not available.
; GCN-LABEL: {{^}}nontemporal_local_1 ; GCN-LABEL: {{^}}nontemporal_local_1
; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_1( define amdgpu_kernel void @nontemporal_local_1(
i32 addrspace(4)* %in, i32 addrspace(3)* %out) { i32* %in, i32 addrspace(3)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0
ret void ret void
Context not available.
; GCN-LABEL: {{^}}nontemporal_flat_0 ; GCN-LABEL: {{^}}nontemporal_flat_0
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_0( define amdgpu_kernel void @nontemporal_flat_0(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32 addrspace(4)* %out, !nontemporal !0 store i32 %val, i32* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_1 ; GCN-LABEL: {{^}}nontemporal_flat_1
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_1( define amdgpu_kernel void @nontemporal_flat_1(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(4)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32* %out, i32 %tid
store i32 %val, i32 addrspace(4)* %out.gep, !nontemporal !0 store i32 %val, i32* %out.gep, !nontemporal !0
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/merge-store-crash.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; This is used to crash in LiveIntervalAnalysis via SILoadStoreOptimizer ; This is used to crash in LiveIntervalAnalysis via SILoadStoreOptimizer
; while fixing up the merge of two ds_write instructions. ; while fixing up the merge of two ds_write instructions.

test/CodeGen/AMDGPU/merge-store-usedef.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test1: ; CHECK-LABEL: {{^}}test1:
; CHECK: ds_write_b32 ; CHECK: ds_write_b32

test/CodeGen/AMDGPU/merge-stores.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
; This test is mostly to test DAG store merging, so disable the vectorizer. ; This test is mostly to test DAG store merging, so disable the vectorizer.
; Run with devices with different unaligned load restrictions. ; Run with devices with different unaligned load restrictions.

test/CodeGen/AMDGPU/min3.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}v_test_imin3_slt_i32: ; GCN-LABEL: {{^}}v_test_imin3_slt_i32:
; GCN: v_min3_i32 ; GCN: v_min3_i32

test/CodeGen/AMDGPU/missing-store.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
@ptr_load = addrspace(3) global i32 addrspace(2)* undef, align 8 @ptr_load = addrspace(3) global i32 addrspace(2)* undef, align 8

test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll

; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa-amdgiz -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
; Check that when mubuf addr64 instruction is handled in moveToVALU ; Check that when mubuf addr64 instruction is handled in moveToVALU
; from the pointer, dead register writes are not emitted. ; from the pointer, dead register writes are not emitted.

test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; XUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; FIXME: broken on VI because flat instructions need to be emitted ; FIXME: broken on VI because flat instructions need to be emitted
; instead of addr64 equivalent of the _OFFSET variants. ; instead of addr64 equivalent of the _OFFSET variants.

test/CodeGen/AMDGPU/move-to-valu-worklist.ll

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; In moveToVALU(), move to vector ALU is performed, all instrs in ; In moveToVALU(), move to vector ALU is performed, all instrs in
; the use chain will be visited. We do not want the same node to be ; the use chain will be visited. We do not want the same node to be
Context not available.
; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @in_worklist_once() #0 { define amdgpu_kernel void @in_worklist_once() #0 {
bb: bb:
%tmp = load i64, i64* undef %tmp = load i64, i64 addrspace(5)* undef
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
Context not available.

test/CodeGen/AMDGPU/movreld-bug.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}main: ; GCN-LABEL: {{^}}main:
; GCN: v_movreld_b32_e32 v0, ; GCN: v_movreld_b32_e32 v0,

test/CodeGen/AMDGPU/mubuf-offset-private.ll

; RUN: llc -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; Test addressing modes when the scratch base is not a frame index. ; Test addressing modes when the scratch base is not a frame index.
; GCN-LABEL: {{^}}store_private_offset_i8: ; GCN-LABEL: {{^}}store_private_offset_i8:
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_i8() #0 { define amdgpu_kernel void @store_private_offset_i8() #0 {
store volatile i8 5, i8* inttoptr (i32 8 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i16: ; GCN-LABEL: {{^}}store_private_offset_i16:
; GCN: buffer_store_short v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_short v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_i16() #0 { define amdgpu_kernel void @store_private_offset_i16() #0 {
store volatile i16 5, i16* inttoptr (i32 8 to i16*) store volatile i16 5, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i32: ; GCN-LABEL: {{^}}store_private_offset_i32:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_i32() #0 { define amdgpu_kernel void @store_private_offset_i32() #0 {
store volatile i32 5, i32* inttoptr (i32 8 to i32*) store volatile i32 5, i32 addrspace(5)* inttoptr (i32 8 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_v2i32: ; GCN-LABEL: {{^}}store_private_offset_v2i32:
; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_v2i32() #0 { define amdgpu_kernel void @store_private_offset_v2i32() #0 {
store volatile <2 x i32> <i32 5, i32 10>, <2 x i32>* inttoptr (i32 8 to <2 x i32>*) store volatile <2 x i32> <i32 5, i32 10>, <2 x i32> addrspace(5)* inttoptr (i32 8 to <2 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_v4i32: ; GCN-LABEL: {{^}}store_private_offset_v4i32:
; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_v4i32() #0 { define amdgpu_kernel void @store_private_offset_v4i32() #0 {
store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, <4 x i32>* inttoptr (i32 8 to <4 x i32>*) store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, <4 x i32> addrspace(5)* inttoptr (i32 8 to <4 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_i8: ; GCN-LABEL: {{^}}load_private_offset_i8:
; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_i8() #0 { define amdgpu_kernel void @load_private_offset_i8() #0 {
%load = load volatile i8, i8* inttoptr (i32 8 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}sextload_private_offset_i8: ; GCN-LABEL: {{^}}sextload_private_offset_i8:
; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @sextload_private_offset_i8(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @sextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
%load = load volatile i8, i8* inttoptr (i32 8 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
%sextload = sext i8 %load to i32 %sextload = sext i8 %load to i32
store i32 %sextload, i32 addrspace(1)* undef store i32 %sextload, i32 addrspace(1)* undef
ret void ret void
Context not available.
; GCN-LABEL: {{^}}zextload_private_offset_i8: ; GCN-LABEL: {{^}}zextload_private_offset_i8:
; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @zextload_private_offset_i8(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @zextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
%load = load volatile i8, i8* inttoptr (i32 8 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
%zextload = zext i8 %load to i32 %zextload = zext i8 %load to i32
store i32 %zextload, i32 addrspace(1)* undef store i32 %zextload, i32 addrspace(1)* undef
ret void ret void
Context not available.
; GCN-LABEL: {{^}}load_private_offset_i16: ; GCN-LABEL: {{^}}load_private_offset_i16:
; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_i16() #0 { define amdgpu_kernel void @load_private_offset_i16() #0 {
%load = load volatile i16, i16* inttoptr (i32 8 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}sextload_private_offset_i16: ; GCN-LABEL: {{^}}sextload_private_offset_i16:
; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @sextload_private_offset_i16(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @sextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
%load = load volatile i16, i16* inttoptr (i32 8 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
%sextload = sext i16 %load to i32 %sextload = sext i16 %load to i32
store i32 %sextload, i32 addrspace(1)* undef store i32 %sextload, i32 addrspace(1)* undef
ret void ret void
Context not available.
; GCN-LABEL: {{^}}zextload_private_offset_i16: ; GCN-LABEL: {{^}}zextload_private_offset_i16:
; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @zextload_private_offset_i16(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @zextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
%load = load volatile i16, i16* inttoptr (i32 8 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
%zextload = zext i16 %load to i32 %zextload = zext i16 %load to i32
store i32 %zextload, i32 addrspace(1)* undef store i32 %zextload, i32 addrspace(1)* undef
ret void ret void
Context not available.
; GCN-LABEL: {{^}}load_private_offset_i32: ; GCN-LABEL: {{^}}load_private_offset_i32:
; GCN: buffer_load_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_i32() #0 { define amdgpu_kernel void @load_private_offset_i32() #0 {
%load = load volatile i32, i32* inttoptr (i32 8 to i32*) %load = load volatile i32, i32 addrspace(5)* inttoptr (i32 8 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_v2i32: ; GCN-LABEL: {{^}}load_private_offset_v2i32:
; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_v2i32() #0 { define amdgpu_kernel void @load_private_offset_v2i32() #0 {
%load = load volatile <2 x i32>, <2 x i32>* inttoptr (i32 8 to <2 x i32>*) %load = load volatile <2 x i32>, <2 x i32> addrspace(5)* inttoptr (i32 8 to <2 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_v4i32: ; GCN-LABEL: {{^}}load_private_offset_v4i32:
; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_v4i32() #0 { define amdgpu_kernel void @load_private_offset_v4i32() #0 {
%load = load volatile <4 x i32>, <4 x i32>* inttoptr (i32 8 to <4 x i32>*) %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* inttoptr (i32 8 to <4 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset: ; GCN-LABEL: {{^}}store_private_offset_i8_max_offset:
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:4095 ; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:4095
define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 { define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 {
store volatile i8 5, i8* inttoptr (i32 4095 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4095 to i8 addrspace(5)*)
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen{{$}} ; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen{{$}}
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 { define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 {
store volatile i8 5, i8* inttoptr (i32 4096 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4096 to i8 addrspace(5)*)
ret void ret void
} }
Context not available.
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen offset:1{{$}} ; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen offset:1{{$}}
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 { define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {
store volatile i8 5, i8* inttoptr (i32 4097 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4097 to i8 addrspace(5)*)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
; Test that buffer_load_format with VGPR resource descriptor is properly ; Test that buffer_load_format with VGPR resource descriptor is properly
; legalized. ; legalized.

test/CodeGen/AMDGPU/mubuf.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.amdgcn.workitem.id.x() readnone declare i32 @llvm.amdgcn.workitem.id.x() readnone

test/CodeGen/AMDGPU/mul.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
; mul24 and mad24 are affected ; mul24 and mad24 are affected

test/CodeGen/AMDGPU/mul_int24.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_smul24_i32: ; FUNC-LABEL: {{^}}test_smul24_i32:
; GCN-NOT: bfe ; GCN-NOT: bfe

test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone

test/CodeGen/AMDGPU/mul_uint24-r600.ll

; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_umul24_i32: ; FUNC-LABEL: {{^}}test_umul24_i32:
; EG: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W ; EG: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W

test/CodeGen/AMDGPU/multi-divergent-exit-region.ll

; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn---amdgiz -S -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Add an extra verifier runs. There were some cases where invalid IR ; Add an extra verifier runs. There were some cases where invalid IR
; was produced but happened to be fixed by the later passes. ; was produced but happened to be fixed by the later passes.

test/CodeGen/AMDGPU/multilevel-break.ll

; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; OPT-LABEL: {{^}}define amdgpu_vs void @multi_else_break( ; OPT-LABEL: {{^}}define amdgpu_vs void @multi_else_break(
; OPT: main_body: ; OPT: main_body:

test/CodeGen/AMDGPU/nested-calls.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=hawaii -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 -check-prefix=VI %s
target datalayout = "A5"
; Test calls when called by other callable functions rather than ; Test calls when called by other callable functions rather than
; kernels. ; kernels.
Context not available.
; GCN: s_sub_u32 s32, s32, 0x1200{{$}} ; GCN: s_sub_u32 s32, s32, 0x1200{{$}}
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @test_func_call_external_void_func_i32_imm_stack_use() #0 { define void @test_func_call_external_void_func_i32_imm_stack_use() #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
%gep15 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 16 %gep15 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 16
store volatile i32 0, i32* %gep0 store volatile i32 0, i32 addrspace(5)* %gep0
store volatile i32 0, i32* %gep15 store volatile i32 0, i32 addrspace(5)* %gep15
call void @external_void_func_i32(i32 42) call void @external_void_func_i32(i32 42)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/nested-loop-conditions.ll

; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn---amdgiz -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; After structurizing, there are 3 levels of loops. The i1 phi ; After structurizing, there are 3 levels of loops. The i1 phi
; conditions mutually depend on each other, so it isn't safe to delete ; conditions mutually depend on each other, so it isn't safe to delete

test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll

; RUN: not llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz < %s 2>&1 | FileCheck %s
; CHECK: in function pixel_s{{.*}}: unsupported non-compute shaders with HSA ; CHECK: in function pixel_s{{.*}}: unsupported non-compute shaders with HSA
define amdgpu_ps void @pixel_shader() #0 { define amdgpu_ps void @pixel_shader() #0 {

test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN
; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN
; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=EG ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=EG
; GCN: R_AMDGPU_REL32 extern_const_addrspace ; GCN: R_AMDGPU_REL32 extern_const_addrspace
; EG: R_AMDGPU_ABS32 extern_const_addrspace ; EG: R_AMDGPU_ABS32 extern_const_addrspace

test/CodeGen/AMDGPU/no-shrink-extloads.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/nop-data.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s
; CHECK: kernel0: ; CHECK: kernel0:
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm

test/CodeGen/AMDGPU/omod.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; IEEE bit enabled for compute kernel, no shouldn't use. ; IEEE bit enabled for compute kernel, no shouldn't use.
; GCN-LABEL: {{^}}v_omod_div2_f32_enable_ieee_signed_zeros: ; GCN-LABEL: {{^}}v_omod_div2_f32_enable_ieee_signed_zeros:

test/CodeGen/AMDGPU/opencl-image-metadata.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; Make sure the OpenCL Image lowering pass doesn't crash when argument metadata ; Make sure the OpenCL Image lowering pass doesn't crash when argument metadata
; is not in expected order. ; is not in expected order.
Context not available.
!0 = !{void (i32 addrspace(1)*)* @kernel, !1, !2, !3, !4, !5} !0 = !{void (i32 addrspace(1)*)* @kernel, !1, !2, !3, !4, !5}
!1 = !{!"kernel_arg_addr_space", i32 0} !1 = !{!"kernel_arg_addr_space", i32 0}
!2 = !{!"kernel_arg_access_qual", !"none"} !2 = !{!"kernel_arg_access_qual", !"none"}
!3 = !{!"kernel_arg_type", !"int*"} !3 = !{!"kernel_arg_type", !"int addrspace(5)*"}
!4 = !{!"kernel_arg_type_qual", !""} !4 = !{!"kernel_arg_type_qual", !""}
!5 = !{!"kernel_arg_name", !""} !5 = !{!"kernel_arg_name", !""}
Context not available.

test/CodeGen/AMDGPU/operand-folding.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}fold_sgpr: ; CHECK-LABEL: {{^}}fold_sgpr:
; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s ; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s

test/CodeGen/AMDGPU/operand-spacing.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
; Make sure there isn't an extra space between the instruction name and first operands. ; Make sure there isn't an extra space between the instruction name and first operands.

test/CodeGen/AMDGPU/or.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}or_v2i32: ; FUNC-LABEL: {{^}}or_v2i32:

test/CodeGen/AMDGPU/over-max-lds-size.ll

; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not llc -march=amdgcn -mcpu=hawaii < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not llc -march=amdgcn -mcpu=fiji < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: error: local memory limit exceeded (400000) in use_huge_lds ; ERROR: error: local memory limit exceeded (400000) in use_huge_lds

test/CodeGen/AMDGPU/pack.v2f16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; GCN-LABEL: {{^}}s_pack_v2f16: ; GCN-LABEL: {{^}}s_pack_v2f16:

test/CodeGen/AMDGPU/pack.v2i16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; GCN-LABEL: {{^}}s_pack_v2i16: ; GCN-LABEL: {{^}}s_pack_v2i16:

test/CodeGen/AMDGPU/packed-op-sel.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s
; GCN-LABEL: {{^}}fma_vector_vector_scalar_lo: ; GCN-LABEL: {{^}}fma_vector_vector_scalar_lo:
; GCN: ds_read_b32 [[VEC0:v[0-9]+]] ; GCN: ds_read_b32 [[VEC0:v[0-9]+]]

test/CodeGen/AMDGPU/packetizer.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s
; CHECK: {{^}}test: ; CHECK: {{^}}test:
; CHECK: BIT_ALIGN_INT T{{[0-9]}}.X ; CHECK: BIT_ALIGN_INT T{{[0-9]}}.X

test/CodeGen/AMDGPU/parallelandifcollapse.ll

; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck %s
target datalayout = "A5"
; ;
; CFG flattening should use parallel-and mode to generate branch conditions and ; CFG flattening should use parallel-and mode to generate branch conditions and
; then merge if-regions with the same bodies. ; then merge if-regions with the same bodies.
Context not available.
define amdgpu_kernel void @_Z9chk1D_512v() #0 { define amdgpu_kernel void @_Z9chk1D_512v() #0 {
entry: entry:
%a0 = alloca i32, align 4 %a0 = alloca i32, align 4, addrspace(5)
%b0 = alloca i32, align 4 %b0 = alloca i32, align 4, addrspace(5)
%c0 = alloca i32, align 4 %c0 = alloca i32, align 4, addrspace(5)
%d0 = alloca i32, align 4 %d0 = alloca i32, align 4, addrspace(5)
%a1 = alloca i32, align 4 %a1 = alloca i32, align 4, addrspace(5)
%b1 = alloca i32, align 4 %b1 = alloca i32, align 4, addrspace(5)
%c1 = alloca i32, align 4 %c1 = alloca i32, align 4, addrspace(5)
%d1 = alloca i32, align 4 %d1 = alloca i32, align 4, addrspace(5)
%data = alloca i32, align 4 %data = alloca i32, align 4, addrspace(5)
%0 = load i32, i32* %a0, align 4 %0 = load i32, i32 addrspace(5)* %a0, align 4
%1 = load i32, i32* %b0, align 4 %1 = load i32, i32 addrspace(5)* %b0, align 4
%cmp = icmp ne i32 %0, %1 %cmp = icmp ne i32 %0, %1
br i1 %cmp, label %land.lhs.true, label %if.end br i1 %cmp, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
%2 = load i32, i32* %c0, align 4 %2 = load i32, i32 addrspace(5)* %c0, align 4
%3 = load i32, i32* %d0, align 4 %3 = load i32, i32 addrspace(5)* %d0, align 4
%cmp1 = icmp ne i32 %2, %3 %cmp1 = icmp ne i32 %2, %3
br i1 %cmp1, label %if.then, label %if.end br i1 %cmp1, label %if.then, label %if.end
if.then: ; preds = %land.lhs.true if.then: ; preds = %land.lhs.true
store i32 1, i32* %data, align 4 store i32 1, i32 addrspace(5)* %data, align 4
br label %if.end br label %if.end
if.end: ; preds = %if.then, %land.lhs.true, %entry if.end: ; preds = %if.then, %land.lhs.true, %entry
%4 = load i32, i32* %a1, align 4 %4 = load i32, i32 addrspace(5)* %a1, align 4
%5 = load i32, i32* %b1, align 4 %5 = load i32, i32 addrspace(5)* %b1, align 4
%cmp2 = icmp ne i32 %4, %5 %cmp2 = icmp ne i32 %4, %5
br i1 %cmp2, label %land.lhs.true3, label %if.end6 br i1 %cmp2, label %land.lhs.true3, label %if.end6
land.lhs.true3: ; preds = %if.end land.lhs.true3: ; preds = %if.end
%6 = load i32, i32* %c1, align 4 %6 = load i32, i32 addrspace(5)* %c1, align 4
%7 = load i32, i32* %d1, align 4 %7 = load i32, i32 addrspace(5)* %d1, align 4
%cmp4 = icmp ne i32 %6, %7 %cmp4 = icmp ne i32 %6, %7
br i1 %cmp4, label %if.then5, label %if.end6 br i1 %cmp4, label %if.then5, label %if.end6
if.then5: ; preds = %land.lhs.true3 if.then5: ; preds = %land.lhs.true3
store i32 1, i32* %data, align 4 store i32 1, i32 addrspace(5)* %data, align 4
br label %if.end6 br label %if.end6
if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end
Context not available.

test/CodeGen/AMDGPU/parallelorifcollapse.ll

; Function Attrs: nounwind ; Function Attrs: nounwind
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
target datalayout = "A5"
; ;
; CFG flattening should use parallel-or to generate branch conditions and ; CFG flattening should use parallel-or to generate branch conditions and
; then merge if-regions with the same bodies. ; then merge if-regions with the same bodies.
Context not available.
; CHECK-NEXT: OR_INT ; CHECK-NEXT: OR_INT
define amdgpu_kernel void @_Z9chk1D_512v() #0 { define amdgpu_kernel void @_Z9chk1D_512v() #0 {
entry: entry:
%a0 = alloca i32, align 4 %a0 = alloca i32, align 4, addrspace(5)
%b0 = alloca i32, align 4 %b0 = alloca i32, align 4, addrspace(5)
%c0 = alloca i32, align 4 %c0 = alloca i32, align 4, addrspace(5)
%d0 = alloca i32, align 4 %d0 = alloca i32, align 4, addrspace(5)
%a1 = alloca i32, align 4 %a1 = alloca i32, align 4, addrspace(5)
%b1 = alloca i32, align 4 %b1 = alloca i32, align 4, addrspace(5)
%c1 = alloca i32, align 4 %c1 = alloca i32, align 4, addrspace(5)
%d1 = alloca i32, align 4 %d1 = alloca i32, align 4, addrspace(5)
%data = alloca i32, align 4 %data = alloca i32, align 4, addrspace(5)
%0 = load i32, i32* %a0, align 4 %0 = load i32, i32 addrspace(5)* %a0, align 4
%1 = load i32, i32* %b0, align 4 %1 = load i32, i32 addrspace(5)* %b0, align 4
%cmp = icmp ne i32 %0, %1 %cmp = icmp ne i32 %0, %1
br i1 %cmp, label %land.lhs.true, label %if.else br i1 %cmp, label %land.lhs.true, label %if.else
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
%2 = load i32, i32* %c0, align 4 %2 = load i32, i32 addrspace(5)* %c0, align 4
%3 = load i32, i32* %d0, align 4 %3 = load i32, i32 addrspace(5)* %d0, align 4
%cmp1 = icmp ne i32 %2, %3 %cmp1 = icmp ne i32 %2, %3
br i1 %cmp1, label %if.then, label %if.else br i1 %cmp1, label %if.then, label %if.else
Context not available.
br label %if.end br label %if.end
if.else: ; preds = %land.lhs.true, %entry if.else: ; preds = %land.lhs.true, %entry
store i32 1, i32* %data, align 4 store i32 1, i32 addrspace(5)* %data, align 4
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%4 = load i32, i32* %a1, align 4 %4 = load i32, i32 addrspace(5)* %a1, align 4
%5 = load i32, i32* %b1, align 4 %5 = load i32, i32 addrspace(5)* %b1, align 4
%cmp2 = icmp ne i32 %4, %5 %cmp2 = icmp ne i32 %4, %5
br i1 %cmp2, label %land.lhs.true3, label %if.else6 br i1 %cmp2, label %land.lhs.true3, label %if.else6
land.lhs.true3: ; preds = %if.end land.lhs.true3: ; preds = %if.end
%6 = load i32, i32* %c1, align 4 %6 = load i32, i32 addrspace(5)* %c1, align 4
%7 = load i32, i32* %d1, align 4 %7 = load i32, i32 addrspace(5)* %d1, align 4
%cmp4 = icmp ne i32 %6, %7 %cmp4 = icmp ne i32 %6, %7
br i1 %cmp4, label %if.then5, label %if.else6 br i1 %cmp4, label %if.then5, label %if.else6
Context not available.
br label %if.end7 br label %if.end7
if.else6: ; preds = %land.lhs.true3, %if.end if.else6: ; preds = %land.lhs.true3, %if.end
store i32 1, i32* %data, align 4 store i32 1, i32 addrspace(5)* %data, align 4
br label %if.end7 br label %if.end7
if.end7: ; preds = %if.else6, %if.then5 if.end7: ; preds = %if.else6, %if.then5
Context not available.

test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll

; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s
target datalayout = "A5"
; FIXME: we should disable sdwa peephole because dead-code elimination, that ; FIXME: we should disable sdwa peephole because dead-code elimination, that
; runs after peephole, ruins this test (different register numbers) ; runs after peephole, ruins this test (different register numbers)

test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -verify-coalescing < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -verify-coalescing < %s
; The original and requires materializing a 64-bit immediate for ; The original and requires materializing a 64-bit immediate for
; s_and_b64. This is split into 2 x v_and_i32, part of the immediate ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate

test/CodeGen/AMDGPU/predicate-dp4.ll

;RUN: llc < %s -march=r600 -mcpu=cayman ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: PRED_SETE_INT * Pred, ; CHECK: PRED_SETE_INT addrspace(5)* Pred,
; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one ; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one
define amdgpu_ps void @main(<4 x float> inreg) { define amdgpu_ps void @main(<4 x float> inreg) {
main_body: main_body:

test/CodeGen/AMDGPU/predicates.ll

; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s ; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -mtriple=r600---amdgiz -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s
; These tests make sure the compiler is optimizing branches using predicates ; These tests make sure the compiler is optimizing branches using predicates
; when it is legal to do so. ; when it is legal to do so.

test/CodeGen/AMDGPU/private-access-no-objects.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI -check-prefix=OPT %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=OPTNONE %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=OPTNONE %s
; There are no stack objects, but still a private memory access. The ; There are no stack objects, but still a private memory access. The
; private access regiters need to be correctly initialized anyway, and ; private access regiters need to be correctly initialized anyway, and
Context not available.
; OPTNONE-NOT: s_mov_b32 ; OPTNONE-NOT: s_mov_b32
; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s5 offen{{$}} ; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s5 offen{{$}}
define amdgpu_kernel void @store_to_undef() #0 { define amdgpu_kernel void @store_to_undef() #0 {
store volatile i32 0, i32* undef store volatile i32 0, i32 addrspace(5)* undef
ret void ret void
} }
Context not available.
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}} ; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}} ; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
define amdgpu_kernel void @store_to_inttoptr() #0 { define amdgpu_kernel void @store_to_inttoptr() #0 {
store volatile i32 0, i32* inttoptr (i32 124 to i32*) store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
Context not available.
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}} ; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
define amdgpu_kernel void @load_from_undef() #0 { define amdgpu_kernel void @load_from_undef() #0 {
%ld = load volatile i32, i32* undef %ld = load volatile i32, i32 addrspace(5)* undef
ret void ret void
} }
Context not available.
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}} ; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
define amdgpu_kernel void @load_from_inttoptr() #0 { define amdgpu_kernel void @load_from_inttoptr() #0 {
%ld = load volatile i32, i32* inttoptr (i32 124 to i32*) %ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/private-element-size.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT16 -check-prefix=HSA -check-prefix=HSA-ELT16 -check-prefix=ALL -check-prefix=HSA_ELTGE8 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT16 -check-prefix=HSA -check-prefix=HSA-ELT16 -check-prefix=ALL -check-prefix=HSA_ELTGE8 %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT8 -check-prefix=HSA -check-prefix=HSA-ELT8 -check-prefix=ALL -check-prefix=HSA-ELTGE8 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT8 -check-prefix=HSA -check-prefix=HSA-ELT8 -check-prefix=ALL -check-prefix=HSA-ELTGE8 %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT4 -check-prefix=HSA -check-prefix=HSA-ELT4 -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT4 -check-prefix=HSA -check-prefix=HSA-ELT4 -check-prefix=ALL %s
target datalayout = "A5"
; ALL-LABEL: {{^}}private_elt_size_v4i32: ; ALL-LABEL: {{^}}private_elt_size_v4i32:
Context not available.
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x <4 x i32>], align 16 %alloca = alloca [2 x <4 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>] addrspace(5)* %alloca, i32 0, i32 1
store <4 x i32> zeroinitializer, <4 x i32>* %gep0 store <4 x i32> zeroinitializer, <4 x i32> addrspace(5)* %gep0
store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %gep1 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>] addrspace(5)* %alloca, i32 0, i32 %index
%load = load <4 x i32>, <4 x i32>* %gep2 %load = load <4 x i32>, <4 x i32> addrspace(5)* %gep2
store <4 x i32> %load, <4 x i32> addrspace(1)* %out store <4 x i32> %load, <4 x i32> addrspace(1)* %out
ret void ret void
} }
Context not available.
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x <8 x i32>], align 16 %alloca = alloca [2 x <8 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>] addrspace(5)* %alloca, i32 0, i32 1
store <8 x i32> zeroinitializer, <8 x i32>* %gep0 store <8 x i32> zeroinitializer, <8 x i32> addrspace(5)* %gep0
store <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>, <8 x i32>* %gep1 store <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>, <8 x i32> addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>] addrspace(5)* %alloca, i32 0, i32 %index
%load = load <8 x i32>, <8 x i32>* %gep2 %load = load <8 x i32>, <8 x i32> addrspace(5)* %gep2
store <8 x i32> %load, <8 x i32> addrspace(1)* %out store <8 x i32> %load, <8 x i32> addrspace(1)* %out
ret void ret void
} }
Context not available.
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x i64], align 16 %alloca = alloca [2 x i64], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x i64], [2 x i64] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x i64], [2 x i64] addrspace(5)* %alloca, i32 0, i32 1
store i64 0, i64* %gep0 store i64 0, i64 addrspace(5)* %gep0
store i64 34359738602, i64* %gep1 store i64 34359738602, i64 addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x i64], [2 x i64] addrspace(5)* %alloca, i32 0, i32 %index
%load = load i64, i64* %gep2 %load = load i64, i64 addrspace(5)* %gep2
store i64 %load, i64 addrspace(1)* %out store i64 %load, i64 addrspace(1)* %out
ret void ret void
} }
Context not available.
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x double], align 16 %alloca = alloca [2 x double], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x double], [2 x double] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x double], [2 x double] addrspace(5)* %alloca, i32 0, i32 1
store double 0.0, double* %gep0 store double 0.0, double addrspace(5)* %gep0
store double 4.0, double* %gep1 store double 4.0, double addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x double], [2 x double] addrspace(5)* %alloca, i32 0, i32 %index
%load = load double, double* %gep2 %load = load double, double addrspace(5)* %gep2
store double %load, double addrspace(1)* %out store double %load, double addrspace(1)* %out
ret void ret void
} }
Context not available.
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x <2 x i64>], align 16 %alloca = alloca [2 x <2 x i64>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>] addrspace(5)* %alloca, i32 0, i32 1
store <2 x i64> zeroinitializer, <2 x i64>* %gep0 store <2 x i64> zeroinitializer, <2 x i64> addrspace(5)* %gep0
store <2 x i64> <i64 1, i64 2>, <2 x i64>* %gep1 store <2 x i64> <i64 1, i64 2>, <2 x i64> addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>] addrspace(5)* %alloca, i32 0, i32 %index
%load = load <2 x i64>, <2 x i64>* %gep2 %load = load <2 x i64>, <2 x i64> addrspace(5)* %gep2
store <2 x i64> %load, <2 x i64> addrspace(1)* %out store <2 x i64> %load, <2 x i64> addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/private-memory-atomics.ll

; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s
target datalayout = "A5"
; This works because promote allocas pass replaces these with LDS atomics. ; This works because promote allocas pass replaces these with LDS atomics.
; Private atomics have no real use, but at least shouldn't crash on it. ; Private atomics have no real use, but at least shouldn't crash on it.
define amdgpu_kernel void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind { define amdgpu_kernel void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%tmp4 = atomicrmw add i32* %tmp3, i32 7 acq_rel %tmp4 = atomicrmw add i32 addrspace(5)* %tmp3, i32 7 acq_rel
store i32 %tmp4, i32 addrspace(1)* %out store i32 %tmp4, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind { define amdgpu_kernel void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%tmp4 = cmpxchg i32* %tmp3, i32 0, i32 1 acq_rel monotonic %tmp4 = cmpxchg i32 addrspace(5)* %tmp3, i32 0, i32 1 acq_rel monotonic
%val = extractvalue { i32, i1 } %tmp4, 0 %val = extractvalue { i32, i1 } %tmp4, 0
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void

test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
; The types of the users of the addrspacecast should not be changed. ; The types of the users of the addrspacecast should not be changed.
; CHECK-LABEL: @invalid_bitcast_addrspace( ; CHECK-LABEL: @invalid_bitcast_addrspace(
; CHECK: getelementptr inbounds [256 x [1 x i32]], [256 x [1 x i32]] addrspace(3)* @invalid_bitcast_addrspace.data, i32 0, i32 %14 ; CHECK: getelementptr inbounds [256 x [1 x i32]], [256 x [1 x i32]] addrspace(3)* @invalid_bitcast_addrspace.data, i32 0, i32 %14
; CHECK: bitcast [1 x i32] addrspace(3)* %{{[0-9]+}} to half addrspace(3)* ; CHECK: bitcast [1 x i32] addrspace(3)* %{{[0-9]+}} to half addrspace(3)*
; CHECK: addrspacecast half addrspace(3)* %tmp to half addrspace(4)* ; CHECK: addrspacecast half addrspace(3)* %tmp to half*
; CHECK: bitcast half addrspace(4)* %tmp1 to <2 x i16> addrspace(4)* ; CHECK: bitcast half* %tmp1 to <2 x i16>*
define amdgpu_kernel void @invalid_bitcast_addrspace() #0 { define amdgpu_kernel void @invalid_bitcast_addrspace() #0 {
entry: entry:
%data = alloca [1 x i32], align 4 %data = alloca [1 x i32], align 4, addrspace(5)
%tmp = bitcast [1 x i32]* %data to half* %tmp = bitcast [1 x i32] addrspace(5)* %data to half addrspace(5)*
%tmp1 = addrspacecast half* %tmp to half addrspace(4)* %tmp1 = addrspacecast half addrspace(5)* %tmp to half*
%tmp2 = bitcast half addrspace(4)* %tmp1 to <2 x i16> addrspace(4)* %tmp2 = bitcast half* %tmp1 to <2 x i16>*
%tmp3 = load <2 x i16>, <2 x i16> addrspace(4)* %tmp2, align 2 %tmp3 = load <2 x i16>, <2 x i16>* %tmp2, align 2
%tmp4 = bitcast <2 x i16> %tmp3 to <2 x half> %tmp4 = bitcast <2 x i16> %tmp3 to <2 x half>
ret void ret void
} }

test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-promote-alloca < %s | FileCheck --check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa-amdgiz -amdgpu-promote-alloca < %s | FileCheck --check-prefix=OPT %s
target datalayout = "A5"
; Make sure that array alloca loaded and stored as multi-element aggregates are handled correctly ; Make sure that array alloca loaded and stored as multi-element aggregates are handled correctly
; Strictly the promote-alloca pass shouldn't have to deal with this case as it is non-canonical, but ; Strictly the promote-alloca pass shouldn't have to deal with this case as it is non-canonical, but
Context not available.
; should now leave these unchanged ; should now leave these unchanged
; OPT-LABEL: @promote_1d_aggr( ; OPT-LABEL: @promote_1d_aggr(
; OPT: store [1 x float] %tmp3, [1 x float]* %f1 ; OPT: store [1 x float] %tmp3, [1 x float] addrspace(5)* %f1
%Block = type { [1 x float], i32 } %Block = type { [1 x float], i32 }
%gl_PerVertex = type { <4 x float>, float, [1 x float], [1 x float] } %gl_PerVertex = type { <4 x float>, float, [1 x float], [1 x float] }
Context not available.
@pv = external addrspace(1) global %gl_PerVertex @pv = external addrspace(1) global %gl_PerVertex
define amdgpu_vs void @promote_1d_aggr() #0 { define amdgpu_vs void @promote_1d_aggr() #0 {
%i = alloca i32 %i = alloca i32, addrspace(5)
%f1 = alloca [1 x float] %f1 = alloca [1 x float], addrspace(5)
%tmp = getelementptr %Block, %Block addrspace(1)* @block, i32 0, i32 1 %tmp = getelementptr %Block, %Block addrspace(1)* @block, i32 0, i32 1
%tmp1 = load i32, i32 addrspace(1)* %tmp %tmp1 = load i32, i32 addrspace(1)* %tmp
store i32 %tmp1, i32* %i store i32 %tmp1, i32 addrspace(5)* %i
%tmp2 = getelementptr %Block, %Block addrspace(1)* @block, i32 0, i32 0 %tmp2 = getelementptr %Block, %Block addrspace(1)* @block, i32 0, i32 0
%tmp3 = load [1 x float], [1 x float] addrspace(1)* %tmp2 %tmp3 = load [1 x float], [1 x float] addrspace(1)* %tmp2
store [1 x float] %tmp3, [1 x float]* %f1 store [1 x float] %tmp3, [1 x float] addrspace(5)* %f1
%tmp4 = load i32, i32* %i %tmp4 = load i32, i32 addrspace(5)* %i
%tmp5 = getelementptr [1 x float], [1 x float]* %f1, i32 0, i32 %tmp4 %tmp5 = getelementptr [1 x float], [1 x float] addrspace(5)* %f1, i32 0, i32 %tmp4
%tmp6 = load float, float* %tmp5 %tmp6 = load float, float addrspace(5)* %tmp5
%tmp7 = alloca <4 x float> %tmp7 = alloca <4 x float>, addrspace(5)
%tmp8 = load <4 x float>, <4 x float>* %tmp7 %tmp8 = load <4 x float>, <4 x float> addrspace(5)* %tmp7
%tmp9 = insertelement <4 x float> %tmp8, float %tmp6, i32 0 %tmp9 = insertelement <4 x float> %tmp8, float %tmp6, i32 0
%tmp10 = insertelement <4 x float> %tmp9, float %tmp6, i32 1 %tmp10 = insertelement <4 x float> %tmp9, float %tmp6, i32 1
%tmp11 = insertelement <4 x float> %tmp10, float %tmp6, i32 2 %tmp11 = insertelement <4 x float> %tmp10, float %tmp6, i32 2
Context not available.
; OPT-LABEL: @promote_store_aggr( ; OPT-LABEL: @promote_store_aggr(
; OPT: %tmp6 = load [2 x float], [2 x float]* %f1 ; OPT: %tmp6 = load [2 x float], [2 x float] addrspace(5)* %f1
%Block2 = type { i32, [2 x float] } %Block2 = type { i32, [2 x float] }
@block2 = external addrspace(1) global %Block2 @block2 = external addrspace(1) global %Block2
define amdgpu_vs void @promote_store_aggr() #0 { define amdgpu_vs void @promote_store_aggr() #0 {
%i = alloca i32 %i = alloca i32, addrspace(5)
%f1 = alloca [2 x float] %f1 = alloca [2 x float], addrspace(5)
%tmp = getelementptr %Block2, %Block2 addrspace(1)* @block2, i32 0, i32 0 %tmp = getelementptr %Block2, %Block2 addrspace(1)* @block2, i32 0, i32 0
%tmp1 = load i32, i32 addrspace(1)* %tmp %tmp1 = load i32, i32 addrspace(1)* %tmp
store i32 %tmp1, i32* %i store i32 %tmp1, i32 addrspace(5)* %i
%tmp2 = load i32, i32* %i %tmp2 = load i32, i32 addrspace(5)* %i
%tmp3 = sitofp i32 %tmp2 to float %tmp3 = sitofp i32 %tmp2 to float
%tmp4 = getelementptr [2 x float], [2 x float]* %f1, i32 0, i32 0 %tmp4 = getelementptr [2 x float], [2 x float] addrspace(5)* %f1, i32 0, i32 0
store float %tmp3, float* %tmp4 store float %tmp3, float addrspace(5)* %tmp4
%tmp5 = getelementptr [2 x float], [2 x float]* %f1, i32 0, i32 1 %tmp5 = getelementptr [2 x float], [2 x float] addrspace(5)* %f1, i32 0, i32 1
store float 2.000000e+00, float* %tmp5 store float 2.000000e+00, float addrspace(5)* %tmp5
%tmp6 = load [2 x float], [2 x float]* %f1 %tmp6 = load [2 x float], [2 x float] addrspace(5)* %f1
%tmp7 = getelementptr %Block2, %Block2 addrspace(1)* @block2, i32 0, i32 1 %tmp7 = getelementptr %Block2, %Block2 addrspace(1)* @block2, i32 0, i32 1
store [2 x float] %tmp6, [2 x float] addrspace(1)* %tmp7 store [2 x float] %tmp6, [2 x float] addrspace(1)* %tmp7
%tmp8 = getelementptr %gl_PerVertex, %gl_PerVertex addrspace(1)* @pv, i32 0, i32 0 %tmp8 = getelementptr %gl_PerVertex, %gl_PerVertex addrspace(1)* @pv, i32 0, i32 0
Context not available.
} }
; OPT-LABEL: @promote_load_from_store_aggr( ; OPT-LABEL: @promote_load_from_store_aggr(
; OPT: store [2 x float] %tmp3, [2 x float]* %f1 ; OPT: store [2 x float] %tmp3, [2 x float] addrspace(5)* %f1
%Block3 = type { [2 x float], i32 } %Block3 = type { [2 x float], i32 }
@block3 = external addrspace(1) global %Block3 @block3 = external addrspace(1) global %Block3
define amdgpu_vs void @promote_load_from_store_aggr() #0 { define amdgpu_vs void @promote_load_from_store_aggr() #0 {
%i = alloca i32 %i = alloca i32, addrspace(5)
%f1 = alloca [2 x float] %f1 = alloca [2 x float], addrspace(5)
%tmp = getelementptr %Block3, %Block3 addrspace(1)* @block3, i32 0, i32 1 %tmp = getelementptr %Block3, %Block3 addrspace(1)* @block3, i32 0, i32 1
%tmp1 = load i32, i32 addrspace(1)* %tmp %tmp1 = load i32, i32 addrspace(1)* %tmp
store i32 %tmp1, i32* %i store i32 %tmp1, i32 addrspace(5)* %i
%tmp2 = getelementptr %Block3, %Block3 addrspace(1)* @block3, i32 0, i32 0 %tmp2 = getelementptr %Block3, %Block3 addrspace(1)* @block3, i32 0, i32 0
%tmp3 = load [2 x float], [2 x float] addrspace(1)* %tmp2 %tmp3 = load [2 x float], [2 x float] addrspace(1)* %tmp2
store [2 x float] %tmp3, [2 x float]* %f1 store [2 x float] %tmp3, [2 x float] addrspace(5)* %f1
%tmp4 = load i32, i32* %i %tmp4 = load i32, i32 addrspace(5)* %i
%tmp5 = getelementptr [2 x float], [2 x float]* %f1, i32 0, i32 %tmp4 %tmp5 = getelementptr [2 x float], [2 x float] addrspace(5)* %f1, i32 0, i32 %tmp4
%tmp6 = load float, float* %tmp5 %tmp6 = load float, float addrspace(5)* %tmp5
%tmp7 = alloca <4 x float> %tmp7 = alloca <4 x float>, addrspace(5)
%tmp8 = load <4 x float>, <4 x float>* %tmp7 %tmp8 = load <4 x float>, <4 x float> addrspace(5)* %tmp7
%tmp9 = insertelement <4 x float> %tmp8, float %tmp6, i32 0 %tmp9 = insertelement <4 x float> %tmp8, float %tmp6, i32 0
%tmp10 = insertelement <4 x float> %tmp9, float %tmp6, i32 1 %tmp10 = insertelement <4 x float> %tmp9, float %tmp6, i32 1
%tmp11 = insertelement <4 x float> %tmp10, float %tmp6, i32 2 %tmp11 = insertelement <4 x float> %tmp10, float %tmp6, i32 2
Context not available.
} }
; OPT-LABEL: @promote_double_aggr( ; OPT-LABEL: @promote_double_aggr(
; OPT: store [2 x double] %tmp5, [2 x double]* %s ; OPT: store [2 x double] %tmp5, [2 x double] addrspace(5)* %s
@tmp_g = external addrspace(1) global { [4 x double], <2 x double>, <3 x double>, <4 x double> } @tmp_g = external addrspace(1) global { [4 x double], <2 x double>, <3 x double>, <4 x double> }
@frag_color = external addrspace(1) global <4 x float> @frag_color = external addrspace(1) global <4 x float>
define amdgpu_ps void @promote_double_aggr() #0 { define amdgpu_ps void @promote_double_aggr() #0 {
%s = alloca [2 x double] %s = alloca [2 x double], addrspace(5)
%tmp = getelementptr { [4 x double], <2 x double>, <3 x double>, <4 x double> }, { [4 x double], <2 x double>, <3 x double>, <4 x double> } addrspace(1)* @tmp_g, i32 0, i32 0, i32 0 %tmp = getelementptr { [4 x double], <2 x double>, <3 x double>, <4 x double> }, { [4 x double], <2 x double>, <3 x double>, <4 x double> } addrspace(1)* @tmp_g, i32 0, i32 0, i32 0
%tmp1 = load double, double addrspace(1)* %tmp %tmp1 = load double, double addrspace(1)* %tmp
%tmp2 = getelementptr { [4 x double], <2 x double>, <3 x double>, <4 x double> }, { [4 x double], <2 x double>, <3 x double>, <4 x double> } addrspace(1)* @tmp_g, i32 0, i32 0, i32 1 %tmp2 = getelementptr { [4 x double], <2 x double>, <3 x double>, <4 x double> }, { [4 x double], <2 x double>, <3 x double>, <4 x double> } addrspace(1)* @tmp_g, i32 0, i32 0, i32 1
%tmp3 = load double, double addrspace(1)* %tmp2 %tmp3 = load double, double addrspace(1)* %tmp2
%tmp4 = insertvalue [2 x double] undef, double %tmp1, 0 %tmp4 = insertvalue [2 x double] undef, double %tmp1, 0
%tmp5 = insertvalue [2 x double] %tmp4, double %tmp3, 1 %tmp5 = insertvalue [2 x double] %tmp4, double %tmp3, 1
store [2 x double] %tmp5, [2 x double]* %s store [2 x double] %tmp5, [2 x double] addrspace(5)* %s
%tmp6 = getelementptr [2 x double], [2 x double]* %s, i32 0, i32 1 %tmp6 = getelementptr [2 x double], [2 x double] addrspace(5)* %s, i32 0, i32 1
%tmp7 = load double, double* %tmp6 %tmp7 = load double, double addrspace(5)* %tmp6
%tmp8 = getelementptr [2 x double], [2 x double]* %s, i32 0, i32 1 %tmp8 = getelementptr [2 x double], [2 x double] addrspace(5)* %s, i32 0, i32 1
%tmp9 = load double, double* %tmp8 %tmp9 = load double, double addrspace(5)* %tmp8
%tmp10 = fadd double %tmp7, %tmp9 %tmp10 = fadd double %tmp7, %tmp9
%tmp11 = getelementptr [2 x double], [2 x double]* %s, i32 0, i32 0 %tmp11 = getelementptr [2 x double], [2 x double] addrspace(5)* %s, i32 0, i32 0
store double %tmp10, double* %tmp11 store double %tmp10, double addrspace(5)* %tmp11
%tmp12 = getelementptr [2 x double], [2 x double]* %s, i32 0, i32 0 %tmp12 = getelementptr [2 x double], [2 x double] addrspace(5)* %s, i32 0, i32 0
%tmp13 = load double, double* %tmp12 %tmp13 = load double, double addrspace(5)* %tmp12
%tmp14 = getelementptr [2 x double], [2 x double]* %s, i32 0, i32 1 %tmp14 = getelementptr [2 x double], [2 x double] addrspace(5)* %s, i32 0, i32 1
%tmp15 = load double, double* %tmp14 %tmp15 = load double, double addrspace(5)* %tmp14
%tmp16 = fadd double %tmp13, %tmp15 %tmp16 = fadd double %tmp13, %tmp15
%tmp17 = fptrunc double %tmp16 to float %tmp17 = fptrunc double %tmp16 to float
%tmp18 = insertelement <4 x float> undef, float %tmp17, i32 0 %tmp18 = insertelement <4 x float> undef, float %tmp17, i32 0
Context not available.
; OPT-LABEL: @alloca_struct( ; OPT-LABEL: @alloca_struct(
define amdgpu_kernel void @alloca_struct() #0 { define amdgpu_kernel void @alloca_struct() #0 {
entry: entry:
%alloca = alloca [2 x %struct], align 4 %alloca = alloca [2 x %struct], align 4, addrspace(5)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa-amdgiz -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
; Make sure this allocates the correct size if the alloca has a non-0 ; Make sure this allocates the correct size if the alloca has a non-0
; number of elements. ; number of elements.
; CHECK-LABEL: @array_alloca( ; CHECK-LABEL: @array_alloca(
; CHECK: %stack = alloca i32, i32 5, align 4 ; CHECK: %stack = alloca i32, i32 5, align 4, addrspace(5)
define amdgpu_kernel void @array_alloca(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define amdgpu_kernel void @array_alloca(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca i32, i32 5, align 4 %stack = alloca i32, i32 5, align 4, addrspace(5)
%ld0 = load i32, i32 addrspace(1)* %in, align 4 %ld0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %stack, i32 %ld0 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 %ld0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds i32, i32* %stack, i32 %ld1 %arrayidx3 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 %ld1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds i32, i32* %stack, i32 0 %arrayidx10 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 0
%ld2 = load i32, i32* %arrayidx10, align 4 %ld2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %ld2, i32 addrspace(1)* %out, align 4 store i32 %ld2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds i32, i32* %stack, i32 1 %arrayidx12 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 1
%ld3 = load i32, i32* %arrayidx12 %ld3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %ld3, i32 addrspace(1)* %arrayidx13 store i32 %ld3, i32 addrspace(1)* %arrayidx13
ret void ret void
} }
; CHECK-LABEL: @array_alloca_dynamic( ; CHECK-LABEL: @array_alloca_dynamic(
; CHECK: %stack = alloca i32, i32 %size, align 4 ; CHECK: %stack = alloca i32, i32 %size, align 4, addrspace(5)
define amdgpu_kernel void @array_alloca_dynamic(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %size) #0 { define amdgpu_kernel void @array_alloca_dynamic(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %size) #0 {
entry: entry:
%stack = alloca i32, i32 %size, align 4 %stack = alloca i32, i32 %size, align 4, addrspace(5)
%ld0 = load i32, i32 addrspace(1)* %in, align 4 %ld0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %stack, i32 %ld0 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 %ld0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds i32, i32* %stack, i32 %ld1 %arrayidx3 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 %ld1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds i32, i32* %stack, i32 0 %arrayidx10 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 0
%ld2 = load i32, i32* %arrayidx10, align 4 %ld2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %ld2, i32 addrspace(1)* %out, align 4 store i32 %ld2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds i32, i32* %stack, i32 1 %arrayidx12 = getelementptr inbounds i32, i32 addrspace(5)* %stack, i32 1
%ld3 = load i32, i32* %arrayidx12 %ld3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %ld3, i32 addrspace(1)* %arrayidx13 store i32 %ld3, i32 addrspace(1)* %arrayidx13
ret void ret void

test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll

; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s 2>&1 | FileCheck %s
target datalayout = "A5"
; FIXME: Error is misleading because it's not an indirect call. ; FIXME: Error is misleading because it's not an indirect call.
Context not available.
; Make sure that AMDGPUPromoteAlloca doesn't crash if the called ; Make sure that AMDGPUPromoteAlloca doesn't crash if the called
; function is a constantexpr cast of a function. ; function is a constantexpr cast of a function.
declare void @foo(float*) #0 declare void @foo(float addrspace(5)*) #0
declare void @foo.varargs(...) #0 declare void @foo.varargs(...) #0
; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo ; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo
define amdgpu_kernel void @crash_call_constexpr_cast() #0 { define amdgpu_kernel void @crash_call_constexpr_cast() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
call void bitcast (void (float*)* @foo to void (i32*)*)(i32* %alloca) #0 call void bitcast (void (float addrspace(5)*)* @foo to void (i32 addrspace(5)*)*)(i32 addrspace(5)* %alloca) #0
ret void ret void
} }
; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo.varargs ; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo.varargs
define amdgpu_kernel void @crash_call_constexpr_cast_varargs() #0 { define amdgpu_kernel void @crash_call_constexpr_cast_varargs() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
call void bitcast (void (...)* @foo.varargs to void (i32*)*)(i32* %alloca) #0 call void bitcast (void (...)* @foo.varargs to void (i32 addrspace(5)*)*)(i32 addrspace(5)* %alloca) #0
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll

; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s ; RUN: opt -S -mtriple=amdgcn-unknown-unknown-amdgiz -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=ASM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji < %s | FileCheck -check-prefix=ASM %s
target datalayout = "A5"
; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 { ; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
; IR: alloca [5 x i32] ; IR: alloca [5 x i32]
Context not available.
; ASM: ; ScratchSize: 24 ; ASM: ; ScratchSize: 24
define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 { define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx4, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx4, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx5 %tmp3 = load i32, i32 addrspace(5)* %arrayidx5
%arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx6 store i32 %tmp3, i32 addrspace(1)* %arrayidx6
ret void ret void
Context not available.
; ASM: ; ScratchSize: 0 ; ASM: ; ScratchSize: 0
define void @promote_to_vector_call_c(i32 addrspace(1)* %out, i32 %in) #0 { define void @promote_to_vector_call_c(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%tmp4 = load i32, i32* %tmp3 %tmp4 = load i32, i32 addrspace(5)* %tmp3
%tmp5 = load volatile i32, i32 addrspace(1)* undef %tmp5 = load volatile i32, i32 addrspace(1)* undef
%tmp6 = add i32 %tmp4, %tmp5 %tmp6 = add i32 %tmp4, %tmp5
store i32 %tmp6, i32 addrspace(1)* %out store i32 %tmp6, i32 addrspace(1)* %out
Context not available.
; ASM: ; ScratchSize: 24 ; ASM: ; ScratchSize: 24
define void @no_promote_to_lds_c(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define void @no_promote_to_lds_c(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
} }
declare i32 @foo(i32*) #0 declare i32 @foo(i32 addrspace(5)*) #0
; ASM-LABEL: {{^}}call_private: ; ASM-LABEL: {{^}}call_private:
; ASM: buffer_store_dword ; ASM: buffer_store_dword
Context not available.
; ASM: ScratchSize: 16396 ; ASM: ScratchSize: 16396
define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%val = call i32 @foo(i32* %tmp3) %val = call i32 @foo(i32 addrspace(5)* %tmp3)
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-globals.ll

; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s ; RUN: opt -S -mtriple=amdgcn-unknown-unknown-amdgiz -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s
target datalayout = "A5"
@global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4 @global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4
Context not available.
define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
entry: entry:
%stack = alloca [10 x i32], align 4 %stack = alloca [10 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
%v0 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array0, i32 0, i32 0, i32 0 %v0 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array0, i32 0, i32 0, i32 0
Context not available.

test/CodeGen/AMDGPU/promote-alloca-lifetime.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -amdgpu-promote-alloca %s | FileCheck -check-prefix=OPT %s
target datalayout = "A5"
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0 declare void @llvm.lifetime.start.p0i8(i64, i8 addrspace(5)* nocapture) #0
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0 declare void @llvm.lifetime.end.p0i8(i64, i8 addrspace(5)* nocapture) #0
; OPT-LABEL: @use_lifetime_promotable_lds( ; OPT-LABEL: @use_lifetime_promotable_lds(
; OPT-NOT: alloca i32 ; OPT-NOT: alloca i32
Context not available.
; OPT: store i32 %tmp3, i32 addrspace(3)* ; OPT: store i32 %tmp3, i32 addrspace(3)*
define amdgpu_kernel void @use_lifetime_promotable_lds(i32 addrspace(1)* %arg) #2 { define amdgpu_kernel void @use_lifetime_promotable_lds(i32 addrspace(1)* %arg) #2 {
bb: bb:
%tmp = alloca i32, align 4 %tmp = alloca i32, align 4, addrspace(5)
%tmp1 = bitcast i32* %tmp to i8* %tmp1 = bitcast i32 addrspace(5)* %tmp to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 4, i8* %tmp1) call void @llvm.lifetime.start.p0i8(i64 4, i8 addrspace(5)* %tmp1)
%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
%tmp3 = load i32, i32 addrspace(1)* %tmp2 %tmp3 = load i32, i32 addrspace(1)* %tmp2
store i32 %tmp3, i32* %tmp store i32 %tmp3, i32 addrspace(5)* %tmp
call void @llvm.lifetime.end.p0i8(i64 4, i8* %tmp1) call void @llvm.lifetime.end.p0i8(i64 4, i8 addrspace(5)* %tmp1)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
declare void @llvm.memcpy.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0 declare void @llvm.memcpy.p0i8.p1i8.i32(i8 addrspace(5)* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0
declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0 declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(5)* nocapture, i32, i32, i1) #0
declare void @llvm.memmove.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0 declare void @llvm.memmove.p0i8.p1i8.i32(i8 addrspace(5)* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0
declare void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0 declare void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(5)* nocapture, i32, i32, i1) #0
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0 declare void @llvm.memset.p0i8.i32(i8 addrspace(5)* nocapture, i8, i32, i32, i1) #0
declare i32 @llvm.objectsize.i32.p0i8(i8*, i1, i1) #1 declare i32 @llvm.objectsize.i32.p0i8(i8 addrspace(5)*, i1, i1) #1
; CHECK-LABEL: @promote_with_memcpy( ; CHECK-LABEL: @promote_with_memcpy(
; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memcpy.alloca, i32 0, i32 %{{[0-9]+}} ; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memcpy.alloca, i32 0, i32 %{{[0-9]+}}
; CHECK: call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) ; CHECK: call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false)
; CHECK: call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(3)* %alloca.bc, i32 68, i32 4, i1 false) ; CHECK: call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(3)* %alloca.bc, i32 68, i32 4, i1 false)
define amdgpu_kernel void @promote_with_memcpy(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @promote_with_memcpy(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%alloca = alloca [17 x i32], align 4 %alloca = alloca [17 x i32], align 4, addrspace(5)
%alloca.bc = bitcast [17 x i32]* %alloca to i8* %alloca.bc = bitcast [17 x i32] addrspace(5)* %alloca to i8 addrspace(5)*
%in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)* %in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)*
%out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)* %out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)*
call void @llvm.memcpy.p0i8.p1i8.i32(i8* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) call void @llvm.memcpy.p0i8.p1i8.i32(i8 addrspace(5)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false)
call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %out.bc, i8* %alloca.bc, i32 68, i32 4, i1 false) call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(5)* %alloca.bc, i32 68, i32 4, i1 false)
ret void ret void
} }
Context not available.
; CHECK: call void @llvm.memmove.p3i8.p1i8.i32(i8 addrspace(3)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) ; CHECK: call void @llvm.memmove.p3i8.p1i8.i32(i8 addrspace(3)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false)
; CHECK: call void @llvm.memmove.p1i8.p3i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(3)* %alloca.bc, i32 68, i32 4, i1 false) ; CHECK: call void @llvm.memmove.p1i8.p3i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(3)* %alloca.bc, i32 68, i32 4, i1 false)
define amdgpu_kernel void @promote_with_memmove(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @promote_with_memmove(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%alloca = alloca [17 x i32], align 4 %alloca = alloca [17 x i32], align 4, addrspace(5)
%alloca.bc = bitcast [17 x i32]* %alloca to i8* %alloca.bc = bitcast [17 x i32] addrspace(5)* %alloca to i8 addrspace(5)*
%in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)* %in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)*
%out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)* %out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)*
call void @llvm.memmove.p0i8.p1i8.i32(i8* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) call void @llvm.memmove.p0i8.p1i8.i32(i8 addrspace(5)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false)
call void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* %out.bc, i8* %alloca.bc, i32 68, i32 4, i1 false) call void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(5)* %alloca.bc, i32 68, i32 4, i1 false)
ret void ret void
} }
Context not available.
; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memset.alloca, i32 0, i32 %{{[0-9]+}} ; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memset.alloca, i32 0, i32 %{{[0-9]+}}
; CHECK: call void @llvm.memset.p3i8.i32(i8 addrspace(3)* %alloca.bc, i8 7, i32 68, i32 4, i1 false) ; CHECK: call void @llvm.memset.p3i8.i32(i8 addrspace(3)* %alloca.bc, i8 7, i32 68, i32 4, i1 false)
define amdgpu_kernel void @promote_with_memset(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @promote_with_memset(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%alloca = alloca [17 x i32], align 4 %alloca = alloca [17 x i32], align 4, addrspace(5)
%alloca.bc = bitcast [17 x i32]* %alloca to i8* %alloca.bc = bitcast [17 x i32] addrspace(5)* %alloca to i8 addrspace(5)*
%in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)* %in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)*
%out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)* %out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)*
call void @llvm.memset.p0i8.i32(i8* %alloca.bc, i8 7, i32 68, i32 4, i1 false) call void @llvm.memset.p0i8.i32(i8 addrspace(5)* %alloca.bc, i8 7, i32 68, i32 4, i1 false)
ret void ret void
} }
Context not available.
; CHECK: [[PTR:%[0-9]+]] = getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_objectsize.alloca, i32 0, i32 %{{[0-9]+}} ; CHECK: [[PTR:%[0-9]+]] = getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_objectsize.alloca, i32 0, i32 %{{[0-9]+}}
; CHECK: call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* %alloca.bc, i1 false, i1 false) ; CHECK: call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* %alloca.bc, i1 false, i1 false)
define amdgpu_kernel void @promote_with_objectsize(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @promote_with_objectsize(i32 addrspace(1)* %out) #0 {
%alloca = alloca [17 x i32], align 4 %alloca = alloca [17 x i32], align 4, addrspace(5)
%alloca.bc = bitcast [17 x i32]* %alloca to i8* %alloca.bc = bitcast [17 x i32] addrspace(5)* %alloca to i8 addrspace(5)*
%size = call i32 @llvm.objectsize.i32.p0i8(i8* %alloca.bc, i1 false, i1 false) %size = call i32 @llvm.objectsize.i32.p0i8(i8 addrspace(5)* %alloca.bc, i1 false, i1 false)
store i32 %size, i32 addrspace(1)* %out store i32 %size, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-no-opts.ll

; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s ; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
target datalayout = "A5"
; ALL-LABEL: {{^}}promote_alloca_i32_array_array: ; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
; NOOPTS: workgroup_group_segment_byte_size = 0{{$}} ; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
Context not available.
; OPTS: ds_write ; OPTS: ds_write
define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x i32]] %alloca = alloca [2 x [2 x i32]], addrspace(5)
%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.
; ALL-NOT ds_write ; ALL-NOT ds_write
define amdgpu_kernel void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 { define amdgpu_kernel void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 {
entry: entry:
%alloca = alloca [2 x [2 x i32]] %alloca = alloca [2 x [2 x i32]], addrspace(5)
%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=kaveri < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
; This shows that the amount of LDS estimate is sensitive to the order ; This shows that the amount of LDS estimate is sensitive to the order
; of the LDS globals. ; of the LDS globals.
Context not available.
; GCN: workgroup_group_segment_byte_size = 2340 ; GCN: workgroup_group_segment_byte_size = 2340
define amdgpu_kernel void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { define amdgpu_kernel void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
Context not available.
; GCN: workgroup_group_segment_byte_size = 2352 ; GCN: workgroup_group_segment_byte_size = 2352
define amdgpu_kernel void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { define amdgpu_kernel void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
Context not available.
; GCN: workgroup_group_segment_byte_size = 1060 ; GCN: workgroup_group_segment_byte_size = 1060
define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
Context not available.

test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll

; RUN: llc -march=amdgcn -mattr=+promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
; Pointer value is stored in a candidate for LDS usage. ; Pointer value is stored in a candidate for LDS usage.
; GCN-LABEL: {{^}}stored_lds_pointer_value: ; GCN-LABEL: {{^}}stored_lds_pointer_value:
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
define amdgpu_kernel void @stored_lds_pointer_value(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_lds_pointer_value(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp = alloca float %tmp = alloca float, addrspace(5)
store float 0.0, float *%tmp store float 0.0, float addrspace(5)*%tmp
store float* %tmp, float* addrspace(1)* %ptr store float addrspace(5)* %tmp, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}stored_lds_pointer_value_offset: ; GCN-LABEL: {{^}}stored_lds_pointer_value_offset:
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
define amdgpu_kernel void @stored_lds_pointer_value_offset(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_lds_pointer_value_offset(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp0 = alloca float %tmp0 = alloca float, addrspace(5)
%tmp1 = alloca float %tmp1 = alloca float, addrspace(5)
store float 0.0, float *%tmp0 store float 0.0, float addrspace(5)*%tmp0
store float 0.0, float *%tmp1 store float 0.0, float addrspace(5)*%tmp1
store volatile float* %tmp0, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp0, float addrspace(5)* addrspace(1)* %ptr
store volatile float* %tmp1, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
Context not available.
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
define amdgpu_kernel void @stored_lds_pointer_value_gep(float* addrspace(1)* %ptr, i32 %idx) #0 { define amdgpu_kernel void @stored_lds_pointer_value_gep(float addrspace(5)* addrspace(1)* %ptr, i32 %idx) #0 {
bb: bb:
%tmp = alloca float, i32 16 %tmp = alloca float, i32 16, addrspace(5)
store float 0.0, float* %tmp store float 0.0, float addrspace(5)* %tmp
%tmp2 = getelementptr inbounds float, float* %tmp, i32 %idx %tmp2 = getelementptr inbounds float, float addrspace(5)* %tmp, i32 %idx
store float* %tmp2, float* addrspace(1)* %ptr store float addrspace(5)* %tmp2, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
Context not available.
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @stored_vector_pointer_value(i32* addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @stored_vector_pointer_value(i32 addrspace(5)* addrspace(1)* %out, i32 %index) {
entry: entry:
%tmp0 = alloca [4 x i32] %tmp0 = alloca [4 x i32], addrspace(5)
%x = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 0 %x = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 0
%y = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 1 %y = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 1
%z = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 2 %z = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 2
%w = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 3 %w = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 3
store i32 0, i32* %x store i32 0, i32 addrspace(5)* %x
store i32 1, i32* %y store i32 1, i32 addrspace(5)* %y
store i32 2, i32* %z store i32 2, i32 addrspace(5)* %z
store i32 3, i32* %w store i32 3, i32 addrspace(5)* %w
%tmp1 = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 %index %tmp1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 %index
store i32* %tmp1, i32* addrspace(1)* %out store i32 addrspace(5)* %tmp1, i32 addrspace(5)* addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_self: ; GCN-LABEL: {{^}}stored_fi_to_self:
; GCN-NOT: ds_ ; GCN-NOT: ds_
define amdgpu_kernel void @stored_fi_to_self() #0 { define amdgpu_kernel void @stored_fi_to_self() #0 {
%tmp = alloca i32* %tmp = alloca i32 addrspace(5)*, addrspace(5)
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp
%bitcast = bitcast i32** %tmp to i32* %bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp to i32 addrspace(5)*
store volatile i32* %bitcast, i32** %tmp store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
; This normally would be fixed by instcombine to be compare to the GEP ; This normally would be fixed by instcombine to be compare to the GEP
; indices ; indices
Context not available.
; CHECK: %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %b ; CHECK: %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %b
; CHECK: %cmp = icmp eq i32 addrspace(3)* %ptr0, %ptr1 ; CHECK: %cmp = icmp eq i32 addrspace(3)* %ptr0, %ptr1
define amdgpu_kernel void @lds_promoted_alloca_icmp_same_derived_pointer(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @lds_promoted_alloca_icmp_same_derived_pointer(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
%ptr1 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %b %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %b
%cmp = icmp eq i32* %ptr0, %ptr1 %cmp = icmp eq i32 addrspace(5)* %ptr0, %ptr1
%zext = zext i1 %cmp to i32 %zext = zext i1 %cmp to i32
store volatile i32 %zext, i32 addrspace(1)* %out store volatile i32 %zext, i32 addrspace(1)* %out
ret void ret void
Context not available.
; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a ; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a
; CHECK: %cmp = icmp eq i32 addrspace(3)* %ptr0, null ; CHECK: %cmp = icmp eq i32 addrspace(3)* %ptr0, null
define amdgpu_kernel void @lds_promoted_alloca_icmp_null_rhs(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @lds_promoted_alloca_icmp_null_rhs(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
%cmp = icmp eq i32* %ptr0, null %cmp = icmp eq i32 addrspace(5)* %ptr0, null
%zext = zext i1 %cmp to i32 %zext = zext i1 %cmp to i32
store volatile i32 %zext, i32 addrspace(1)* %out store volatile i32 %zext, i32 addrspace(1)* %out
ret void ret void
Context not available.
; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a ; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a
; CHECK: %cmp = icmp eq i32 addrspace(3)* null, %ptr0 ; CHECK: %cmp = icmp eq i32 addrspace(3)* null, %ptr0
define amdgpu_kernel void @lds_promoted_alloca_icmp_null_lhs(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @lds_promoted_alloca_icmp_null_lhs(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
%cmp = icmp eq i32* null, %ptr0 %cmp = icmp eq i32 addrspace(5)* null, %ptr0
%zext = zext i1 %cmp to i32 %zext = zext i1 %cmp to i32
store volatile i32 %zext, i32 addrspace(1)* %out store volatile i32 %zext, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: @lds_promoted_alloca_icmp_unknown_ptr( ; CHECK-LABEL: @lds_promoted_alloca_icmp_unknown_ptr(
; CHECK: %alloca = alloca [16 x i32], align 4 ; CHECK: %alloca = alloca [16 x i32], align 4, addrspace(5)
; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a ; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
; CHECK: %ptr1 = call i32* @get_unknown_pointer() ; CHECK: %ptr1 = call i32 addrspace(5)* @get_unknown_pointer()
; CHECK: %cmp = icmp eq i32* %ptr0, %ptr1 ; CHECK: %cmp = icmp eq i32 addrspace(5)* %ptr0, %ptr1
define amdgpu_kernel void @lds_promoted_alloca_icmp_unknown_ptr(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @lds_promoted_alloca_icmp_unknown_ptr(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
%ptr1 = call i32* @get_unknown_pointer() %ptr1 = call i32 addrspace(5)* @get_unknown_pointer()
%cmp = icmp eq i32* %ptr0, %ptr1 %cmp = icmp eq i32 addrspace(5)* %ptr0, %ptr1
%zext = zext i1 %cmp to i32 %zext = zext i1 %cmp to i32
store volatile i32 %zext, i32 addrspace(1)* %out store volatile i32 %zext, i32 addrspace(1)* %out
ret void ret void
} }
declare i32* @get_unknown_pointer() #0 declare i32 addrspace(5)* @get_unknown_pointer() #0
attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" } attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
; CHECK-LABEL: @branch_ptr_var_same_alloca( ; CHECK-LABEL: @branch_ptr_var_same_alloca(
Context not available.
; CHECK: store i32 0, i32 addrspace(3)* %phi.ptr, align 4 ; CHECK: store i32 0, i32 addrspace(3)* %phi.ptr, align 4
define amdgpu_kernel void @branch_ptr_var_same_alloca(i32 %a, i32 %b) #0 { define amdgpu_kernel void @branch_ptr_var_same_alloca(i32 %a, i32 %b) #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
br i1 undef, label %if, label %else br i1 undef, label %if, label %else
if: if:
%arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %a
br label %endif br label %endif
else: else:
%arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %b %arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %b
br label %endif br label %endif
endif: endif:
%phi.ptr = phi i32* [ %arrayidx0, %if ], [ %arrayidx1, %else ] %phi.ptr = phi i32 addrspace(5)* [ %arrayidx0, %if ], [ %arrayidx1, %else ]
store i32 0, i32* %phi.ptr, align 4 store i32 0, i32 addrspace(5)* %phi.ptr, align 4
ret void ret void
} }
Context not available.
; CHECK: %phi.ptr = phi i32 addrspace(3)* [ %arrayidx0, %if ], [ null, %entry ] ; CHECK: %phi.ptr = phi i32 addrspace(3)* [ %arrayidx0, %if ], [ null, %entry ]
define amdgpu_kernel void @branch_ptr_phi_alloca_null_0(i32 %a, i32 %b) #0 { define amdgpu_kernel void @branch_ptr_phi_alloca_null_0(i32 %a, i32 %b) #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
br i1 undef, label %if, label %endif br i1 undef, label %if, label %endif
if: if:
%arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %a
br label %endif br label %endif
endif: endif:
%phi.ptr = phi i32* [ %arrayidx0, %if ], [ null, %entry ] %phi.ptr = phi i32 addrspace(5)* [ %arrayidx0, %if ], [ null, %entry ]
store i32 0, i32* %phi.ptr, align 4 store i32 0, i32 addrspace(5)* %phi.ptr, align 4
ret void ret void
} }
Context not available.
; CHECK: %phi.ptr = phi i32 addrspace(3)* [ null, %entry ], [ %arrayidx0, %if ] ; CHECK: %phi.ptr = phi i32 addrspace(3)* [ null, %entry ], [ %arrayidx0, %if ]
define amdgpu_kernel void @branch_ptr_phi_alloca_null_1(i32 %a, i32 %b) #0 { define amdgpu_kernel void @branch_ptr_phi_alloca_null_1(i32 %a, i32 %b) #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
br i1 undef, label %if, label %endif br i1 undef, label %if, label %endif
if: if:
%arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %a
br label %endif br label %endif
endif: endif:
%phi.ptr = phi i32* [ null, %entry ], [ %arrayidx0, %if ] %phi.ptr = phi i32 addrspace(5)* [ null, %entry ], [ %arrayidx0, %if ]
store i32 0, i32* %phi.ptr, align 4 store i32 0, i32 addrspace(5)* %phi.ptr, align 4
ret void ret void
} }
Context not available.
; CHECK: store i32 0, i32 addrspace(3)* %phi.ptr, align 4 ; CHECK: store i32 0, i32 addrspace(3)* %phi.ptr, align 4
define amdgpu_kernel void @one_phi_value(i32 %a) #0 { define amdgpu_kernel void @one_phi_value(i32 %a) #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
%arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %a
br label %exit br label %exit
exit: exit:
%phi.ptr = phi i32* [ %arrayidx0, %entry ] %phi.ptr = phi i32 addrspace(5)* [ %arrayidx0, %entry ]
store i32 0, i32* %phi.ptr, align 4 store i32 0, i32 addrspace(5)* %phi.ptr, align 4
ret void ret void
} }
; CHECK-LABEL: @branch_ptr_alloca_unknown_obj( ; CHECK-LABEL: @branch_ptr_alloca_unknown_obj(
; CHECK: %alloca = alloca [64 x i32], align 4 ; CHECK: %alloca = alloca [64 x i32], align 4, addrspace(5)
; CHECK: if: ; CHECK: if:
; CHECK: %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a ; CHECK: %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %a
; CHECK: else: ; CHECK: else:
; CHECK: %arrayidx1 = call i32* @get_unknown_pointer() ; CHECK: %arrayidx1 = call i32 addrspace(5)* @get_unknown_pointer()
; CHECK: endif: ; CHECK: endif:
; CHECK: %phi.ptr = phi i32* [ %arrayidx0, %if ], [ %arrayidx1, %else ] ; CHECK: %phi.ptr = phi i32 addrspace(5)* [ %arrayidx0, %if ], [ %arrayidx1, %else ]
; CHECK: store i32 0, i32* %phi.ptr, align 4 ; CHECK: store i32 0, i32 addrspace(5)* %phi.ptr, align 4
define amdgpu_kernel void @branch_ptr_alloca_unknown_obj(i32 %a, i32 %b) #0 { define amdgpu_kernel void @branch_ptr_alloca_unknown_obj(i32 %a, i32 %b) #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
br i1 undef, label %if, label %else br i1 undef, label %if, label %else
if: if:
%arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 %a
br label %endif br label %endif
else: else:
%arrayidx1 = call i32* @get_unknown_pointer() %arrayidx1 = call i32 addrspace(5)* @get_unknown_pointer()
br label %endif br label %endif
endif: endif:
%phi.ptr = phi i32* [ %arrayidx0, %if ], [ %arrayidx1, %else ] %phi.ptr = phi i32 addrspace(5)* [ %arrayidx0, %if ], [ %arrayidx1, %else ]
store i32 0, i32* %phi.ptr, align 4 store i32 0, i32 addrspace(5)* %phi.ptr, align 4
ret void ret void
} }
Context not available.
; int i = 0; ; int i = 0;
; #pragma nounroll ; #pragma nounroll
; for (int* p = &alloca[2], *e = &alloca[48]; p != e; ++p, ++i) ; for (int addrspace(5)* p = &alloca[2], *e = &alloca[48]; p != e; ++p, ++i)
; { ; {
; *p = i; ; *p = i;
; } ; }
Context not available.
; GetUnderlyingObjects when looking at the icmp user. ; GetUnderlyingObjects when looking at the icmp user.
; CHECK-LABEL: @ptr_induction_var_same_alloca( ; CHECK-LABEL: @ptr_induction_var_same_alloca(
; CHECK: %alloca = alloca [64 x i32], align 4 ; CHECK: %alloca = alloca [64 x i32], align 4, addrspace(5)
; CHECK: phi i32* [ %arrayidx, %entry ], [ %incdec.ptr, %for.body ] ; CHECK: phi i32 addrspace(5)* [ %arrayidx, %entry ], [ %incdec.ptr, %for.body ]
define amdgpu_kernel void @ptr_induction_var_same_alloca() #0 { define amdgpu_kernel void @ptr_induction_var_same_alloca() #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
%arrayidx = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 2 %arrayidx = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 2
%arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 48 %arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 48
br label %for.body br label %for.body
for.cond.cleanup: ; preds = %for.body for.cond.cleanup: ; preds = %for.body
Context not available.
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%p.08 = phi i32* [ %arrayidx, %entry ], [ %incdec.ptr, %for.body ] %p.08 = phi i32 addrspace(5)* [ %arrayidx, %entry ], [ %incdec.ptr, %for.body ]
store i32 %i.09, i32* %p.08, align 4 store i32 %i.09, i32 addrspace(5)* %p.08, align 4
%incdec.ptr = getelementptr inbounds i32, i32* %p.08, i32 1 %incdec.ptr = getelementptr inbounds i32, i32 addrspace(5)* %p.08, i32 1
%inc = add nuw nsw i32 %i.09, 1 %inc = add nuw nsw i32 %i.09, 1
%cmp = icmp eq i32* %incdec.ptr, %arrayidx1 %cmp = icmp eq i32 addrspace(5)* %incdec.ptr, %arrayidx1
br i1 %cmp, label %for.cond.cleanup, label %for.body br i1 %cmp, label %for.cond.cleanup, label %for.body
} }
; extern int* get_unknown_pointer(void); ; extern int addrspace(5)* get_unknown_pointer(void);
; kernel void ptr_induction_var_alloca_unknown(void) ; kernel void ptr_induction_var_alloca_unknown(void)
; { ; {
; int alloca[64]; ; int alloca[64];
; int i = 0; ; int i = 0;
; ;
; for (int* p = &alloca[2], *e = get_unknown_pointer(); p != e; ++p, ++i) ; for (int addrspace(5)* p = &alloca[2], *e = get_unknown_pointer(); p != e; ++p, ++i)
; { ; {
; *p = i; ; *p = i;
; } ; }
; } ; }
; CHECK-LABEL: @ptr_induction_var_alloca_unknown( ; CHECK-LABEL: @ptr_induction_var_alloca_unknown(
; CHECK: %alloca = alloca [64 x i32], align 4 ; CHECK: %alloca = alloca [64 x i32], align 4, addrspace(5)
; CHECK: %p.08 = phi i32* [ %incdec.ptr, %for.body ], [ %arrayidx, %for.body.preheader ] ; CHECK: %p.08 = phi i32 addrspace(5)* [ %incdec.ptr, %for.body ], [ %arrayidx, %for.body.preheader ]
; CHECK: %cmp = icmp eq i32* %incdec.ptr, %call ; CHECK: %cmp = icmp eq i32 addrspace(5)* %incdec.ptr, %call
define amdgpu_kernel void @ptr_induction_var_alloca_unknown() #0 { define amdgpu_kernel void @ptr_induction_var_alloca_unknown() #0 {
entry: entry:
%alloca = alloca [64 x i32], align 4 %alloca = alloca [64 x i32], align 4, addrspace(5)
%arrayidx = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 2 %arrayidx = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %alloca, i32 0, i32 2
%call = tail call i32* @get_unknown_pointer() #2 %call = tail call i32 addrspace(5)* @get_unknown_pointer() #2
%cmp.7 = icmp eq i32* %arrayidx, %call %cmp.7 = icmp eq i32 addrspace(5)* %arrayidx, %call
br i1 %cmp.7, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp.7, label %for.cond.cleanup, label %for.body.preheader
for.body.preheader: ; preds = %entry for.body.preheader: ; preds = %entry
Context not available.
for.body: ; preds = %for.body, %for.body.preheader for.body: ; preds = %for.body, %for.body.preheader
%i.09 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] %i.09 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
%p.08 = phi i32* [ %incdec.ptr, %for.body ], [ %arrayidx, %for.body.preheader ] %p.08 = phi i32 addrspace(5)* [ %incdec.ptr, %for.body ], [ %arrayidx, %for.body.preheader ]
store i32 %i.09, i32* %p.08, align 4 store i32 %i.09, i32 addrspace(5)* %p.08, align 4
%incdec.ptr = getelementptr inbounds i32, i32* %p.08, i32 1 %incdec.ptr = getelementptr inbounds i32, i32 addrspace(5)* %p.08, i32 1
%inc = add nuw nsw i32 %i.09, 1 %inc = add nuw nsw i32 %i.09, 1
%cmp = icmp eq i32* %incdec.ptr, %call %cmp = icmp eq i32 addrspace(5)* %incdec.ptr, %call
br i1 %cmp, label %for.cond.cleanup.loopexit, label %for.body br i1 %cmp, label %for.cond.cleanup.loopexit, label %for.body
} }
declare i32* @get_unknown_pointer() #0 declare i32 addrspace(5)* @get_unknown_pointer() #0
attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" } attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }
Context not available.

test/CodeGen/AMDGPU/promote-alloca-volatile.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa-amdgiz -amdgpu-promote-alloca < %s | FileCheck %s
target datalayout = "A5"
; CHECK-LABEL: @volatile_load( ; CHECK-LABEL: @volatile_load(
; CHECK: alloca [4 x i32] ; CHECK: alloca [4 x i32]
; CHECK: load volatile i32, i32* ; CHECK: load volatile i32, i32 addrspace(5)*
define amdgpu_kernel void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { define amdgpu_kernel void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
entry: entry:
%stack = alloca [4 x i32], align 4 %stack = alloca [4 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
%load = load volatile i32, i32* %arrayidx1 %load = load volatile i32, i32 addrspace(5)* %arrayidx1
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: @volatile_store( ; CHECK-LABEL: @volatile_store(
; CHECK: alloca [4 x i32] ; CHECK: alloca [4 x i32]
; CHECK: store volatile i32 %tmp, i32* ; CHECK: store volatile i32 %tmp, i32 addrspace(5)*
define amdgpu_kernel void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { define amdgpu_kernel void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
entry: entry:
%stack = alloca [4 x i32], align 4 %stack = alloca [4 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
store volatile i32 %tmp, i32* %arrayidx1 store volatile i32 %tmp, i32 addrspace(5)* %arrayidx1
ret void ret void
} }
Context not available.
; CHECK: load volatile double ; CHECK: load volatile double
define amdgpu_kernel void @volatile_and_non_volatile_load(double addrspace(1)* nocapture %arg, i32 %arg1) #0 { define amdgpu_kernel void @volatile_and_non_volatile_load(double addrspace(1)* nocapture %arg, i32 %arg1) #0 {
bb: bb:
%tmp = alloca double, align 8 %tmp = alloca double, align 8, addrspace(5)
store double 0.000000e+00, double* %tmp, align 8 store double 0.000000e+00, double addrspace(5)* %tmp, align 8
%tmp4 = load double, double* %tmp, align 8 %tmp4 = load double, double addrspace(5)* %tmp, align 8
%tmp5 = load volatile double, double* %tmp, align 8 %tmp5 = load volatile double, double addrspace(5)* %tmp, align 8
store double %tmp4, double addrspace(1)* %arg store double %tmp4, double addrspace(1)* %arg
ret void ret void
Context not available.

test/CodeGen/AMDGPU/pv-packing.ll

; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman | FileCheck %s
;CHECK: DOT4 T{{[0-9]\.X}} ;CHECK: DOT4 T{{[0-9]\.X}}
;CHECK: MULADD_IEEE * T{{[0-9]\.W}} ;CHECK: MULADD_IEEE * T{{[0-9]\.W}}

test/CodeGen/AMDGPU/pv.ll

; RUN: llc -march=r600 < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz < %s | FileCheck %s
; CHECK: DOT4 * T{{[0-9]\.W}} (MASKED) ; CHECK: DOT4 * T{{[0-9]\.W}} (MASKED)
; CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X ; CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X

test/CodeGen/AMDGPU/r600-constant-array-fixup.ll

; RUN: llc -filetype=obj -march=r600 -mcpu=cypress -verify-machineinstrs < %s | llvm-readobj -relocations -symbols | FileCheck %s ; RUN: llc -filetype=obj -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | llvm-readobj -relocations -symbols | FileCheck %s
@arr = internal unnamed_addr addrspace(2) constant [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 4 @arr = internal unnamed_addr addrspace(2) constant [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 4

test/CodeGen/AMDGPU/r600-encoding.ll

; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s
; The earliest R600 GPUs have a slightly different encoding than the rest of ; The earliest R600 GPUs have a slightly different encoding than the rest of
; the VLIW4/5 GPUs. ; the VLIW4/5 GPUs.

test/CodeGen/AMDGPU/r600-export-fix.ll

; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cedar | FileCheck %s
;CHECK: EXPORT T{{[0-9]}}.XYZW ;CHECK: EXPORT T{{[0-9]}}.XYZW
;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000

test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll

; RUN: llc -march=r600 -mcpu=cayman < %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s
define amdgpu_ps void @main(<4 x float> inreg %arg, <4 x float> inreg %arg1) { define amdgpu_ps void @main(<4 x float> inreg %arg, <4 x float> inreg %arg1) {
main_body: main_body:

test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll

; RUN: llc -march=r600 -mcpu=cypress -start-after safe-stack %s -o - | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -start-after safe-stack %s -o - | FileCheck %s
; Don't crash ; Don't crash
; CHECK: MAX_UINT ; CHECK: MAX_UINT

test/CodeGen/AMDGPU/r600.alu-limits.ll

; RUN: opt -loop-unroll -unroll-threshold=2000 -S < %s | llc -march=r600 -mcpu=cypress | FileCheck %s ; RUN: opt -loop-unroll -unroll-threshold=2000 -S < %s | llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; CHECK: {{^}}alu_limits: ; CHECK: {{^}}alu_limits:
Context not available.
%struct.foo = type {i32, i32, i32} %struct.foo = type {i32, i32, i32}
define amdgpu_kernel void @alu_limits(i32 addrspace(1)* %out, %struct.foo* %in, i32 %offset) { define amdgpu_kernel void @alu_limits(i32 addrspace(1)* %out, %struct.foo addrspace(5)* %in, i32 %offset) {
entry: entry:
%ptr = getelementptr inbounds %struct.foo, %struct.foo* %in, i32 1, i32 2 %ptr = getelementptr inbounds %struct.foo, %struct.foo addrspace(5)* %in, i32 1, i32 2
%x = load i32, i32 *%ptr, align 4 %x = load i32, i32 addrspace(5)*%ptr, align 4
br label %loop br label %loop
loop: loop:
%i = phi i32 [ 100, %entry ], [ %nexti, %loop ] %i = phi i32 [ 100, %entry ], [ %nexti, %loop ]
Context not available.

test/CodeGen/AMDGPU/r600.bitcast.ll

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; This test just checks that the compiler doesn't crash. ; This test just checks that the compiler doesn't crash.

test/CodeGen/AMDGPU/r600.global_atomics.ll

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; TODO: Add _RTN versions and merge with the GCN test ; TODO: Add _RTN versions and merge with the GCN test

test/CodeGen/AMDGPU/r600.private-memory.ll

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
target datalayout = "A5"
declare i32 @llvm.r600.read.tidig.x() nounwind readnone declare i32 @llvm.r600.read.tidig.x() nounwind readnone
Context not available.
; FUNC-LABEL: {{^}}work_item_info: ; FUNC-LABEL: {{^}}work_item_info:
; R600-NOT: MOV T0.X ; R600-NOT: MOV T0.X
; Additional check in case the move ends up in the last slot ; Additional check in case the move ends up in the last slot
; R600-NOT: MOV * TO.X ; R600-NOT: MOV addrspace(5)* TO.X
define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
entry: entry:
%0 = alloca [2 x i32] %0 = alloca [2 x i32], addrspace(5)
%1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 %1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 %2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
store i32 0, i32* %1 store i32 0, i32 addrspace(5)* %1
store i32 1, i32* %2 store i32 1, i32 addrspace(5)* %2
%3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in %3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
%4 = load i32, i32* %3 %4 = load i32, i32 addrspace(5)* %3
%5 = call i32 @llvm.r600.read.tidig.x() %5 = call i32 @llvm.r600.read.tidig.x()
%6 = add i32 %4, %5 %6 = add i32 %4, %5
store i32 %6, i32 addrspace(1)* %out store i32 %6, i32 addrspace(1)* %out
Context not available.

test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}tgid_x: ; FUNC-LABEL: {{^}}tgid_x:
; EG: MEM_RAT_CACHELESS STORE_RAW T1.X ; EG: MEM_RAT_CACHELESS STORE_RAW T1.X
Context not available.
} }
; FUNC-LABEL: {{^}}test_implicit: ; FUNC-LABEL: {{^}}test_implicit:
; 36 prepended implicit bytes + 4(out pointer) + 4*4 = 56 ; 36 prepended implicit bytes + 4(out pointer) + 4 addrspace(5)*4 = 56
; EG: VTX_READ_32 {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, 56 ; EG: VTX_READ_32 {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, 56
define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
%implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr() %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
Context not available.

test/CodeGen/AMDGPU/r600cfg.ll

;RUN: llc < %s -march=r600 -mcpu=redwood ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
main_body: main_body:

test/CodeGen/AMDGPU/rcp-pattern.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}rcp_pat_f32: ; FUNC-LABEL: {{^}}rcp_pat_f32:
; GCN: s_load_dword [[SRC:s[0-9]+]] ; GCN: s_load_dword [[SRC:s[0-9]+]]

test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll

; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: invalid register "flat_scratch_lo" for subtarget. ; CHECK: invalid register "flat_scratch_lo" for subtarget.

test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll

; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: invalid type for register "exec". ; CHECK: invalid type for register "exec".

test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll

; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: invalid type for register "m0". ; CHECK: invalid type for register "m0".

test/CodeGen/AMDGPU/read_register.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s
declare i32 @llvm.read_register.i32(metadata) #0 declare i32 @llvm.read_register.i32(metadata) #0
declare i64 @llvm.read_register.i64(metadata) #0 declare i64 @llvm.read_register.i64(metadata) #0

test/CodeGen/AMDGPU/readcyclecounter.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
declare i64 @llvm.readcyclecounter() #0 declare i64 @llvm.readcyclecounter() #0

test/CodeGen/AMDGPU/reduce-load-width-alignment.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}reduce_i64_load_align_4_width_to_i32: ; GCN-LABEL: {{^}}reduce_i64_load_align_4_width_to_i32:
; GCN: buffer_load_dword [[VAL:v[0-9]+]] ; GCN: buffer_load_dword [[VAL:v[0-9]+]]

test/CodeGen/AMDGPU/reduce-store-width-alignment.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4: ; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2

test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -o /dev/null < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o /dev/null < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o /dev/null < %s
; The register coalescer introduces a verifier error which later ; The register coalescer introduces a verifier error which later
; results in a crash during scheduling. ; results in a crash during scheduling.

test/CodeGen/AMDGPU/register-count-comments.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -asm-verbose < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -asm-verbose < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa-amdgiz -verify-machineinstrs -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0

test/CodeGen/AMDGPU/reorder-stores.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}no_reorder_v2f64_global_load_store: ; SI-LABEL: {{^}}no_reorder_v2f64_global_load_store:
; SI: buffer_load_dwordx4 ; SI: buffer_load_dwordx4

test/CodeGen/AMDGPU/ret.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}vgpr: ; GCN-LABEL: {{^}}vgpr:
; GCN: v_mov_b32_e32 v1, v0 ; GCN: v_mov_b32_e32 v1, v0

test/CodeGen/AMDGPU/ret_jump.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; This should end with an no-op sequence of exec mask manipulations ; This should end with an no-op sequence of exec mask manipulations
; Mask should be in original state after executed unreachable block ; Mask should be in original state after executed unreachable block

test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-any-address-space-out-arguments -amdgpu-rewrite-out-arguments < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa-amdgiz -amdgpu-any-address-space-out-arguments -amdgpu-rewrite-out-arguments < %s | FileCheck %s
; CHECK: %void_one_out_non_private_arg_i32_1_use = type { i32 } ; CHECK: %void_one_out_non_private_arg_i32_1_use = type { i32 }
; CHECK: %bitcast_pointer_as1 = type { <3 x i32> } ; CHECK: %bitcast_pointer_as1 = type { <3 x i32> }

test/CodeGen/AMDGPU/rotl.i64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s
; BOTH-LABEL: {{^}}s_rotl_i64: ; BOTH-LABEL: {{^}}s_rotl_i64:
; BOTH-DAG: s_lshl_b64 ; BOTH-DAG: s_lshl_b64

test/CodeGen/AMDGPU/rotl.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}rotl_i32: ; FUNC-LABEL: {{^}}rotl_i32:
; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x ; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x

test/CodeGen/AMDGPU/rotr.i64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s
; BOTH-LABEL: {{^}}s_rotr_i64: ; BOTH-LABEL: {{^}}s_rotr_i64:
; BOTH-DAG: s_sub_i32 ; BOTH-DAG: s_sub_i32

test/CodeGen/AMDGPU/rotr.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}rotr_i32: ; FUNC-LABEL: {{^}}rotr_i32:
; R600: BIT_ALIGN_INT ; R600: BIT_ALIGN_INT

test/CodeGen/AMDGPU/rsq.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare float @llvm.sqrt.f32(float) nounwind readnone declare float @llvm.sqrt.f32(float) nounwind readnone

test/CodeGen/AMDGPU/rv7x0_count3.ll

; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -show-mc-encoding -mcpu=rv710 | FileCheck %s
; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80] ; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {

test/CodeGen/AMDGPU/s_addk_i32.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}s_addk_i32_k0: ; SI-LABEL: {{^}}s_addk_i32_k0:
; SI: s_load_dword [[VAL:s[0-9]+]] ; SI: s_load_dword [[VAL:s[0-9]+]]

test/CodeGen/AMDGPU/s_movk_i32.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}s_movk_i32_k0: ; SI-LABEL: {{^}}s_movk_i32_k0:
; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}} ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}}

test/CodeGen/AMDGPU/s_mulk_i32.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}s_mulk_i32_k0: ; SI-LABEL: {{^}}s_mulk_i32_k0:
; SI: s_load_dword [[VAL:s[0-9]+]] ; SI: s_load_dword [[VAL:s[0-9]+]]

test/CodeGen/AMDGPU/sad.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}v_sad_u32_pat1: ; GCN-LABEL: {{^}}v_sad_u32_pat1:
; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
Context not available.
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
store volatile i32 %ret0, i32 *undef store volatile i32 %ret0, i32 addrspace(5)*undef
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
Context not available.
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store volatile i32 %ret, i32 *undef store volatile i32 %ret, i32 addrspace(5)*undef
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.
define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b %t0 = select i1 %icmp0, i32 %a, i32 %b
store volatile i32 %t0, i32 *undef store volatile i32 %t0, i32 addrspace(5)*undef
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
Context not available.
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
store volatile i32 %t1, i32 *undef store volatile i32 %t1, i32 addrspace(5)*undef
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
Context not available.
define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b %sub0 = sub i32 %a, %b
store volatile i32 %sub0, i32 *undef store volatile i32 %sub0, i32 addrspace(5)*undef
%sub1 = sub i32 %b, %a %sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
Context not available.
%sub0 = sub i32 %a, %b %sub0 = sub i32 %a, %b
%sub1 = sub i32 %b, %a %sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
store volatile i32 %ret0, i32 *undef store volatile i32 %ret0, i32 addrspace(5)*undef
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
Context not available.

test/CodeGen/AMDGPU/saddo.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs< %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs< %s
declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
declare { i64, i1 } @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone declare { i64, i1 } @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone

test/CodeGen/AMDGPU/salu-to-valu.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0
Context not available.
; Make sure we aren't using VGPRs for the source operand of s_mov_b64 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_* ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_ addrspace(5)*
; instructions ; instructions
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
Context not available.

test/CodeGen/AMDGPU/sampler-resource-id.ll

; RUN: llc -march=r600 -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_0: ; FUNC-LABEL: {{^}}test_0:
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
Context not available.
!0 = !{void (i32, i32 addrspace(1)*)* @test_0, !10, !20, !30, !40, !50} !0 = !{void (i32, i32 addrspace(1)*)* @test_0, !10, !20, !30, !40, !50}
!10 = !{!"kernel_arg_addr_space", i32 0, i32 1} !10 = !{!"kernel_arg_addr_space", i32 0, i32 1}
!20 = !{!"kernel_arg_access_qual", !"none", !"none"} !20 = !{!"kernel_arg_access_qual", !"none", !"none"}
!30 = !{!"kernel_arg_type", !"sampler_t", !"int*"} !30 = !{!"kernel_arg_type", !"sampler_t", !"int addrspace(5)*"}
!40 = !{!"kernel_arg_base_type", !"sampler_t", !"int*"} !40 = !{!"kernel_arg_base_type", !"sampler_t", !"int addrspace(5)*"}
!50 = !{!"kernel_arg_type_qual", !"", !""} !50 = !{!"kernel_arg_type_qual", !"", !""}
!1 = !{void (i32, i32, i32 addrspace(1)*)* @test_1, !11, !21, !31, !41, !51} !1 = !{void (i32, i32, i32 addrspace(1)*)* @test_1, !11, !21, !31, !41, !51}
!11 = !{!"kernel_arg_addr_space", i32 0, i32 0, i32 1} !11 = !{!"kernel_arg_addr_space", i32 0, i32 0, i32 1}
!21 = !{!"kernel_arg_access_qual", !"none", !"none", !"none"} !21 = !{!"kernel_arg_access_qual", !"none", !"none", !"none"}
!31 = !{!"kernel_arg_type", !"sampler_t", !"sampler_t", !"int*"} !31 = !{!"kernel_arg_type", !"sampler_t", !"sampler_t", !"int addrspace(5)*"}
!41 = !{!"kernel_arg_base_type", !"sampler_t", !"sampler_t", !"int*"} !41 = !{!"kernel_arg_base_type", !"sampler_t", !"sampler_t", !"int addrspace(5)*"}
!51 = !{!"kernel_arg_type_qual", !"", !"", !""} !51 = !{!"kernel_arg_type_qual", !"", !"", !""}
!2 = !{void (i32, i32, i32, i32 addrspace(1)*)* @test_2, !12, !22, !32, !42, !52} !2 = !{void (i32, i32, i32, i32 addrspace(1)*)* @test_2, !12, !22, !32, !42, !52}
!12 = !{!"kernel_arg_addr_space", i32 0, i32 0, i32 0, i32 1} !12 = !{!"kernel_arg_addr_space", i32 0, i32 0, i32 0, i32 1}
!22 = !{!"kernel_arg_access_qual", !"none", !"none", !"none", !"none"} !22 = !{!"kernel_arg_access_qual", !"none", !"none", !"none", !"none"}
!32 = !{!"kernel_arg_type", !"sampler_t", !"sampler_t", !"sampler_t", !"int*"} !32 = !{!"kernel_arg_type", !"sampler_t", !"sampler_t", !"sampler_t", !"int addrspace(5)*"}
!42 = !{!"kernel_arg_base_type", !"sampler_t", !"sampler_t", !"sampler_t", !"int*"} !42 = !{!"kernel_arg_base_type", !"sampler_t", !"sampler_t", !"sampler_t", !"int addrspace(5)*"}
!52 = !{!"kernel_arg_type_qual", !"", !"", !"", !""} !52 = !{!"kernel_arg_type_qual", !"", !"", !"", !""}
Context not available.

test/CodeGen/AMDGPU/scalar_to_vector.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; XXX - Why the packing? ; XXX - Why the packing?
; GCN-LABEL: {{^}}scalar_to_vector_v2i32: ; GCN-LABEL: {{^}}scalar_to_vector_v2i32:

test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll

; RUN: llc -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s
; REQUIRES: asserts ; REQUIRES: asserts
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {

test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll

; RUN: llc -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s
; REQUIRES: asserts ; REQUIRES: asserts
define amdgpu_kernel void @main() #0 { define amdgpu_kernel void @main() #0 {

test/CodeGen/AMDGPU/schedule-fs-loop.ll

; RUN: llc -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs < %s
; REQUIRES: asserts ; REQUIRES: asserts
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {

test/CodeGen/AMDGPU/schedule-global-loads.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
; FIXME: This currently doesn't do a great job of clustering the ; FIXME: This currently doesn't do a great job of clustering the
; loads, which end up with extra moves between them. Right now, it ; loads, which end up with extra moves between them. Right now, it

test/CodeGen/AMDGPU/schedule-if-2.ll

;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts ;REQUIRES: asserts
define amdgpu_kernel void @main() { define amdgpu_kernel void @main() {

test/CodeGen/AMDGPU/schedule-if.ll

;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts ;REQUIRES: asserts
define amdgpu_kernel void @main() { define amdgpu_kernel void @main() {

test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI -check-prefix=GCN %s
; FUNC-LABEL: {{^}}cluster_arg_loads: ; FUNC-LABEL: {{^}}cluster_arg_loads:
; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9

test/CodeGen/AMDGPU/schedule-regpressure-limit.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck %s
; We expect a two digit VGPR usage here, not a three digit. ; We expect a two digit VGPR usage here, not a three digit.
; CHECK: NumVgprs: {{[0-9][0-9]$}} ; CHECK: NumVgprs: {{[0-9][0-9]$}}

test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
; SI: NumSgprs: {{[1-9]$}} ; SI: NumSgprs: {{[1-9]$}}
; SI: NumVgprs: {{[1-9]$}} ; SI: NumVgprs: {{[1-9]$}}

test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll

; RUN: llc -O0 -march=amdgcn -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s
declare void @llvm.amdgcn.s.barrier() nounwind convergent declare void @llvm.amdgcn.s.barrier() nounwind convergent

test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll

;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -stress-sched -verify-misched
;REQUIRES: asserts ;REQUIRES: asserts
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {

test/CodeGen/AMDGPU/scheduler-subrange-crash.ll

; RUN: llc -march=amdgcn < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; ;
; This test used to crash with the following assertion: ; This test used to crash with the following assertion:
; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed. ; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval addrspace(5)*, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval addrspace(5)*, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.
; ;
; This was related to incorrectly calculating subregister live ranges ; This was related to incorrectly calculating subregister live ranges
; (i.e. live interval subranges): subregister defs are not uses for that ; (i.e. live interval subranges): subregister defs are not uses for that

test/CodeGen/AMDGPU/scratch-buffer.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
; When a frame index offset is more than 12-bits, make sure we don't store ; When a frame index offset is more than 12-bits, make sure we don't store
; it in mubuf's offset field. ; it in mubuf's offset field.
Context not available.
define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) { define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 0 %scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 0
store i32 1, i32* %scratchptr0 store i32 1, i32 addrspace(5)* %scratchptr0
%scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 0 %scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 0
store i32 2, i32* %scratchptr1 store i32 2, i32 addrspace(5)* %scratchptr1
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else br i1 %cmp, label %if, label %else
if: if:
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
%if_value = load i32, i32* %if_ptr %if_value = load i32, i32 addrspace(5)* %if_ptr
br label %done br label %done
else: else:
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
%else_value = load i32, i32* %else_ptr %else_value = load i32, i32 addrspace(5)* %else_ptr
br label %done br label %done
done: done:
Context not available.
define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) { define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%offset0 = load i32, i32 addrspace(1)* %offsets %offset0 = load i32, i32 addrspace(1)* %offsets
%scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %offset0 %scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %offset0
store i32 %offset0, i32* %scratchptr0 store i32 %offset0, i32 addrspace(5)* %scratchptr0
%offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1 %offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1
%offset1 = load i32, i32 addrspace(1)* %offsetptr1 %offset1 = load i32, i32 addrspace(1)* %offsetptr1
%scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %offset1 %scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %offset1
store i32 %offset1, i32* %scratchptr1 store i32 %offset1, i32 addrspace(5)* %scratchptr1
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else br i1 %cmp, label %if, label %else
if: if:
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
%if_value = load i32, i32* %if_ptr %if_value = load i32, i32 addrspace(5)* %if_ptr
br label %done br label %done
else: else:
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
%else_value = load i32, i32* %else_ptr %else_value = load i32, i32 addrspace(5)* %else_ptr
br label %done br label %done
done: done:
Context not available.
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:16{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:16{{$}}
define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) { define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) {
entry: entry:
%array = alloca [8192 x i32] %array = alloca [8192 x i32], addrspace(5)
%ptr_offset = add i32 %offset, 4 %ptr_offset = add i32 %offset, 4
%ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset %ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
store i32 0, i32* %ptr store i32 0, i32 addrspace(5)* %ptr
ret void ret void
} }
Context not available.
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:20 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:20
define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) { define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) {
entry: entry:
%array = alloca [8192 x i32] %array = alloca [8192 x i32], addrspace(5)
%ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 4 %ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 4
store i32 0, i32* %ptr store i32 0, i32 addrspace(5)* %ptr
%load_ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %offset %load_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %offset
%val = load i32, i32* %load_ptr %val = load i32, i32 addrspace(5)* %load_ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/sdiv.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; The code generated by sdiv is long and complex and may frequently change. ; The code generated by sdiv is long and complex and may frequently change.
; The goal of this test is to make sure the ISel doesn't fail. ; The goal of this test is to make sure the ISel doesn't fail.

test/CodeGen/AMDGPU/sdivrem24.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}sdiv24_i8: ; FUNC-LABEL: {{^}}sdiv24_i8:
; SI: v_cvt_f32_i32 ; SI: v_cvt_f32_i32

test/CodeGen/AMDGPU/sdivrem64.ll

;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
;RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s ;RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
;FUNC-LABEL: {{^}}s_test_sdiv: ;FUNC-LABEL: {{^}}s_test_sdiv:
;EG: RECIP_UINT ;EG: RECIP_UINT

test/CodeGen/AMDGPU/sdwa-peephole.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=NOSDWA -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-sdwa-peephole=0 -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=NOSDWA -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SDWA -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-sdwa-peephole -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SDWA -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -amdgpu-sdwa-peephole -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=SDWA -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -amdgpu-sdwa-peephole -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=SDWA -check-prefix=GCN %s
; GCN-LABEL: {{^}}add_shr_i32: ; GCN-LABEL: {{^}}add_shr_i32:
; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}} ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}

test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; -------------------------------------------------------------------------------- ; --------------------------------------------------------------------------------
; Don't fold if fneg can fold into the source ; Don't fold if fneg can fold into the source

test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}add_select_fabs_fabs_f32: ; GCN-LABEL: {{^}}add_select_fabs_fabs_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]

test/CodeGen/AMDGPU/select-i1.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI ; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI

test/CodeGen/AMDGPU/select-opt.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Make sure to test with f32 and i32 compares. If we have to use float ; Make sure to test with f32 and i32 compares. If we have to use float
; compares, we always have multiple condition registers. If we can do ; compares, we always have multiple condition registers. If we can do

test/CodeGen/AMDGPU/select-vectors.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; Test expansion of scalar selects on vectors. ; Test expansion of scalar selects on vectors.
; Evergreen not enabled since it seems to be having problems with doubles. ; Evergreen not enabled since it seems to be having problems with doubles.

test/CodeGen/AMDGPU/select.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}select_f16: ; GCN-LABEL: {{^}}select_f16:
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/select.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; Normally icmp + select is optimized to select_cc, when this happens the ; Normally icmp + select is optimized to select_cc, when this happens the

test/CodeGen/AMDGPU/select64.ll

; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: {{^}}select0: ; CHECK-LABEL: {{^}}select0:
; i64 select should be split into two i32 selects, and we shouldn't need ; i64 select should be split into two i32 selects, and we shouldn't need

test/CodeGen/AMDGPU/selectcc-cnd.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK-NOT: SETE ;CHECK-NOT: SETE
;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x, ;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,

test/CodeGen/AMDGPU/selectcc-cnde-int.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK-NOT: SETE_INT ;CHECK-NOT: SETE_INT
;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x, ;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,

test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; Note additional optimizations may cause this SGT to be replaced with a ; Note additional optimizations may cause this SGT to be replaced with a
; CND* instruction. ; CND addrspace(5)* instruction.
; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, literal.x, ; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, literal.x,
; CHECK-NEXT: -1 ; CHECK-NEXT: -1
; Test a selectcc with i32 LHS/RHS and float True/False ; Test a selectcc with i32 LHS/RHS and float True/False

test/CodeGen/AMDGPU/selectcc-opt.ll

; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_a: ; FUNC-LABEL: {{^}}test_a:
Context not available.
ret void ret void
} }
; Test a CND*_INT instruction with float true/false values ; Test a CND addrspace(5)*_INT instruction with float true/false values
; EG-LABEL: {{^}}test_c: ; EG-LABEL: {{^}}test_c:
; EG: CND{{[GTE]+}}_INT ; EG: CND{{[GTE]+}}_INT
define amdgpu_kernel void @test_c(float addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @test_c(float addrspace(1)* %out, i32 %in) {
Context not available.

test/CodeGen/AMDGPU/selectcc.ll

; RUN: llc -verify-machineinstrs -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}selectcc_i64: ; FUNC-LABEL: {{^}}selectcc_i64:
; EG: XOR_INT ; EG: XOR_INT

test/CodeGen/AMDGPU/selected-stack-object.ll

; "Assertion failure" should be caught with both XFAIL * and +Asserts. ; "Assertion failure" should be caught with both XFAIL addrspace(5)* and +Asserts.
; XFAIL: * ; XFAIL: *
; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; See also local-stack-slot-bug.ll ; See also local-stack-slot-bug.ll
; This fails because a stack object is created during instruction selection. ; This fails because a stack object is created during instruction selection.

test/CodeGen/AMDGPU/set-dx10.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; These tests check that floating point comparisons which are used by select ; These tests check that floating point comparisons which are used by select
; to store integer true (-1) and false (0) values are lowered to one of the ; to store integer true (-1) and false (0) values are lowered to one of the

test/CodeGen/AMDGPU/setcc-equivalent.ll

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
; EG-LABEL: {{^}}and_setcc_setcc_i32: ; EG-LABEL: {{^}}and_setcc_setcc_i32:
; EG: AND_INT ; EG: AND_INT

test/CodeGen/AMDGPU/setcc-fneg-constant.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine. ; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.

test/CodeGen/AMDGPU/setcc-opt.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}sext_bool_icmp_eq_0: ; FUNC-LABEL: {{^}}sext_bool_icmp_eq_0:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp

test/CodeGen/AMDGPU/setcc-sext.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}setcc_sgt_true_sext: ; GCN-LABEL: {{^}}setcc_sgt_true_sext:
; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}

test/CodeGen/AMDGPU/setcc64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s| FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s| FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; XXX: Merge this into setcc, once R600 supports 64-bit operations ; XXX: Merge this into setcc, once R600 supports 64-bit operations

test/CodeGen/AMDGPU/seto.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]] ; CHECK: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]]

test/CodeGen/AMDGPU/setuo.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: v_cmp_u_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]] ; CHECK: v_cmp_u_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]]

test/CodeGen/AMDGPU/sext-eliminate.ll

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}sext_in_reg_i1_i32_add: ; FUNC-LABEL: {{^}}sext_in_reg_i1_i32_add:

test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll

; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
; ;
; EG-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount: ; EG-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount:
; EG: MEM_{{.*}} MSKOR [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} MSKOR [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]

test/CodeGen/AMDGPU/sgpr-control-flow.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; ;
; ;
; Most SALU instructions ignore control flow, so we need to make sure ; Most SALU instructions ignore control flow, so we need to make sure

test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; Copy VGPR -> SGPR used twice as an instruction operand, which is then ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
; used in an REG_SEQUENCE that also needs to be handled. ; used in an REG_SEQUENCE that also needs to be handled.

test/CodeGen/AMDGPU/sgpr-copy.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}phi1: ; CHECK-LABEL: {{^}}phi1:
; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0

test/CodeGen/AMDGPU/sgprcopies.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}checkTwoBlocksWithUniformBranch ; GCN-LABEL: {{^}}checkTwoBlocksWithUniformBranch
; GCN: BB0_2 ; GCN: BB0_2

test/CodeGen/AMDGPU/shared-op-cycle.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; CHECK: {{^}}main: ; CHECK: {{^}}main:
; CHECK: MULADD_IEEE * ; CHECK: MULADD_IEEE *

test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Extract the high bit of the 1st quarter ; Extract the high bit of the 1st quarter
; GCN-LABEL: {{^}}v_uextract_bit_31_i128: ; GCN-LABEL: {{^}}v_uextract_bit_31_i128:

test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Fails with -enable-var-scope ; FIXME: Fails with -enable-var-scope
; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half. ; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.

test/CodeGen/AMDGPU/shift-i64-opts.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=FAST64 -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=FAST64 -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=SLOW64 -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire < %s | FileCheck -check-prefix=SLOW64 -check-prefix=GCN %s
; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 0 ; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 0

test/CodeGen/AMDGPU/shl-add-to-add-shl.ll

; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji < %s | FileCheck %s
; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1) ; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1)
; Only one shift if expected, GEP shall not produce a separate shift ; Only one shift if expected, GEP shall not produce a separate shift

test/CodeGen/AMDGPU/shl.v2i16.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
; GCN-LABEL: {{^}}s_shl_v2i16: ; GCN-LABEL: {{^}}s_shl_v2i16:
; GFX9: s_load_dword [[LHS:s[0-9]+]] ; GFX9: s_load_dword [[LHS:s[0-9]+]]

test/CodeGen/AMDGPU/shl_add_constant.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1

test/CodeGen/AMDGPU/shl_add_ptr.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
; Test that doing a shift of a pointer with a constant add will be ; Test that doing a shift of a pointer with a constant add will be
; folded into the constant offset addressing mode even if the add has ; folded into the constant offset addressing mode even if the add has

test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Test that add/sub with a constant is swapped to sub/add with negated ; Test that add/sub with a constant is swapped to sub/add with negated
; constant to minimize code size. ; constant to minimize code size.

test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll

; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn---amdgiz -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; OPT-LABEL: @annotate_unreachable_noloop( ; OPT-LABEL: @annotate_unreachable_noloop(

test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll

; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn---amdgiz -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; OPT-LABEL: @annotate_unreachable( ; OPT-LABEL: @annotate_unreachable(

test/CodeGen/AMDGPU/si-annotate-cf.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; FUNC-LABEL: {{^}}break_inserted_outside_of_loop: ; FUNC-LABEL: {{^}}break_inserted_outside_of_loop:

test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll

; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test: ; CHECK-LABEL: {{^}}test:
; CHECK s_and_saveexec_b64 ; CHECK s_and_saveexec_b64

test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll

; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s ; RUN: llc -o - %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s
; This test verifies that the instruction selection will add the implicit ; This test verifies that the instruction selection will add the implicit
; register operands in the correct order when modifying the opcode of an ; register operands in the correct order when modifying the opcode of an
; instruction to V_ADD_I32_e32. ; instruction to V_ADD_I32_e32.

test/CodeGen/AMDGPU/si-lod-bias.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; This shader has the potential to generated illegal VGPR to SGPR copies if ; This shader has the potential to generated illegal VGPR to SGPR copies if
; the wrong register class is used for the REG_SEQUENCE instructions. ; the wrong register class is used for the REG_SEQUENCE instructions.

test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}if_with_kill: ; GCN-LABEL: {{^}}if_with_kill:
; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]], ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]],

test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator: ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
; GCN: v_cmp_eq_u32 ; GCN: v_cmp_eq_u32

test/CodeGen/AMDGPU/si-scheduler.ll

Context not available.
; The only way the subtarget knows that the si machine scheduler is being used ; The only way the subtarget knows that the si machine scheduler is being used
; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend ; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend
; won't know what scheduler we are using. ; won't know what scheduler we are using.
; RUN: llc -march=amdgcn --misched=si -mattr=si-scheduler < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz --misched=si -mattr=si-scheduler < %s | FileCheck %s
; The test checks the "si" machine scheduler pass works correctly. ; The test checks the "si" machine scheduler pass works correctly.
Context not available.

test/CodeGen/AMDGPU/si-sgpr-spill.ll

; RUN: llc -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=TOVGPR %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=TOVGPR %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling,-mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+vgpr-spilling,-mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; These tests check that the compiler won't crash when it needs to spill ; These tests check that the compiler won't crash when it needs to spill
; SGPRs. ; SGPRs.

test/CodeGen/AMDGPU/si-spill-cf.ll

; RUN: llc -march=amdgcn < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s
; If this occurs it is likely due to reordering and the restore was ; If this occurs it is likely due to reordering and the restore was
; originally supposed to happen before SI_END_CF. ; originally supposed to happen before SI_END_CF.

test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll

; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
; Make sure this doesn't crash. ; Make sure this doesn't crash.
; ALL-LABEL: {{^}}test: ; ALL-LABEL: {{^}}test:

test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)

test/CodeGen/AMDGPU/si-vector-hang.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s
; CHECK: {{^}}test_8_min_char: ; CHECK: {{^}}test_8_min_char:
; CHECK: buffer_store_byte ; CHECK: buffer_store_byte

test/CodeGen/AMDGPU/sign_extend.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; GCN-LABEL: {{^}}s_sext_i1_to_i32: ; GCN-LABEL: {{^}}s_sext_i1_to_i32:
; GCN: v_cndmask_b32_e64 ; GCN: v_cndmask_b32_e64

test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll

; RUN: llc -march=amdgcn < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck %s
; Check we can compile this bugpoint-reduced test without an ; Check we can compile this bugpoint-reduced test without an
; infinite loop in TLI.SimplifyDemandedBits() due to failure ; infinite loop in TLI.SimplifyDemandedBits() due to failure

test/CodeGen/AMDGPU/sint_to_fp.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/sint_to_fp.i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
; FIXME: This should be merged with sint_to_fp.ll, but s_sint_to_fp_v2i64 crashes on r600 ; FIXME: This should be merged with sint_to_fp.ll, but s_sint_to_fp_v2i64 crashes on r600

test/CodeGen/AMDGPU/sint_to_fp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}s_sint_to_fp_i32_to_f32: ; FUNC-LABEL: {{^}}s_sint_to_fp_i32_to_f32:
; SI: v_cvt_f32_i32_e32 {{v[0-9]+}}, {{s[0-9]+$}} ; SI: v_cvt_f32_i32_e32 {{v[0-9]+}}, {{s[0-9]+$}}

test/CodeGen/AMDGPU/sitofp.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}sitofp_i16_to_f16 ; GCN-LABEL: {{^}}sitofp_i16_to_f16
; GCN: buffer_load_{{sshort|ushort}} v[[A_I16:[0-9]+]] ; GCN: buffer_load_{{sshort|ushort}} v[[A_I16:[0-9]+]]

test/CodeGen/AMDGPU/skip-if-dead.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos: ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos:
; CHECK-NEXT: ; BB#0: ; CHECK-NEXT: ; BB#0:

test/CodeGen/AMDGPU/smed3.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0

test/CodeGen/AMDGPU/sminmax.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}s_abs_i32: ; FUNC-LABEL: {{^}}s_abs_i32:
; GCN: s_abs_i32 ; GCN: s_abs_i32

test/CodeGen/AMDGPU/sminmax.v2i16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=CIVI -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=CIVI -check-prefix=GCN %s
; GCN-LABEL: {{^}}s_abs_v2i16: ; GCN-LABEL: {{^}}s_abs_v2i16:
; GFX9: s_load_dword [[VAL:s[0-9]+]] ; GFX9: s_load_dword [[VAL:s[0-9]+]]

test/CodeGen/AMDGPU/smrd-vccz-bug.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s
; GCN-FUNC: {{^}}vccz_workaround: ; GCN-FUNC: {{^}}vccz_workaround:
; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0

test/CodeGen/AMDGPU/smrd.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICI -check-prefix=SIVIGFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICI -check-prefix=SIVIGFX9 %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
; SMRD load with an immediate offset. ; SMRD load with an immediate offset.
; GCN-LABEL: {{^}}smrd0: ; GCN-LABEL: {{^}}smrd0:

test/CodeGen/AMDGPU/sopk-compares.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Since this intrinsic is exposed as a constant after isel, use it to ; Since this intrinsic is exposed as a constant after isel, use it to
; defeat the DAG's compare with constant canonicalizations. ; defeat the DAG's compare with constant canonicalizations.

test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=TONGA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=TONGA %s
target datalayout = "A5"
; On Tonga and Iceland, limited SGPR availability means care must be taken to ; On Tonga and Iceland, limited SGPR availability means care must be taken to
; allocate scratch registers correctly. Check that this test compiles without ; allocate scratch registers correctly. Check that this test compiles without

test/CodeGen/AMDGPU/spill-cfg-position.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -stress-regalloc=6 < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -stress-regalloc=6 < %s | FileCheck %s
; Inline spiller can decide to move a spill as early as possible in the basic block. ; Inline spiller can decide to move a spill as early as possible in the basic block.
; It will skip phis and label, but we also need to make sure it skips instructions ; It will skip phis and label, but we also need to make sure it skips instructions

test/CodeGen/AMDGPU/spill-m0.ll

; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=1 -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=GCN %s ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=1 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=GCN %s
; XXX - Why does it like to use vcc? ; XXX - Why does it like to use vcc?

test/CodeGen/AMDGPU/spill-scavenge-offset.ll

; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s ; RUN: llc -regalloc=basic -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
target datalayout = "A5"
; ;
; There is something about Tonga that causes this test to spend a lot of time ; There is something about Tonga that causes this test to spend a lot of time
; in the default register allocator. ; in the default register allocator.

test/CodeGen/AMDGPU/spill-to-smem-m0.ll

; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs -stop-before=prologepilog < %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs -stop-before=prologepilog < %s
; Spill to SMEM clobbers M0. Check that the implicit-def dead operand is present ; Spill to SMEM clobbers M0. Check that the implicit-def dead operand is present
; in the pseudo instructions. ; in the pseudo instructions.

test/CodeGen/AMDGPU/spill-wide-sgpr.ll

; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s
; ALL-LABEL: {{^}}spill_sgpr_x2: ; ALL-LABEL: {{^}}spill_sgpr_x2:
; SMEM: s_add_u32 m0, s3, 0x100{{$}} ; SMEM: s_add_u32 m0, s3, 0x100{{$}}

test/CodeGen/AMDGPU/split-scalar-i64-add.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() readnone declare i32 @llvm.amdgcn.workitem.id.x() readnone

test/CodeGen/AMDGPU/split-smrd.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Move this to sgpr-copy.ll when this is fixed on VI. ; FIXME: Move this to sgpr-copy.ll when this is fixed on VI.
; Make sure that when we split an smrd instruction in order to move it to ; Make sure that when we split an smrd instruction in order to move it to

test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll

; RUN: llc -march=amdgcn -mcpu=hawaii -enable-amdgpu-aa=0 -verify-machineinstrs -mattr=-promote-alloca,-load-store-opt < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -enable-amdgpu-aa=0 -verify-machineinstrs -mattr=-promote-alloca,-load-store-opt < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
@sPrivateStorage = internal addrspace(3) global [256 x [8 x <4 x i64>]] undef @sPrivateStorage = internal addrspace(3) global [256 x [8 x <4 x i64>]] undef

test/CodeGen/AMDGPU/srem.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s
define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
%den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1

test/CodeGen/AMDGPU/srl.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; XUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() #0 declare i32 @llvm.r600.read.tidig.x() #0

test/CodeGen/AMDGPU/ssubo.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs< %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs< %s
declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone

test/CodeGen/AMDGPU/store-barrier.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s
; This test is for a bug in the machine scheduler where stores without ; This test is for a bug in the machine scheduler where stores without
; an underlying object would be moved across the barrier. In this ; an underlying object would be moved across the barrier. In this

test/CodeGen/AMDGPU/store-hi16.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; GCN-LABEL: {{^}}store_global_hi_v2i16: ; GCN-LABEL: {{^}}store_global_hi_v2i16:
; GCN: s_waitcnt ; GCN: s_waitcnt
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16(i16 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16(i16* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
store i16 %hi, i16 addrspace(4)* %out store i16 %hi, i16* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2f16(half addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2f16(half* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x half> %value = bitcast i32 %arg to <2 x half>
%hi = extractelement <2 x half> %value, i32 1 %hi = extractelement <2 x half> %value, i32 1
store half %hi, half addrspace(4)* %out store half %hi, half* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_i32_shift(i16 addrspace(4)* %out, i32 %value) #0 { define void @store_flat_hi_i32_shift(i16* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i16 %hi = trunc i32 %hi32 to i16
store i16 %hi, i16 addrspace(4)* %out store i16 %hi, i16* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8(i8 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_i8(i8* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store i8 %trunc, i8 addrspace(4)* %out store i8 %trunc, i8* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_i8_shift(i8 addrspace(4)* %out, i32 %value) #0 { define void @store_flat_hi_i8_shift(i8* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i8 %hi = trunc i32 %hi32 to i8
store i8 %hi, i8 addrspace(4)* %out store i8 %hi, i8* %out
ret void ret void
} }
Context not available.
; VI: flat_store_short v[0:1], v2{{$}} ; VI: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_max_offset(i16 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_max_offset(i16* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds i16, i16 addrspace(4)* %out, i64 2047 %gep = getelementptr inbounds i16, i16* %out, i64 2047
store i16 %hi, i16 addrspace(4)* %gep store i16 %hi, i16* %gep
ret void ret void
} }
Context not available.
; VI: flat_store_short v[0:1], v2{{$}} ; VI: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_neg_offset(i16 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_neg_offset(i16* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds i16, i16 addrspace(4)* %out, i64 -1023 %gep = getelementptr inbounds i16, i16* %out, i64 -1023
store i16 %hi, i16 addrspace(4)* %gep store i16 %hi, i16* %gep
ret void ret void
} }
Context not available.
; VI: flat_store_byte v[0:1], v2{{$}} ; VI: flat_store_byte v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8_max_offset(i8 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_i8_max_offset(i8* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
%gep = getelementptr inbounds i8, i8 addrspace(4)* %out, i64 4095 %gep = getelementptr inbounds i8, i8* %out, i64 4095
store i8 %trunc, i8 addrspace(4)* %gep store i8 %trunc, i8* %gep
ret void ret void
} }
Context not available.
; VI: flat_store_byte v[0:1], v2{{$}} ; VI: flat_store_byte v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8_neg_offset(i8 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_i8_neg_offset(i8* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
%gep = getelementptr inbounds i8, i8 addrspace(4)* %out, i64 -4095 %gep = getelementptr inbounds i8, i8* %out, i64 -4095
store i8 %trunc, i8 addrspace(4)* %gep store i8 %trunc, i8* %gep
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16(i16* %out, i32 %arg) #0 { define void @store_private_hi_v2i16(i16 addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
; FIXME: ABI for pre-gfx9 ; FIXME: ABI for pre-gfx9
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
store i16 %hi, i16* %out store i16 %hi, i16 addrspace(5)* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2f16(half* %out, i32 %arg) #0 { define void @store_private_hi_v2f16(half addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
; FIXME: ABI for pre-gfx9 ; FIXME: ABI for pre-gfx9
%value = bitcast i32 %arg to <2 x half> %value = bitcast i32 %arg to <2 x half>
%hi = extractelement <2 x half> %value, i32 1 %hi = extractelement <2 x half> %value, i32 1
store half %hi, half* %out store half %hi, half addrspace(5)* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_i32_shift(i16* %out, i32 %value) #0 { define void @store_private_hi_i32_shift(i16 addrspace(5)* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i16 %hi = trunc i32 %hi32 to i16
store i16 %hi, i16* %out store i16 %hi, i16 addrspace(5)* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_i8(i8* %out, i32 %arg) #0 { define void @store_private_hi_v2i16_i8(i8 addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store i8 %trunc, i8* %out store i8 %trunc, i8 addrspace(5)* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_i8_shift(i8* %out, i32 %value) #0 { define void @store_private_hi_i8_shift(i8 addrspace(5)* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i8 %hi = trunc i32 %hi32 to i8
store i8 %hi, i8* %out store i8 %hi, i8 addrspace(5)* %out
ret void ret void
} }
Context not available.
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_max_offset(i16* %out, i32 %arg) #0 { define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds i16, i16* %out, i64 2047 %gep = getelementptr inbounds i16, i16 addrspace(5)* %out, i64 2047
store i16 %hi, i16* %gep store i16 %hi, i16 addrspace(5)* %gep
ret void ret void
} }
Context not available.
; FIXME: ABI for pre-gfx9 ; FIXME: ABI for pre-gfx9
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
store volatile i16 %hi, i16* null store volatile i16 %hi, i16 addrspace(5)* null
ret void ret void
} }
Context not available.
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store volatile i8 %trunc, i8* null store volatile i8 %trunc, i8 addrspace(5)* null
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/store-private.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}store_i1: ; FUNC-LABEL: {{^}}store_i1:
; EG: MOVA_INT ; EG: MOVA_INT
Context not available.
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_i1(i1 addrspace(0)* %out) { define amdgpu_kernel void @store_i1(i1 addrspace(5)* %out) {
entry: entry:
store i1 true, i1 addrspace(0)* %out store i1 true, i1 addrspace(5)* %out
ret void ret void
} }
Context not available.
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_i8(i8 addrspace(0)* %out, i8 %in) { define amdgpu_kernel void @store_i8(i8 addrspace(5)* %out, i8 %in) {
entry: entry:
store i8 %in, i8 addrspace(0)* %out store i8 %in, i8 addrspace(5)* %out
ret void ret void
} }
Context not available.
; EG: MOV * T(0 + AR.x).X+, [[RES]] ; EG: MOV * T(0 + AR.x).X+, [[RES]]
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_i16(i16 addrspace(0)* %out, i16 %in) { define amdgpu_kernel void @store_i16(i16 addrspace(5)* %out, i16 %in) {
entry: entry:
store i16 %in, i16 addrspace(0)* %out store i16 %in, i16 addrspace(5)* %out
ret void ret void
} }
Context not available.
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
define amdgpu_kernel void @store_i24(i24 addrspace(0)* %out, i24 %in) { define amdgpu_kernel void @store_i24(i24 addrspace(5)* %out, i24 %in) {
entry: entry:
store i24 %in, i24 addrspace(0)* %out store i24 %in, i24 addrspace(5)* %out
ret void ret void
} }
Context not available.
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
define amdgpu_kernel void @store_i25(i25 addrspace(0)* %out, i25 %in) { define amdgpu_kernel void @store_i25(i25 addrspace(5)* %out, i25 %in) {
entry: entry:
store i25 %in, i25 addrspace(0)* %out store i25 %in, i25 addrspace(5)* %out
ret void ret void
} }
Context not available.
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i8> %0 = trunc <2 x i32> %in to <2 x i8>
store <2 x i8> %0, <2 x i8> addrspace(0)* %out store <2 x i8> %0, <2 x i8> addrspace(5)* %out
ret void ret void
} }
Context not available.
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i8> %0 = trunc <2 x i32> %in to <2 x i8>
store <2 x i8> %0, <2 x i8> addrspace(0)* %out, align 1 store <2 x i8> %0, <2 x i8> addrspace(5)* %out, align 1
ret void ret void
} }
Context not available.
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i16> %0 = trunc <2 x i32> %in to <2 x i16>
store <2 x i16> %0, <2 x i16> addrspace(0)* %out store <2 x i16> %0, <2 x i16> addrspace(5)* %out
ret void ret void
} }
Context not available.
; SI: buffer_store_short ; SI: buffer_store_short
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i16> %0 = trunc <2 x i32> %in to <2 x i16>
store <2 x i16> %0, <2 x i16> addrspace(0)* %out, align 2 store <2 x i16> %0, <2 x i16> addrspace(5)* %out, align 2
ret void ret void
} }
Context not available.
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i8> %0 = trunc <4 x i32> %in to <4 x i8>
store <4 x i8> %0, <4 x i8> addrspace(0)* %out store <4 x i8> %0, <4 x i8> addrspace(5)* %out
ret void ret void
} }
Context not available.
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI-NOT: buffer_store_dword ; SI-NOT: buffer_store_dword
define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i8> %0 = trunc <4 x i32> %in to <4 x i8>
store <4 x i8> %0, <4 x i8> addrspace(0)* %out, align 1 store <4 x i8> %0, <4 x i8> addrspace(5)* %out, align 1
ret void ret void
} }
Context not available.
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI-NOT: buffer_store_dword ; SI-NOT: buffer_store_dword
define amdgpu_kernel void @store_v8i8_unaligned(<8 x i8> addrspace(0)* %out, <8 x i32> %in) { define amdgpu_kernel void @store_v8i8_unaligned(<8 x i8> addrspace(5)* %out, <8 x i32> %in) {
entry: entry:
%0 = trunc <8 x i32> %in to <8 x i8> %0 = trunc <8 x i32> %in to <8 x i8>
store <8 x i8> %0, <8 x i8> addrspace(0)* %out, align 1 store <8 x i8> %0, <8 x i8> addrspace(5)* %out, align 1
ret void ret void
} }
Context not available.
; SI: buffer_store_short ; SI: buffer_store_short
; SI: buffer_store_short ; SI: buffer_store_short
; SI-NOT: buffer_store_dword ; SI-NOT: buffer_store_dword
define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i8> %0 = trunc <4 x i32> %in to <4 x i8>
store <4 x i8> %0, <4 x i8> addrspace(0)* %out, align 2 store <4 x i8> %0, <4 x i8> addrspace(5)* %out, align 2
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_f32(float addrspace(0)* %out, float %in) { define amdgpu_kernel void @store_f32(float addrspace(5)* %out, float %in) {
store float %in, float addrspace(0)* %out store float %in, float addrspace(5)* %out
ret void ret void
} }
Context not available.
; XSI: buffer_store_dwordx2 ; XSI: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i16> %0 = trunc <4 x i32> %in to <4 x i16>
store <4 x i16> %0, <4 x i16> addrspace(0)* %out store <4 x i16> %0, <4 x i16> addrspace(5)* %out
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(0)* %out, float %a, float %b) { define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(5)* %out, float %a, float %b) {
entry: entry:
%0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
%1 = insertelement <2 x float> %0, float %b, i32 1 %1 = insertelement <2 x float> %0, float %b, i32 1
store <2 x float> %1, <2 x float> addrspace(0)* %out store <2 x float> %1, <2 x float> addrspace(5)* %out
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(0)* %out, <3 x i32> %a) nounwind { define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(5)* %out, <3 x i32> %a) nounwind {
store <3 x i32> %a, <3 x i32> addrspace(0)* %out, align 16 store <3 x i32> %a, <3 x i32> addrspace(5)* %out, align 16
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
store <4 x i32> %in, <4 x i32> addrspace(0)* %out store <4 x i32> %in, <4 x i32> addrspace(5)* %out
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
store <4 x i32> %in, <4 x i32> addrspace(0)* %out, align 4 store <4 x i32> %in, <4 x i32> addrspace(5)* %out, align 4
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(0)* %out, <4 x float> addrspace(0)* %in) { define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(5)* %out, <4 x float> addrspace(5)* %in) {
%1 = load <4 x float>, <4 x float> addrspace(0) * %in %1 = load <4 x float>, <4 x float> addrspace(5)* %in
store <4 x float> %1, <4 x float> addrspace(0)* %out store <4 x float> %1, <4 x float> addrspace(5)* %out
ret void ret void
} }
Context not available.
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_i64_i8(i8 addrspace(0)* %out, i64 %in) { define amdgpu_kernel void @store_i64_i8(i8 addrspace(5)* %out, i64 %in) {
entry: entry:
%0 = trunc i64 %in to i8 %0 = trunc i64 %in to i8
store i8 %0, i8 addrspace(0)* %out store i8 %0, i8 addrspace(5)* %out
ret void ret void
} }
Context not available.
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_i64_i16(i16 addrspace(0)* %out, i64 %in) { define amdgpu_kernel void @store_i64_i16(i16 addrspace(5)* %out, i64 %in) {
entry: entry:
%0 = trunc i64 %in to i16 %0 = trunc i64 %in to i16
store i16 %0, i16 addrspace(0)* %out store i16 %0, i16 addrspace(5)* %out
ret void ret void
} }
Context not available.
; XSI: buffer_store_dwordx2 ; XSI: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @vecload2(i32 addrspace(0)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { define amdgpu_kernel void @vecload2(i32 addrspace(5)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
entry: entry:
%0 = load i32, i32 addrspace(2)* %mem, align 4 %0 = load i32, i32 addrspace(2)* %mem, align 4
%arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1 %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
%1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4 %1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
store i32 %0, i32 addrspace(0)* %out, align 4 store i32 %0, i32 addrspace(5)* %out, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
store i32 %1, i32 addrspace(0)* %arrayidx1, align 4 store i32 %1, i32 addrspace(5)* %arrayidx1, align 4
ret void ret void
} }
Context not available.
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @i128-const-store(i32 addrspace(0)* %out) { define amdgpu_kernel void @i128-const-store(i32 addrspace(5)* %out) {
entry: entry:
store i32 1, i32 addrspace(0)* %out, align 4 store i32 1, i32 addrspace(5)* %out, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
store i32 1, i32 addrspace(0)* %arrayidx2, align 4 store i32 1, i32 addrspace(5)* %arrayidx2, align 4
%arrayidx4 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 2 %arrayidx4 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 2
store i32 2, i32 addrspace(0)* %arrayidx4, align 4 store i32 2, i32 addrspace(5)* %arrayidx4, align 4
%arrayidx6 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 3 %arrayidx6 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 3
store i32 2, i32 addrspace(0)* %arrayidx6, align 4 store i32 2, i32 addrspace(5)* %arrayidx6, align 4
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/store-v3i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}global_store_v3i64: ; GCN-LABEL: {{^}}global_store_v3i64:
; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 ; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16

test/CodeGen/AMDGPU/store-vector-ptrs.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs< %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs< %s
; This tests for a bug that caused a crash in ; This tests for a bug that caused a crash in
; AMDGPUDAGToDAGISel::SelectMUBUFScratch() which is used for selecting ; AMDGPUDAGToDAGISel::SelectMUBUFScratch() which is used for selecting
; scratch loads and stores. ; scratch loads and stores.
; CHECK-LABEL: {{^}}store_vector_ptrs: ; CHECK-LABEL: {{^}}store_vector_ptrs:
define amdgpu_kernel void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind { define amdgpu_kernel void @store_vector_ptrs(<4 x i32 addrspace(5)*> addrspace(5)* %out, <4 x [1024 x i32] addrspace(5)*> %array) nounwind {
%p = getelementptr [1024 x i32], <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> %p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(5)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
store <4 x i32*> %p, <4 x i32*>* %out store <4 x i32 addrspace(5)*> %p, <4 x i32 addrspace(5)*> addrspace(5)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/store_typed.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck --check-prefix=CM --check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cayman < %s | FileCheck --check-prefix=CM --check-prefix=FUNC %s
; store to rat 0 ; store to rat 0
; FUNC-LABEL: {{^}}store_typed_rat0: ; FUNC-LABEL: {{^}}store_typed_rat0:

test/CodeGen/AMDGPU/structurize.ll

; RUN: llc < %s -march=r600 -mcpu=redwood -r600-ir-structurize=0 | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -r600-ir-structurize=0 | FileCheck %s
; Test case for a crash in the AMDILCFGStructurizer from a CFG like this: ; Test case for a crash in the AMDILCFGStructurizer from a CFG like this:
; ;
; entry ; entry

test/CodeGen/AMDGPU/structurize1.ll

; RUN: llc -march=r600 -mcpu=redwood -r600-if-convert=0 < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -r600-if-convert=0 < %s | FileCheck %s
; This tests for abug where the AMDILCFGStructurizer was crashing on loops ; This tests for abug where the AMDILCFGStructurizer was crashing on loops
; like this: ; like this:

test/CodeGen/AMDGPU/sub.i16.ll

; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_sub_i16: ; GCN-LABEL: {{^}}v_test_sub_i16:

test/CodeGen/AMDGPU/sub.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() readnone declare i32 @llvm.r600.read.tidig.x() readnone

test/CodeGen/AMDGPU/sub.v2i16.ll

; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_sub_v2i16: ; GCN-LABEL: {{^}}v_test_sub_v2i16:

test/CodeGen/AMDGPU/subreg-coalescer-crash.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL:{{^}}row_filter_C1_D0: ; GCN-LABEL:{{^}}row_filter_C1_D0:
define amdgpu_kernel void @row_filter_C1_D0() #0 { define amdgpu_kernel void @row_filter_C1_D0() #0 {

test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -o - %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -o - %s | FileCheck %s
; Don't crash when the use of an undefined value is only detected by the ; Don't crash when the use of an undefined value is only detected by the
; register coalescer because it is hidden with subregister insert/extract. ; register coalescer because it is hidden with subregister insert/extract.
target triple="amdgcn--" target triple="amdgcn--"

test/CodeGen/AMDGPU/subreg-eliminate-dead.ll

; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=amdgcn---amdgiz -verify-machineinstrs -o - %s | FileCheck %s
; LiveRangeEdit::eliminateDeadDef did not update LiveInterval sub ranges ; LiveRangeEdit::eliminateDeadDef did not update LiveInterval sub ranges
; properly. ; properly.

test/CodeGen/AMDGPU/swizzle-export.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck --check-prefix=EG %s
;EG: {{^}}main: ;EG: {{^}}main:
;EG: EXPORT T{{[0-9]+}}.XYXX ;EG: EXPORT T{{[0-9]+}}.XYXX

test/CodeGen/AMDGPU/syncscopes.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: name: syncscopes ; GCN-LABEL: name: syncscopes
; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out) ; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
Context not available.
; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) ; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
define void @syncscopes( define void @syncscopes(
i32 %agent, i32 %agent,
i32 addrspace(4)* %agent_out, i32* %agent_out,
i32 %workgroup, i32 %workgroup,
i32 addrspace(4)* %workgroup_out, i32* %workgroup_out,
i32 %wavefront, i32 %wavefront,
i32 addrspace(4)* %wavefront_out) { i32* %wavefront_out) {
entry: entry:
store atomic i32 %agent, i32 addrspace(4)* %agent_out syncscope("agent") seq_cst, align 4 store atomic i32 %agent, i32* %agent_out syncscope("agent") seq_cst, align 4
store atomic i32 %workgroup, i32 addrspace(4)* %workgroup_out syncscope("workgroup") seq_cst, align 4 store atomic i32 %workgroup, i32* %workgroup_out syncscope("workgroup") seq_cst, align 4
store atomic i32 %wavefront, i32 addrspace(4)* %wavefront_out syncscope("wavefront") seq_cst, align 4 store atomic i32 %wavefront, i32* %wavefront_out syncscope("wavefront") seq_cst, align 4
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/tail-call-cgp.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -codegenprepare %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa-amdgiz -codegenprepare %s | FileCheck %s
define internal fastcc void @callee(i32* nocapture %p, i32 %a) #0 { define internal fastcc void @callee(i32 addrspace(5)* nocapture %p, i32 %a) #0 {
store volatile i32 %a, i32* %p, align 4 store volatile i32 %a, i32 addrspace(5)* %p, align 4
ret void ret void
} }
Context not available.
; CHECK: tail call fastcc void @callee( ; CHECK: tail call fastcc void @callee(
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: ret void ; CHECK: ret void
define void @func_caller(i32* nocapture %p, i32 %a, i32 %b) #0 { define void @func_caller(i32 addrspace(5)* nocapture %p, i32 %a, i32 %b) #0 {
entry: entry:
%cmp = icmp eq i32 %b, 0 %cmp = icmp eq i32 %b, 0
br i1 %cmp, label %bb, label %ret br i1 %cmp, label %bb, label %ret
bb: bb:
tail call fastcc void @callee(i32* %p, i32 %a) tail call fastcc void @callee(i32 addrspace(5)* %p, i32 %a)
br label %ret br label %ret
ret: ret:
Context not available.
; CHECK-NEXT: br label %ret ; CHECK-NEXT: br label %ret
; CHECK: ret void ; CHECK: ret void
define amdgpu_kernel void @kernel_caller(i32* nocapture %p, i32 %a, i32 %b) #0 { define amdgpu_kernel void @kernel_caller(i32 addrspace(5)* nocapture %p, i32 %a, i32 %b) #0 {
entry: entry:
%cmp = icmp eq i32 %b, 0 %cmp = icmp eq i32 %b, 0
br i1 %cmp, label %bb, label %ret br i1 %cmp, label %bb, label %ret
bb: bb:
tail call fastcc void @callee(i32* %p, i32 %a) tail call fastcc void @callee(i32 addrspace(5)* %p, i32 %a)
br label %ret br label %ret
ret: ret:
Context not available.

test/CodeGen/AMDGPU/target-cpu.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
target datalayout = "A5"
declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #1 declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #1
Context not available.
; CHECK: ; LDSByteSize: 5120 ; CHECK: ; LDSByteSize: 5120
define amdgpu_kernel void @promote_alloca_enabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #5 { define amdgpu_kernel void @promote_alloca_enabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #5 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
%load = load i32, i32* %arrayidx1 %load = load i32, i32 addrspace(5)* %arrayidx1
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.
; CHECK: ScratchSize: 24 ; CHECK: ScratchSize: 24
define amdgpu_kernel void @promote_alloca_disabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #6 { define amdgpu_kernel void @promote_alloca_disabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #6 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
%load = load i32, i32* %arrayidx1 %load = load i32, i32 addrspace(5)* %arrayidx1
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/tex-clause-antidep.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK: TEX ;CHECK: TEX
;CHECK-NEXT: ALU ;CHECK-NEXT: ALU

test/CodeGen/AMDGPU/texture-input-merge.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
;CHECK-NOT: MOV ;CHECK-NOT: MOV

test/CodeGen/AMDGPU/trap.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-TRAP %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-TRAP %s
; RUN: llc -mtriple=amdgcn--amdhsa -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
; enable trap handler feature ; enable trap handler feature
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
; disable trap handler feature ; disable trap handler feature
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d-amdgiz -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
declare void @llvm.trap() #0 declare void @llvm.trap() #0
declare void @llvm.debugtrap() #0 declare void @llvm.debugtrap() #0

test/CodeGen/AMDGPU/trunc-bitcast-vector.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck --check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
; CHECK-LABEL: {{^}}trunc_i64_bitcast_v2i32: ; CHECK-LABEL: {{^}}trunc_i64_bitcast_v2i32:
; CHECK: buffer_load_dword v ; CHECK: buffer_load_dword v

test/CodeGen/AMDGPU/trunc-cmp-constant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}global_truncstore_f64_to_f16: ; GCN-LABEL: {{^}}global_truncstore_f64_to_f16:
; GCN: s_endpgm ; GCN: s_endpgm

test/CodeGen/AMDGPU/trunc-store-i1.ll

; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}global_truncstore_i32_to_i1: ; SI-LABEL: {{^}}global_truncstore_i32_to_i1:

test/CodeGen/AMDGPU/trunc-store.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}truncstore_arg_v16i32_to_v16i8: ; FUNC-LABEL: {{^}}truncstore_arg_v16i32_to_v16i8:
; SI: buffer_store_dwordx4 ; SI: buffer_store_dwordx4

test/CodeGen/AMDGPU/trunc.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone declare i32 @llvm.r600.read.tidig.x() nounwind readnone

test/CodeGen/AMDGPU/tti-unroll-prefs.ll

; RUN: opt -loop-unroll -S -mtriple=amdgcn-- -mcpu=tahiti %s | FileCheck %s ; RUN: opt -loop-unroll -S -mtriple=amdgcn---amdgiz -mcpu=tahiti %s | FileCheck %s
; This IR comes from this OpenCL C code: ; This IR comes from this OpenCL C code:
; ;

test/CodeGen/AMDGPU/uaddo.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s
; FUNC-LABEL: {{^}}s_uaddo_i64_zext: ; FUNC-LABEL: {{^}}s_uaddo_i64_zext:
; GCN: s_add_u32 ; GCN: s_add_u32

test/CodeGen/AMDGPU/udiv.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -mattr=-fp32-denormals < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -mattr=-fp32-denormals < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=+fp32-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}udiv_i32: ; FUNC-LABEL: {{^}}udiv_i32:
; EG-NOT: SETGE_INT ; EG-NOT: SETGE_INT

test/CodeGen/AMDGPU/udivrem.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_udivrem: ; FUNC-LABEL: {{^}}test_udivrem:
; EG: RECIP_UINT ; EG: RECIP_UINT

test/CodeGen/AMDGPU/udivrem24.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}udiv24_i8: ; FUNC-LABEL: {{^}}udiv24_i8:
; SI: v_cvt_f32_ubyte ; SI: v_cvt_f32_ubyte

test/CodeGen/AMDGPU/udivrem64.ll

;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s
;RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s
;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s ;RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
;FUNC-LABEL: {{^}}test_udiv: ;FUNC-LABEL: {{^}}test_udiv:
;EG: RECIP_UINT ;EG: RECIP_UINT

test/CodeGen/AMDGPU/uint_to_fp.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/uint_to_fp.i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
; FIXME: This should be merged with uint_to_fp.ll, but s_uint_to_fp_v2i64 crashes on r600 ; FIXME: This should be merged with uint_to_fp.ll, but s_uint_to_fp_v2i64 crashes on r600

test/CodeGen/AMDGPU/uint_to_fp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}s_uint_to_fp_i32_to_f32: ; FUNC-LABEL: {{^}}s_uint_to_fp_i32_to_f32:
; SI: v_cvt_f32_u32_e32 ; SI: v_cvt_f32_u32_e32

test/CodeGen/AMDGPU/uitofp.f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}uitofp_i16_to_f16 ; GCN-LABEL: {{^}}uitofp_i16_to_f16
; GCN: buffer_load_ushort v[[A_I16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_I16:[0-9]+]]

test/CodeGen/AMDGPU/umed3.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0

test/CodeGen/AMDGPU/unaligned-load-store.ll

; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s
; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=+unaligned-buffer-access -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=UNALIGNED %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -mattr=+unaligned-buffer-access -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=UNALIGNED %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s
; SI-LABEL: {{^}}local_unaligned_load_store_i16: ; SI-LABEL: {{^}}local_unaligned_load_store_i16:
; SI: ds_read_u8 ; SI: ds_read_u8

test/CodeGen/AMDGPU/undefined-subreg-liverange.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; We may have subregister live ranges that are undefined on some paths. The ; We may have subregister live ranges that are undefined on some paths. The
; verifier should not complain about this. ; verifier should not complain about this.

test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll

; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s ; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s ; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
; XUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s ; XUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s
; SI hits an assertion at -O0, evergreen hits a not implemented unreachable. ; SI hits an assertion at -O0, evergreen hits a not implemented unreachable.

test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; This used to raise an assertion due to how the choice between uniform and ; This used to raise an assertion due to how the choice between uniform and
; non-uniform branches was determined. ; non-uniform branches was determined.

test/CodeGen/AMDGPU/uniform-cfg.ll

; RUN: llc -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}uniform_if_scc: ; GCN-LABEL: {{^}}uniform_if_scc:
; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0

test/CodeGen/AMDGPU/uniform-crash.ll

; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}icmp_2_users: ; GCN-LABEL: {{^}}icmp_2_users:
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1

test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll

; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde < %s | FileCheck %s
; Test a simple uniform loop that lives inside non-uniform control flow. ; Test a simple uniform loop that lives inside non-uniform control flow.

test/CodeGen/AMDGPU/unify-metadata.ll

; RUN: opt -mtriple=amdgcn--amdhsa -amdgpu-unify-metadata -S < %s | FileCheck -check-prefix=ALL %s ; RUN: opt -mtriple=amdgcn--amdhsa-amdgiz -amdgpu-unify-metadata -S < %s | FileCheck -check-prefix=ALL %s
; This test check that we have a singe metadata value after linking several ; This test check that we have a singe metadata value after linking several
; modules for records such as opencl.ocl.version, llvm.ident and similar. ; modules for records such as opencl.ocl.version, llvm.ident and similar.

test/CodeGen/AMDGPU/unigine-liveness-crash.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck %s
; ;
; This test used to crash with the following assertion: ; This test used to crash with the following assertion:
; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed. ; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval addrspace(5)*, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval addrspace(5)*, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.
; ;
; This was related to incorrectly calculating subregister live ranges ; This was related to incorrectly calculating subregister live ranges
; (i.e. live interval subranges): subregister defs are not uses for that ; (i.e. live interval subranges): subregister defs are not uses for that

test/CodeGen/AMDGPU/unroll.ll

; RUN: opt -mtriple=amdgcn-- -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s ; RUN: opt -mtriple=amdgcn---amdgiz -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s
; RUN: opt -mtriple=r600-- -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s ; RUN: opt -mtriple=r600---amdgiz -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s
target datalayout = "A5"
; This test contains a simple loop that initializes an array declared in ; This test contains a simple loop that initializes an array declared in
Context not available.
; CHECK: store i32 5, i32 addrspace(1)* %out ; CHECK: store i32 5, i32 addrspace(1)* %out
define amdgpu_kernel void @private_memory(i32 addrspace(1)* %out) { define amdgpu_kernel void @private_memory(i32 addrspace(1)* %out) {
entry: entry:
%0 = alloca [32 x i32] %0 = alloca [32 x i32], addrspace(5)
br label %loop.header br label %loop.header
loop.header: loop.header:
Context not available.
br label %loop.body br label %loop.body
loop.body: loop.body:
%ptr = getelementptr [32 x i32], [32 x i32]* %0, i32 0, i32 %counter %ptr = getelementptr [32 x i32], [32 x i32] addrspace(5)* %0, i32 0, i32 %counter
store i32 %counter, i32* %ptr store i32 %counter, i32 addrspace(5)* %ptr
br label %loop.inc br label %loop.inc
loop.inc: loop.inc:
Context not available.
br i1 %1, label %exit, label %loop.header br i1 %1, label %exit, label %loop.header
exit: exit:
%2 = getelementptr [32 x i32], [32 x i32]* %0, i32 0, i32 5 %2 = getelementptr [32 x i32], [32 x i32] addrspace(5)* %0, i32 0, i32 5
%3 = load i32, i32* %2 %3 = load i32, i32 addrspace(5)* %2
store i32 %3, i32 addrspace(1)* %out store i32 %3, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.
; CHECK-NEXT: getelementptr ; CHECK-NEXT: getelementptr
; CHECK-NEXT: store ; CHECK-NEXT: store
; CHECK-NOT: br ; CHECK-NOT: br
define amdgpu_kernel void @unroll_for_if(i32* %a) { define amdgpu_kernel void @unroll_for_if(i32 addrspace(5)* %a) {
entry: entry:
br label %for.body br label %for.body
Context not available.
if.then: ; preds = %for.body if.then: ; preds = %for.body
%0 = sext i32 %i1 to i64 %0 = sext i32 %i1 to i64
%arrayidx = getelementptr inbounds i32, i32* %a, i64 %0 %arrayidx = getelementptr inbounds i32, i32 addrspace(5)* %a, i64 %0
store i32 0, i32* %arrayidx, align 4 store i32 0, i32 addrspace(5)* %arrayidx, align 4
br label %for.inc br label %for.inc
for.inc: ; preds = %for.body, %if.then for.inc: ; preds = %for.body, %if.then
Context not available.

test/CodeGen/AMDGPU/unsupported-cc.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; These tests are for condition codes that are not supported by the hardware ; These tests are for condition codes that are not supported by the hardware

test/CodeGen/AMDGPU/urem.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; The code generated by urem is long and complex and may frequently ; The code generated by urem is long and complex and may frequently
; change. The goal of this test is to make sure the ISel doesn't fail ; change. The goal of this test is to make sure the ISel doesn't fail

test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
declare float @llvm.fma.f32(float, float, float) #1 declare float @llvm.fma.f32(float, float, float) #1
declare double @llvm.fma.f64(double, double, double) #1 declare double @llvm.fma.f64(double, double, double) #1

test/CodeGen/AMDGPU/usubo.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s
; FUNC-LABEL: {{^}}s_usubo_i64_zext: ; FUNC-LABEL: {{^}}s_usubo_i64_zext:
; GCN: s_sub_u32 ; GCN: s_sub_u32

test/CodeGen/AMDGPU/v1i64-kernel-arg.ll

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck %s
; CHECK-LABEL: {{^}}kernel_arg_i64: ; CHECK-LABEL: {{^}}kernel_arg_i64:
define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind { define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind {

test/CodeGen/AMDGPU/v_cndmask.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1

test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.cvt.pk.u8.f32(float, i32, i32) #0 declare i32 @llvm.amdgcn.cvt.pk.u8.f32(float, i32, i32) #0

test/CodeGen/AMDGPU/v_mac.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-FLUSH -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-FLUSH -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-DENORM -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-DENORM -check-prefix=GCN %s
; GCN-LABEL: {{^}}mac_vvv: ; GCN-LABEL: {{^}}mac_vvv:
; GCN: buffer_load_dword [[A:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}} ; GCN: buffer_load_dword [[A:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}}

test/CodeGen/AMDGPU/v_mac_f16.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}mac_f16: ; GCN-LABEL: {{^}}mac_f16:
; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]] ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/v_madak_f16.ll

; RUN: llc -march=amdgcn -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}madak_f16 ; GCN-LABEL: {{^}}madak_f16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]

test/CodeGen/AMDGPU/valu-i1.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

test/CodeGen/AMDGPU/vector-extract-insert.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Test that when extracting the same unknown vector index from an ; Test that when extracting the same unknown vector index from an
; insertelement the dynamic indexing is folded away. ; insertelement the dynamic indexing is folded away.

test/CodeGen/AMDGPU/vectorize-global-local.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
; CHECK-DAG: flat_load_dwordx4 ; CHECK-DAG: flat_load_dwordx4
; CHECK-DAG: flat_load_dwordx4 ; CHECK-DAG: flat_load_dwordx4
; CHECK-DAG: flat_load_dwordx4 ; CHECK-DAG: flat_load_dwordx4

test/CodeGen/AMDGPU/vertex-fetch-encoding.ll

; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cypress | FileCheck --check-prefix=EG --check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -show-mc-encoding -mcpu=cypress | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=EG --check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM --check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM --check-prefix=FUNC %s
; FUNC-LABEL: {{^}}vtx_fetch32: ; FUNC-LABEL: {{^}}vtx_fetch32:
; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00

test/CodeGen/AMDGPU/vi-removed-intrinsics.ll

; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: error: foo.cl:1:42: in function rsq_legacy_f32 void (float addrspace(1)*, float): intrinsic not supported on subtarget ; ERROR: error: foo.cl:1:42: in function rsq_legacy_f32 void (float addrspace(1)*, float): intrinsic not supported on subtarget

test/CodeGen/AMDGPU/vop-shrink.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; Test that we correctly commute a sub instruction ; Test that we correctly commute a sub instruction
; FUNC-LABEL: {{^}}sub_rev: ; FUNC-LABEL: {{^}}sub_rev:

test/CodeGen/AMDGPU/vselect.ll

;RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=VI --check-prefix=FUNC %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=VI --check-prefix=FUNC %s
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_select_v2i32: ; FUNC-LABEL: {{^}}test_select_v2i32:

test/CodeGen/AMDGPU/vselect64.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; XXX: Merge this test into vselect.ll once SI supports 64-bit select. ; XXX: Merge this test into vselect.ll once SI supports 64-bit select.
; CHECK-LABEL: {{^}}test_select_v4i64: ; CHECK-LABEL: {{^}}test_select_v4i64:

test/CodeGen/AMDGPU/vtx-fetch-branch.ll

; RUN: llc -march=r600 -mcpu=redwood %s -o - | FileCheck %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood %s -o - | FileCheck %s
; This tests for a bug where vertex fetch clauses right before an ENDIF ; This tests for a bug where vertex fetch clauses right before an ENDIF
; instruction where being emitted after the ENDIF. We were using ALU_POP_AFTER ; instruction where being emitted after the ENDIF. We were using ALU_POP_AFTER

test/CodeGen/AMDGPU/vtx-schedule.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s
; This test is for a scheduler bug where VTX_READ instructions that used ; This test is for a scheduler bug where VTX_READ instructions that used
; the result of another VTX_READ instruction were being grouped in the ; the result of another VTX_READ instruction were being grouped in the

test/CodeGen/AMDGPU/wait.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -march=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; The ilpmax scheduler is used for the second test to get the ordering we want for the test. ; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
; DEFAULT-LABEL: {{^}}main: ; DEFAULT-LABEL: {{^}}main:

test/CodeGen/AMDGPU/waitcnt-flat.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; If flat_store_dword and flat_load_dword use different registers for the data ; If flat_store_dword and flat_load_dword use different registers for the data
; operand, this test is not broken. It just means it is no longer testing ; operand, this test is not broken. It just means it is no longer testing
Context not available.
; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]] ; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]]
; XGCN: s_waitcnt vmcnt(0) lgkmcnt(0) ; XGCN: s_waitcnt vmcnt(0) lgkmcnt(0)
; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}] ; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @test(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @test(i32* %out, i32 %in) {
store volatile i32 0, i32 addrspace(4)* %out store volatile i32 0, i32* %out
%val = load volatile i32, i32 addrspace(4)* %out %val = load volatile i32, i32* %out
ret void ret void
} }
; Make sure lgkmcnt isn't used for global_* instructions ; Make sure lgkmcnt isn't used for global_ addrspace(5)* instructions
; GCN-LABEL: {{^}}test_waitcnt_type_flat_global: ; GCN-LABEL: {{^}}test_waitcnt_type_flat_global:
; GFX9: global_load_dword [[LD:v[0-9]+]] ; GFX9: global_load_dword [[LD:v[0-9]+]]
; GFX9-NEXT: s_waitcnt vmcnt(0){{$}} ; GFX9-NEXT: s_waitcnt vmcnt(0){{$}}
Context not available.

test/CodeGen/AMDGPU/waitcnt-looptest.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=GCN %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=GCN %s
; Check that the waitcnt insertion algorithm correctly propagates wait counts ; Check that the waitcnt insertion algorithm correctly propagates wait counts
; from before a loop to the loop header. ; from before a loop to the loop header.
Context not available.
define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture %arg) local_unnamed_addr #0 { define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture %arg) local_unnamed_addr #0 {
bb: bb:
store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> addrspace(4)* bitcast (float addrspace(4)* getelementptr ([100 x float], [100 x float] addrspace(4)* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float] addrspace(4)*), i64 0, i64 4) to <2 x float> addrspace(4)*), align 4 store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4
store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> addrspace(4)* bitcast (float addrspace(4)* getelementptr ([100 x float], [100 x float] addrspace(4)* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float] addrspace(4)*), i64 0, i64 4) to <2 x float> addrspace(4)*), align 4 store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4
br label %bb18 br label %bb18
bb1: ; preds = %bb18 bb1: ; preds = %bb18
Context not available.

test/CodeGen/AMDGPU/widen-vselect-and-mask.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to ; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to
; create vselects with i64 condition masks. ; create vselects with i64 condition masks.

test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll

; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -amdgpu-codegenprepare < %s | FileCheck -check-prefix=OPT %s
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0

test/CodeGen/AMDGPU/wqm.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=VI %s
target datalayout = "A5"
; Check that WQM isn't triggered by image load/store intrinsics. ; Check that WQM isn't triggered by image load/store intrinsics.
; ;
Context not available.
; CHECK: buffer_store_dwordx4 ; CHECK: buffer_store_dwordx4
define amdgpu_ps void @test_alloca(float %data, i32 %a, i32 %idx) nounwind { define amdgpu_ps void @test_alloca(float %data, i32 %a, i32 %idx) nounwind {
entry: entry:
%array = alloca [32 x i32], align 4 %array = alloca [32 x i32], align 4, addrspace(5)
call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
%s.gep = getelementptr [32 x i32], [32 x i32]* %array, i32 0, i32 0 %s.gep = getelementptr [32 x i32], [32 x i32] addrspace(5)* %array, i32 0, i32 0
store volatile i32 %a, i32* %s.gep, align 4 store volatile i32 %a, i32 addrspace(5)* %s.gep, align 4
call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 1, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 1, i32 0, i1 0, i1 0)
%c.gep = getelementptr [32 x i32], [32 x i32]* %array, i32 0, i32 %idx %c.gep = getelementptr [32 x i32], [32 x i32] addrspace(5)* %array, i32 0, i32 %idx
%c = load i32, i32* %c.gep, align 4 %c = load i32, i32 addrspace(5)* %c.gep, align 4
%c.bc = bitcast i32 %c to float %c.bc = bitcast i32 %c to float
%t = call <4 x float> @llvm.amdgcn.image.sample.v4f32.f32.v8i32(float %c.bc, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #0 %t = call <4 x float> @llvm.amdgcn.image.sample.v4f32.f32.v8i32(float %c.bc, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #0
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %t, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %t, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
Context not available.

test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll

; XFAIL: * ; XFAIL: *
; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -verify-machineinstrs < %s
; write_register doesn't prevent us from illegally trying to write a ; write_register doesn't prevent us from illegally trying to write a
; vgpr value into a scalar register, but I don't think there's much we ; vgpr value into a scalar register, but I don't think there's much we

test/CodeGen/AMDGPU/write_register.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s
declare void @llvm.write_register.i32(metadata, i32) #0 declare void @llvm.write_register.i32(metadata, i32) #0
declare void @llvm.write_register.i64(metadata, i64) #0 declare void @llvm.write_register.i64(metadata, i64) #0

test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll

; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s ; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600---amdgiz < %s | FileCheck %s
; We want all MULLO_INT inst to be last in their instruction group ; We want all MULLO_INT inst to be last in their instruction group
;CHECK: {{^}}fill3d: ;CHECK: {{^}}fill3d:

test/CodeGen/AMDGPU/xfail.r600.bitcast.ll

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; XFAIL: * ; XFAIL: *
; This is the failing part of the r600 bitacts tests ; This is the failing part of the r600 bitacts tests

test/CodeGen/AMDGPU/xnor.ll

; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
; RUN: llc -march=amdgcn -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX800 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX800 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
; GCN-LABEL: {{^}}scalar_xnor_i32_one_use ; GCN-LABEL: {{^}}scalar_xnor_i32_one_use
; GCN: s_xnor_b32 ; GCN: s_xnor_b32

test/CodeGen/AMDGPU/xor.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}xor_v2i32: ; FUNC-LABEL: {{^}}xor_v2i32:

test/CodeGen/AMDGPU/zero_extend.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck %s --check-prefix=SI
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI ; RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 ; RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -mcpu=redwood | FileCheck %s --check-prefix=R600
; R600: {{^}}s_mad_zext_i32_to_i64: ; R600: {{^}}s_mad_zext_i32_to_i64:
; R600: MEM_RAT_CACHELESS STORE_RAW ; R600: MEM_RAT_CACHELESS STORE_RAW

test/CodeGen/AMDGPU/zext-i64-bit-operand.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}zext_or_operand_i64: ; GCN-LABEL: {{^}}zext_or_operand_i64:
; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}

test/CodeGen/AMDGPU/zext-lid.ll

; RUN: llc -march=amdgcn < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz < %s | FileCheck %s
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn---amdgiz -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s
; CHECK-NOT: and_b32 ; CHECK-NOT: and_b32