LLD/ELF: Allow targets to set e_flags

[t-tye]

ELF/Arch/MipsArchTree.cpp

284 ↗

(On Diff #119697)

Would it be better to just rename this calcEFlags to match how the other targets are now?

[ruiu]

ELF/Arch/MipsArchTree.cpp

284 ↗

(On Diff #119697)

Yes, please just rename it.

[kzhuravl]

ELF/Arch/MipsArchTree.cpp

284 ↗

(On Diff #119697)

Could you elaborate on what needs renaming?

Reasons why I left it as is:

• Mips class derived from TargetInfo is in anonymous namespace in Mips.cpp, so inaccessible in MipsArchTree.cpp
• calcMipsEFlags is using few functions (e.g. checkFlags) that are static, so inaccessible in Mips.cpp

I was thinking of merging Mips.cpp and MipsArchTree.cpp into one file, but not sure if it is the right choice (I do not know why it was done this way in the first place).

[ruiu]

LGTM, but please apply clang-format-diff before committing. Thanks!

ELF/Arch/MipsArchTree.cpp

284 ↗

(On Diff #119697)

Ah, got it. I wasn't aware that the function is in another file. I'm fine with the current code.

[kzhuravl]

In D39139#904673, @ruiu wrote:

LGTM, but please apply clang-format-diff before committing. Thanks!

Done, thanks.

lld/trunk/ELF/Arch/ARM.cpp

 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class ARM final : public TargetInfo {
 public:
   ARM();
+  uint32_t calcEFlags() const override;
   RelExpr getRelExpr(RelType Type, const SymbolBody &S,
                      const uint8_t *Loc) const override;
   bool isPicRel(RelType Type) const override;
   RelType getDynRel(RelType Type) const override;
   int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
ARM::ARM() {
   PltEntrySize = 16;
   PltHeaderSize = 20;
   TrapInstr = 0xd4d4d4d4;
   // ARM uses Variant 1 TLS
   TcbSize = 8;
   NeedsThunks = true;
 }
 
+uint32_t ARM::calcEFlags() const {
+  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
+  // but we don't have any firm guarantees of conformance. Linux AArch64
+  // kernels (as of 2016) require an EABI version to be set.
+  return EF_ARM_EABI_VER5;
+}
+
 RelExpr ARM::getRelExpr(RelType Type, const SymbolBody &S,
                         const uint8_t *Loc) const {
   switch (Type) {
   case R_ARM_THM_JUMP11:
     return R_PC;
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:

lld/trunk/ELF/Arch/Mips.cpp

 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 template <class ELFT> class MIPS final : public TargetInfo {
 public:
   MIPS();
+  uint32_t calcEFlags() const override;
   RelExpr getRelExpr(RelType Type, const SymbolBody &S,
                      const uint8_t *Loc) const override;
   int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
   bool isPicRel(RelType Type) const override;
   RelType getDynRel(RelType Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
template <class ELFT> MIPS<ELFT>::MIPS() {
   } else {
     RelativeRel = R_MIPS_REL32;
     TlsGotRel = R_MIPS_TLS_TPREL32;
     TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
     TlsOffsetRel = R_MIPS_TLS_DTPREL32;
   }
 }
 
+template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
+  return calcMipsEFlags<ELFT>();
+}
+
 template <class ELFT>
 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const SymbolBody &S,
                                const uint8_t *Loc) const {
   // See comment in the calculateMipsRelChain.
   if (ELFT::Is64Bits || Config->MipsN32Abi)
     Type &= 0xff;
 
   switch (Type) {

 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
                                    uint8_t Shift) {
   uint16_t Instr = read16<E>(Loc);
   uint16_t Mask = 0xffff >> (16 - BitsSize);
   uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
   write16<E>(Loc, Data);
 }
 
-static bool isMicroMips() { return Config->MipsEFlags & EF_MIPS_MICROMIPS; }
+static bool isMicroMips() { return Config->EFlags & EF_MIPS_MICROMIPS; }
 
 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
   const endianness E = ELFT::TargetEndianness;
   if (isMicroMips()) {
     uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
     uint64_t Plt = In<ELFT>::Plt->getVA();
     // Overwrite trap instructions written by Writer::writeTrapInstr.
     memset(Buf, 0, PltHeaderSize);

lld/trunk/ELF/Arch/MipsArchTree.cpp

bool elf::isMipsN32Abi(const InputFile *F) {
   case ELF64BEKind:
     return isN32Abi<ELF64BE>(F);
   default:
     llvm_unreachable("unknown Config->EKind");
   }
 }
 
 bool elf::isMipsR6() {
-  uint32_t Arch = Config->MipsEFlags & EF_MIPS_ARCH;
+  uint32_t Arch = Config->EFlags & EF_MIPS_ARCH;
   return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
 }
 
 template uint32_t elf::calcMipsEFlags<ELF32LE>();
 template uint32_t elf::calcMipsEFlags<ELF32BE>();
 template uint32_t elf::calcMipsEFlags<ELF64LE>();
 template uint32_t elf::calcMipsEFlags<ELF64BE>();

lld/trunk/ELF/Config.h

struct Configuration {
   // not in various places.
   //
   // (Note that MIPS64EL is not a typo for MIPS64LE. This is the official
   // name whatever that means. A fun hypothesis is that "EL" is short for
   // little-endian written in the little-endian order, but I don't know
   // if that's true.)
   bool IsMips64EL;
 
-  // Holds set of ELF header flags for MIPS targets. The set calculated
-  // by the `elf::calcMipsEFlags` function and cached in this field. For
-  // the calculation we iterate over all input object files and combine
-  // their ELF flags.
-  uint32_t MipsEFlags = 0;
+  // Holds set of ELF header flags for the target.
+  uint32_t EFlags = 0;
 
   // The ELF spec defines two types of relocation table entries, RELA and
   // REL. RELA is a triplet of (offset, info, addend) while REL is a
   // tuple of (offset, info). Addends for REL are implicit and read from
   // the location where the relocations are applied. So, REL is more
   // compact than RELA but requires a bit of more work to process.
   //
   // (From the linker writer's view, this distinction is not necessary.

lld/trunk/ELF/Driver.cpp

template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
   for (InputFile *F : ObjectFiles)
     for (InputSectionBase *S : F->getSections())
       if (S && S != &InputSection::Discarded)
         InputSections.push_back(S);
   for (BinaryFile *F : BinaryFiles)
     for (InputSectionBase *S : F->getSections())
       InputSections.push_back(cast<InputSection>(S));
 
-  if (Config->EMachine == EM_MIPS)
-    Config->MipsEFlags = calcMipsEFlags<ELFT>();
+  Config->EFlags = Target->calcEFlags();
 
   // This adds a .comment section containing a version string. We have to add it
   // before decompressAndMergeSections because the .comment section is a
   // mergeable section.
   if (!Config->Relocatable)
     InputSections.push_back(createCommentSection<ELFT>());
 
   // Create a .bss section for each common symbol and then replace the common

lld/trunk/ELF/Target.h

 std::string toString(elf::RelType Type);
 
 namespace elf {
 class InputFile;
 class SymbolBody;
 
 class TargetInfo {
 public:
+  virtual uint32_t calcEFlags() const { return 0; }
   virtual bool isPicRel(RelType Type) const { return true; }
   virtual RelType getDynRel(RelType Type) const { return Type; }
   virtual void writeGotPltHeader(uint8_t *Buf) const {}
   virtual void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {};
   virtual void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const;
   virtual int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const;
 
   // If lazy binding is supported, the first entry of the PLT has code

lld/trunk/ELF/Writer.cpp

template <class ELFT> void Writer<ELFT>::writeHeader() {
   EHdr->e_ident[EI_DATA] = Config->IsLE ? ELFDATA2LSB : ELFDATA2MSB;
   EHdr->e_ident[EI_VERSION] = EV_CURRENT;
   EHdr->e_ident[EI_OSABI] = Config->OSABI;
   EHdr->e_type = getELFType();
   EHdr->e_machine = Config->EMachine;
   EHdr->e_version = EV_CURRENT;
   EHdr->e_entry = getEntryAddr();
   EHdr->e_shoff = SectionHeaderOff;
+  EHdr->e_flags = Config->EFlags;
   EHdr->e_ehsize = sizeof(Elf_Ehdr);
   EHdr->e_phnum = Phdrs.size();
   EHdr->e_shentsize = sizeof(Elf_Shdr);
   EHdr->e_shnum = OutputSections.size() + 1;
   EHdr->e_shstrndx = InX::ShStrTab->getParent()->SectionIndex;
 
-  if (Config->EMachine == EM_ARM)
-    // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
-    // but we don't have any firm guarantees of conformance. Linux AArch64
-    // kernels (as of 2016) require an EABI version to be set.
-    EHdr->e_flags = EF_ARM_EABI_VER5;
-  else if (Config->EMachine == EM_MIPS)
-    EHdr->e_flags = Config->MipsEFlags;
-
   if (!Config->Relocatable) {
     EHdr->e_phoff = sizeof(Elf_Ehdr);
     EHdr->e_phentsize = sizeof(Elf_Phdr);
   }
 
   // Write the program header table.
   auto *HBuf = reinterpret_cast<Elf_Phdr *>(Buf + EHdr->e_phoff);
   for (PhdrEntry *P : Phdrs) {