AMDGPU: Fix failure to select branch with optnone

[arsenm]

Summary

opt-bisect/optnone disable the AMDGPUUniformAnnotateValues pass.
The heuristic in the custom selector for brcond deferred the
branch uniformity check to the pattern, which would fail.

[arsenm]

Right version of test

[rampitec]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

1647

Why cannot we use condition register w/o a copy?

[arsenm]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

1647

It needs to be associated with a chain and glue. You don't know if the condition is using vcc already, like the condition is probably an unknown SGPR right ow.

I'm actually surprised this worked with SCC, since I think this needs to use the glued def without the copy but it seems to do the right thing.

[rampitec]

LGTM

[arsenm]

r315360

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
   SDValue Cond = N->getOperand(1);
 
   if (Cond.isUndef()) {
     CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
                          N->getOperand(2), N->getOperand(0));
     return;
   }
 
-  if (isCBranchSCC(N)) {
-    // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
-    SelectCode(N);
-    return;
-  }
-
+  bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N);
+  unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ;
+  unsigned CondReg = UseSCCBr ? AMDGPU::SCC : AMDGPU::VCC;
   SDLoc SL(N);
 
-  SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond);
-  CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
+  SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
+  CurDAG->SelectNodeTo(N, BrOp, MVT::Other,
                        N->getOperand(2), // Basic Block
                        VCC.getValue(0));
 }
 
 void AMDGPUDAGToDAGISel::SelectFMAD(SDNode *N) {
   MVT VT = N->getSimpleValueType(0);
   if (VT != MVT::f32 || !Subtarget->hasMadMixInsts()) {
     SelectCode(N);

lib/Target/AMDGPU/SIInstrInfo.td

for (SDNode *Use : N->uses()) {
 
     unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
     if (Reg != AMDGPU::SCC)
       return false;
   }
   return true;
 }]>;
 
-def si_uniform_br : PatFrag <
-  (ops node:$cond, node:$bb), (brcond node:$cond, node:$bb), [{
-  return isUniformBr(N);
-}]>;
-
-def si_uniform_br_scc : PatFrag <
-  (ops node:$cond, node:$bb), (si_uniform_br node:$cond, node:$bb), [{
-  return isCBranchSCC(N);
-}]>;
-
 def lshr_rev : PatFrag <
   (ops node:$src1, node:$src0),
   (srl $src0, $src1)
 >;
 
 def ashr_rev : PatFrag <
   (ops node:$src1, node:$src0),
   (sra $src0, $src1)

lib/Target/AMDGPU/SOPInstructions.td

 
 let Uses = [SCC] in {
 def S_CBRANCH_SCC0 : SOPP <
   0x00000004, (ins sopp_brtarget:$simm16),
   "s_cbranch_scc0 $simm16"
 >;
 def S_CBRANCH_SCC1 : SOPP <
   0x00000005, (ins sopp_brtarget:$simm16),
-  "s_cbranch_scc1 $simm16",
-  [(si_uniform_br_scc SCC, bb:$simm16)]
+  "s_cbranch_scc1 $simm16"
 >;
 } // End Uses = [SCC]
 
 let Uses = [VCC] in {
 def S_CBRANCH_VCCZ : SOPP <
   0x00000006, (ins sopp_brtarget:$simm16),
   "s_cbranch_vccz $simm16"
 >;

test/CodeGen/AMDGPU/control-flow-optnone.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
+; to be uniform during instruction selection. The custom selection for
+; brcond was not checking if the branch was uniform, relying on the
+; selection pattern to check that. That would fail, so then the branch
+; would fail to select.
+
+; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
+; GCN: s_branch
+
+; GCN-DAG: v_cmp_lt_i32
+; GCN-DAG: v_cmp_gt_i32
+; GCN: s_and_b64
+; GCN: s_and_saveexec_b64
+
+; GCN: s_or_b64 exec, exec
+; GCN: v_cmp_eq_u32
+; GCN: s_cbranch_vccnz
+; GCN-NEXT: s_branch
+define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp3 = zext i32 %tmp to i64
+  %tmp5 = add i64 %tmp3, undef
+  %tmp6 = trunc i64 %tmp5 to i32
+  %tmp7 = mul nsw i32 %tmp6, %arg2
+  br label %bb8
+
+bb8.loopexit:                                     ; preds = %bb14
+  br label %bb8
+
+bb8:                                              ; preds = %bb8.loopexit, %bb
+  br label %bb9
+
+bb9:                                              ; preds = %bb14, %bb8
+  %tmp10 = icmp slt i32 %tmp7, %arg1
+  %tmp11 = icmp sgt i32 %arg, 0
+  %tmp12 = and i1 %tmp10, %tmp11
+  br i1 %tmp12, label %bb13, label %bb14
+
+bb13:                                             ; preds = %bb9
+  store volatile i32 0, i32 addrspace(1)* undef, align 4
+  br label %bb14
+
+bb14:                                             ; preds = %bb13, %bb9
+  %tmp15 = icmp eq i32 %arg2, 1
+  br i1 %tmp15, label %bb8.loopexit, label %bb9
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+attributes #0 = { nounwind optnone noinline }
+attributes #1 = { nounwind readnone speculatable }