Eliminate ftrunc if source is know to be rounded

[hfinkel]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10705 ↗

(On Diff #117204)

Is there any way we can generalize this? All of the operations listed here are like ftrunc in this regard (they're idempotent for integer inputs).

[rampitec]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10705 ↗

(On Diff #117204)

I did not find any function to tell if a value is rounded to integer. Thinking about that function it might be non-trivial, given that we might have denorms. So I decided to go with opcodes which guarantied to produce integral value no matter what. A function like that most likely shall also check for these opcodes first before taking more complex analysis.

[b-sumner]

We could potentially update visitCEIL and visitFLOOR as well, and use the same opcode test in each, although I don't think such combinations are very likely.

[rampitec]

In D38421#884908, @b-sumner wrote:

We could potentially update visitCEIL and visitFLOOR as well, and use the same opcode test in each, although I don't think such combinations are very likely.

Right, that is possible but unlikely to happen. The current situation we have is due to the fact we have (fptosi (rint x)). I.e. we have rounded value but now we need to get integer from rounded float, and trunc is a part of that fptosi expansion.

[hfinkel]

In D38421#884918, @rampitec wrote:

In D38421#884908, @b-sumner wrote:

We could potentially update visitCEIL and visitFLOOR as well, and use the same opcode test in each, although I don't think such combinations are very likely.

Right, that is possible but unlikely to happen. The current situation we have is due to the fact we have (fptosi (rint x)). I.e. we have rounded value but now we need to get integer from rounded float, and trunc is a part of that fptosi expansion.

Okay. That makes sense. Please add a comment noting that here (i.e. that trunc is part of the fpto[su]i expansions on some targets, so we're likely to generate this combination).

[rampitec]

Added comment as requested.

[hfinkel]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
   // fold (ftrunc c1) -> ftrunc(c1)
   if (isConstantFPBuildVectorOrConstantFP(N0))
     return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
 
+  // fold ftrunc (known rounded int x) -> x
+  // ftrunc is a part of fptosi/fptoui expansion on some targets, so this is
+  // likely to be generated to extract integer from a rounded floating value.
+  switch (N0.getOpcode()) {
+  default: break;
+  case ISD::FRINT:
+  case ISD::FTRUNC:
+  case ISD::FNEARBYINT:
+  case ISD::FFLOOR:
+  case ISD::FCEIL:
+    return N0;
+  }
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
   // fold (ffloor c1) -> ffloor(c1)

llvm/trunk/test/CodeGen/AMDGPU/combine-ftrunc.ll

+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}combine_ftrunc_frint_f64:
+; GCN: v_rndne_f64_e32 [[RND:v\[[0-9:]+\]]],
+; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], [[RND]]
+define amdgpu_kernel void @combine_ftrunc_frint_f64(double addrspace(1)* %p) {
+  %v = load double, double addrspace(1)* %p, align 8
+  %round = tail call double @llvm.rint.f64(double %v)
+  %trunc = tail call double @llvm.trunc.f64(double %round)
+  store double %trunc, double addrspace(1)* %p, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}combine_ftrunc_frint_f32:
+; GCN: v_rndne_f32_e32 [[RND:v[0-9]+]],
+; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
+define amdgpu_kernel void @combine_ftrunc_frint_f32(float addrspace(1)* %p) {
+  %v = load float, float addrspace(1)* %p, align 4
+  %round = tail call float @llvm.rint.f32(float %v)
+  %trunc = tail call float @llvm.trunc.f32(float %round)
+  store float %trunc, float addrspace(1)* %p, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}combine_ftrunc_frint_v2f32:
+; GCN: s_load_dwordx2
+; GCN: s_load_dwordx2 s{{\[}}[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]{{\]}}
+; GCN-DAG: v_rndne_f32_e32 v[[RND1:[0-9]+]], s[[SRC1]]
+; GCN-DAG: v_rndne_f32_e32 v[[RND2:[0-9]+]], s[[SRC2]]
+; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RND1]]:[[RND2]]{{\]}}
+define amdgpu_kernel void @combine_ftrunc_frint_v2f32(<2 x float> addrspace(1)* %p) {
+  %v = load <2 x float>, <2 x float> addrspace(1)* %p, align 8
+  %round = tail call <2 x float> @llvm.rint.v2f32(<2 x float> %v)
+  %trunc = tail call <2 x float> @llvm.trunc.v2f32(<2 x float> %round)
+  store <2 x float> %trunc, <2 x float> addrspace(1)* %p, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}combine_ftrunc_fceil_f32:
+; GCN: v_ceil_f32_e32 [[RND:v[0-9]+]],
+; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
+define amdgpu_kernel void @combine_ftrunc_fceil_f32(float addrspace(1)* %p) {
+  %v = load float, float addrspace(1)* %p, align 4
+  %round = tail call float @llvm.ceil.f32(float %v)
+  %trunc = tail call float @llvm.trunc.f32(float %round)
+  store float %trunc, float addrspace(1)* %p, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}combine_ftrunc_ffloor_f32:
+; GCN: v_floor_f32_e32 [[RND:v[0-9]+]],
+; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
+define amdgpu_kernel void @combine_ftrunc_ffloor_f32(float addrspace(1)* %p) {
+  %v = load float, float addrspace(1)* %p, align 4
+  %round = tail call float @llvm.floor.f32(float %v)
+  %trunc = tail call float @llvm.trunc.f32(float %round)
+  store float %trunc, float addrspace(1)* %p, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}combine_ftrunc_fnearbyint_f32:
+; GCN: v_rndne_f32_e32 [[RND:v[0-9]+]],
+; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
+define amdgpu_kernel void @combine_ftrunc_fnearbyint_f32(float addrspace(1)* %p) {
+  %v = load float, float addrspace(1)* %p, align 4
+  %round = tail call float @llvm.nearbyint.f32(float %v)
+  %trunc = tail call float @llvm.trunc.f32(float %round)
+  store float %trunc, float addrspace(1)* %p, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}combine_ftrunc_ftrunc_f32:
+; GCN: s_load_dword [[SRC:s[0-9]+]],
+; GCN: v_trunc_f32_e32 [[RND:v[0-9]+]], [[SRC]]
+; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
+define amdgpu_kernel void @combine_ftrunc_ftrunc_f32(float addrspace(1)* %p) {
+  %v = load float, float addrspace(1)* %p, align 4
+  %round = tail call float @llvm.trunc.f32(float %v)
+  %trunc = tail call float @llvm.trunc.f32(float %round)
+  store float %trunc, float addrspace(1)* %p, align 4
+  ret void
+}
+
+declare double @llvm.trunc.f64(double)
+declare float @llvm.trunc.f32(float)
+declare <2 x float> @llvm.trunc.v2f32(<2 x float>)
+declare double @llvm.rint.f64(double)
+declare float @llvm.rint.f32(float)
+declare <2 x float> @llvm.rint.v2f32(<2 x float>)
+declare float @llvm.ceil.f32(float)
+declare float @llvm.floor.f32(float)
+declare float @llvm.nearbyint.f32(float)