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Differential D37559

[X86FixupBWInsts] More presise register liveness if no <imp-use> on MOVs.
ClosedPublic

Authored by a.elovikov on Sep 7 2017, 4:07 AM.

Details

Reviewers
MatzeB
DavidKreitzer
ab
andrew.w.kaylor
craig.topper
Commits
rG84af99b3b1ce: [X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs.
rL313524: [X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs.
Summary

Subregister liveness tracking is not implemented for X86 backend, so
sometimes the whole super register is said to be live, when only a
subregister is really live. That might happen if the def and the use
are located in different MBBs, see added fixup-bw-isnt.mir test.

However, using knowledge of the specific instructions handled by the
bw-fixup-pass we can get more precise liveness information which this
change does.

Diff Detail

Event Timeline

a.elovikov created this revision.Sep 7 2017, 4:07 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptSep 7 2017, 4:07 AM
a.elovikov added a comment.Sep 12 2017, 11:28 AM

Ping.

DavidKreitzer added reviewers: andrew.w.kaylor, craig.topper.Sep 13 2017, 5:08 PM
craig.topper added inline comments.Sep 13 2017, 8:33 PM
llvm/lib/Target/X86/X86FixupBWInsts.cpp
220

I don't think the isDef and isUse check is necessary. An operand is either a use or a def. There's no third state.

craig.topper added inline comments.Sep 13 2017, 9:46 PM
llvm/lib/Target/X86/X86FixupBWInsts.cpp
169

Not directly related to this patch, but is this TODO still accurate? When it was written this algorithm was completely different. Right now we're using the live regs after the instruction we're considering so we shouldn't be seeing live regs from the address calc right?

a.elovikov updated this revision to Diff 115178.Sep 14 2017, 12:59 AM
  • Address review comments.
Harbormaster completed remote builds in B10221: Diff 115178.Sep 14 2017, 12:59 AM
a.elovikov marked 2 inline comments as done.Sep 14 2017, 1:01 AM
craig.topper accepted this revision.Sep 14 2017, 2:42 PM

LGTM

This revision is now accepted and ready to land.Sep 14 2017, 2:42 PM
Closed by commit rL313524: [X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs. (authored by n.bozhenov). · Explain WhySep 18 2017, 3:19 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 114148

llvm/lib/Target/X86/X86FixupBWInsts.cpp

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Linesbool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
for (auto &MBB : MF) for (auto &MBB : MF)
processBasicBlock(MF, MBB); processBasicBlock(MF, MBB);
DEBUG(dbgs() << "End X86FixupBWInsts\n";); DEBUG(dbgs() << "End X86FixupBWInsts\n";);
return true; return true;
} }
/// Check if register \p Reg is live after the \p MI.
///
/// \p LiveRegs should be in a state describing liveness information in
/// that exact place as this function tries to precise analysis made
/// by \p LiveRegs by exploiting the information about particular
/// instruction \p MI. \p MI is expected to be one of the MOVs handled
/// by the x86FixupBWInsts pass.
/// Note: similar to LivePhysRegs::contains this would state that
/// super-register is not used if only some part of it is used.
///
/// X86 backend does not have subregister liveness tracking enabled,
/// so liveness information might be overly conservative. However, for
/// some specific instructions (this pass only cares about MOVs) we can
/// produce more precise results by analysing that MOV's operands.
///
/// Indeed, if super-register is not live before the mov it means that it
/// was originally <read-undef> and so we are free to modify these
/// undef upper bits. That may happen in case where the use is in another MBB
/// and the vreg/physreg corresponding to the move has higher width than
/// necessary (e.g. due to register coalescing with a "truncate" copy).
/// So, it handles pattern like this:
///
/// BB#2: derived from LLVM BB %if.then
/// Live Ins: %RDI
/// Predecessors according to CFG: BB#0
/// %AX<def> = MOV16rm %RDI<kill>, 1, %noreg, 0, %noreg, %EAX<imp-def>; mem:LD2[%p]
/// No %EAX<imp-use>
/// Successors according to CFG: BB#3(?%)
///
/// BB#3: derived from LLVM BB %if.end
/// Live Ins: %EAX Only %AX is actually live
/// Predecessors according to CFG: BB#2 BB#1
/// %AX<def> = KILL %AX, %EAX<imp-use,kill>
/// RET 0, %AX
static bool isLive(const MachineInstr &MI,
const LivePhysRegs &LiveRegs,
const TargetRegisterInfo *TRI,
unsigned Reg) {
if (!LiveRegs.contains(Reg))
return false;
unsigned Opc = MI.getOpcode(); (void)Opc;
// These are the opcodes currently handled by the pass, if something
// else will be added we need to ensure that new opcode has the same
// properties.
assert((Opc == X86::MOV8rm || Opc == X86::MOV16rm || Opc == X86::MOV8rr ||
Opc == X86::MOV16rr) &&
"Unexpected opcode.");
bool IsDefined = false;
for (auto &MO: MI.implicit_operands()) {
if (!MO.isReg() || (!MO.isDef() && !MO.isUse()))
craig.topperUnsubmitted
Done
ReplyInline Actions

I don't think the isDef and isUse check is necessary. An operand is either a use or a def. There's no third state.

craig.topper: I don't think the isDef and isUse check is necessary. An operand is either a use or a def.
continue;
for (MCSuperRegIterator Supers(Reg, TRI, true); Supers.isValid(); ++Supers) {
if (*Supers == MO.getReg()) {
if (MO.isDef())
IsDefined = true;
else
return true; // SuperReg Imp-used' -> live before the MI
}
}
}
// Reg is not Imp-def'ed -> it's live both before/after the instruction.
if (!IsDefined)
return true;
// Otherwise, the Reg is not live before the MI and the MOV can't
// make it really live, so it's in fact dead even after the MI.
return false;
}
// TODO: This method of analysis can miss some legal cases, because the // TODO: This method of analysis can miss some legal cases, because the
craig.topperUnsubmitted
Done
ReplyInline Actions

Not directly related to this patch, but is this TODO still accurate? When it was written this algorithm was completely different. Right now we're using the live regs after the instruction we're considering so we shouldn't be seeing live regs from the address calc right?

craig.topper: Not directly related to this patch, but is this TODO still accurate? When it was written this…
// super-register could be live into the address expression for a memory // super-register could be live into the address expression for a memory
// reference for the instruction, and still be killed/last used by the // reference for the instruction, and still be killed/last used by the
// instruction. However, the existing query interfaces don't seem to // instruction. However, the existing query interfaces don't seem to
// easily allow that to be checked. // easily allow that to be checked.
// //
// What we'd really like to know is whether after OrigMI, the // What we'd really like to know is whether after OrigMI, the
// only portion of SuperDestReg that is alive is the portion that // only portion of SuperDestReg that is alive is the portion that
// was the destination register of OrigMI. // was the destination register of OrigMI.
bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI, bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
unsigned &SuperDestReg) const { unsigned &SuperDestReg) const {
auto *TRI = &TII->getRegisterInfo(); auto *TRI = &TII->getRegisterInfo();
unsigned OrigDestReg = OrigMI->getOperand(0).getReg(); unsigned OrigDestReg = OrigMI->getOperand(0).getReg();
SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32); SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
// Make sure that the sub-register that this instruction has as its // Make sure that the sub-register that this instruction has as its
// destination is the lowest order sub-register of the super-register. // destination is the lowest order sub-register of the super-register.
// If it isn't, then the register isn't really dead even if the // If it isn't, then the register isn't really dead even if the
// super-register is considered dead. // super-register is considered dead.
if (SubRegIdx == X86::sub_8bit_hi) if (SubRegIdx == X86::sub_8bit_hi)
return false; return false;
if (LiveRegs.contains(SuperDestReg)) if (isLive(*OrigMI, LiveRegs, TRI, SuperDestReg))
return false; return false;
if (SubRegIdx == X86::sub_8bit) { if (SubRegIdx == X86::sub_8bit) {
// In the case of byte registers, we also have to check that the upper // In the case of byte registers, we also have to check that the upper
// byte register is also dead. That is considered to be independent of // byte register is also dead. That is considered to be independent of
// whether the super-register is dead. // whether the super-register is dead.
unsigned UpperByteReg = unsigned UpperByteReg =
getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true); getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true);
if (LiveRegs.contains(UpperByteReg)) if (isLive(*OrigMI, LiveRegs, TRI, UpperByteReg))
return false; return false;
} }
return true; return true;
} }
MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
MachineInstr *MI) const { MachineInstr *MI) const {
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Linesvoid FixupBWInstPass::processBasicBlock(MachineFunction &MF,
// Start computing liveness for this block. We iterate from the end to be able // Start computing liveness for this block. We iterate from the end to be able
// to update this for each instruction. // to update this for each instruction.
LiveRegs.clear(); LiveRegs.clear();
// We run after PEI, so we need to AddPristinesAndCSRs. // We run after PEI, so we need to AddPristinesAndCSRs.
LiveRegs.addLiveOuts(MBB); LiveRegs.addLiveOuts(MBB);
for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) { for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
MachineInstr *MI = &*I; MachineInstr *MI = &*I;
if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB)) if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB))
MIReplacements.push_back(std::make_pair(MI, NewMI)); MIReplacements.push_back(std::make_pair(MI, NewMI));
// We're done with this instruction, update liveness for the next one. // We're done with this instruction, update liveness for the next one.
LiveRegs.stepBackward(*MI); LiveRegs.stepBackward(*MI);
} }
while (!MIReplacements.empty()) { while (!MIReplacements.empty()) {
MachineInstr *MI = MIReplacements.back().first; MachineInstr *MI = MIReplacements.back().first;
MachineInstr *NewMI = MIReplacements.back().second; MachineInstr *NewMI = MIReplacements.back().second;
MIReplacements.pop_back(); MIReplacements.pop_back();
MBB.insert(MI, NewMI); MBB.insert(MI, NewMI);
MBB.erase(MI); MBB.erase(MI);
} }
} }

llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 979 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = insertelement <32 x i8> %arg0, i8 %a1, i32 4 %res = insertelement <32 x i8> %arg0, i8 %a1, i32 4
%bc = bitcast <32 x i8> %res to <4 x i64> %bc = bitcast <32 x i8> %res to <4 x i64>
ret <4 x i64> %bc ret <4 x i64> %bc
} }
define <4 x i64> @test_mm256_insert_epi16(<4 x i64> %a0, i16 %a1) nounwind { define <4 x i64> @test_mm256_insert_epi16(<4 x i64> %a0, i16 %a1) nounwind {
; X32-LABEL: test_mm256_insert_epi16: ; X32-LABEL: test_mm256_insert_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X32-NEXT: vextractf128 $1, %ymm0, %xmm1
; X32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_insert_epi16: ; X64-LABEL: test_mm256_insert_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm1
▲ Show 20 Lines • Show All 1,029 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res31 = insertelement <32 x i8> %res30, i8 %a0 , i32 31 %res31 = insertelement <32 x i8> %res30, i8 %a0 , i32 31
%res = bitcast <32 x i8> %res31 to <4 x i64> %res = bitcast <32 x i8> %res31 to <4 x i64>
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_mm256_set_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind { define <4 x i64> @test_mm256_set_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind {
; X32-LABEL: test_mm256_set_epi16: ; X32-LABEL: test_mm256_set_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovd %eax, %xmm0 ; X32-NEXT: vmovd %eax, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovd %eax, %xmm1 ; X32-NEXT: vmovd %eax, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_set_epi16: ; X64-LABEL: test_mm256_set_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vmovd %eax, %xmm0 ; X64-NEXT: vmovd %eax, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
; X64-NEXT: vpinsrw $2, %r9d, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $2, %r9d, %xmm0, %xmm0
; X64-NEXT: vpinsrw $3, %r8d, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $3, %r8d, %xmm0, %xmm0
; X64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
; X64-NEXT: vpinsrw $5, %edx, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $5, %edx, %xmm0, %xmm0
; X64-NEXT: vpinsrw $6, %esi, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $6, %esi, %xmm0, %xmm0
; X64-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vmovd %eax, %xmm1 ; X64-NEXT: vmovd %eax, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = insertelement <16 x i16> undef, i16 %a15, i32 0 %res0 = insertelement <16 x i16> undef, i16 %a15, i32 0
%res1 = insertelement <16 x i16> %res0, i16 %a14, i32 1 %res1 = insertelement <16 x i16> %res0, i16 %a14, i32 1
%res2 = insertelement <16 x i16> %res1, i16 %a13, i32 2 %res2 = insertelement <16 x i16> %res1, i16 %a13, i32 2
%res3 = insertelement <16 x i16> %res2, i16 %a12, i32 3 %res3 = insertelement <16 x i16> %res2, i16 %a12, i32 3
%res4 = insertelement <16 x i16> %res3, i16 %a11, i32 4 %res4 = insertelement <16 x i16> %res3, i16 %a11, i32 4
▲ Show 20 Lines • Show All 253 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res31 = insertelement <32 x i8> %res30, i8 %a0, i32 31 %res31 = insertelement <32 x i8> %res30, i8 %a0, i32 31
%res = bitcast <32 x i8> %res31 to <4 x i64> %res = bitcast <32 x i8> %res31 to <4 x i64>
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_mm256_set1_epi16(i16 %a0) nounwind { define <4 x i64> @test_mm256_set1_epi16(i16 %a0) nounwind {
; X32-LABEL: test_mm256_set1_epi16: ; X32-LABEL: test_mm256_set1_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovd %eax, %xmm0 ; X32-NEXT: vmovd %eax, %xmm0
; X32-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] ; X32-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_set1_epi16: ; X64-LABEL: test_mm256_set1_epi16:
; X64: # BB#0: ; X64: # BB#0:
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%res31 = insertelement <32 x i8> %res30, i8 %a31, i32 31 %res31 = insertelement <32 x i8> %res30, i8 %a31, i32 31
%res = bitcast <32 x i8> %res31 to <4 x i64> %res = bitcast <32 x i8> %res31 to <4 x i64>
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_mm256_setr_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind { define <4 x i64> @test_mm256_setr_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind {
; X32-LABEL: test_mm256_setr_epi16: ; X32-LABEL: test_mm256_setr_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovd %eax, %xmm0 ; X32-NEXT: vmovd %eax, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0 ; X32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vmovd %eax, %xmm1 ; X32-NEXT: vmovd %eax, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_setr_epi16: ; X64-LABEL: test_mm256_setr_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vmovd %eax, %xmm0 ; X64-NEXT: vmovd %eax, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0 ; X64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
; X64-NEXT: vmovd %edi, %xmm1 ; X64-NEXT: vmovd %edi, %xmm1
; X64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
; X64-NEXT: vpinsrw $2, %edx, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $2, %edx, %xmm1, %xmm1
; X64-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1
; X64-NEXT: vpinsrw $4, %r8d, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $4, %r8d, %xmm1, %xmm1
; X64-NEXT: vpinsrw $5, %r9d, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $5, %r9d, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = insertelement <16 x i16> undef, i16 %a0 , i32 0 %res0 = insertelement <16 x i16> undef, i16 %a0 , i32 0
%res1 = insertelement <16 x i16> %res0, i16 %a1 , i32 1 %res1 = insertelement <16 x i16> %res0, i16 %a1 , i32 1
%res2 = insertelement <16 x i16> %res1, i16 %a2 , i32 2 %res2 = insertelement <16 x i16> %res1, i16 %a2 , i32 2
%res3 = insertelement <16 x i16> %res2, i16 %a3 , i32 3 %res3 = insertelement <16 x i16> %res2, i16 %a3 , i32 3
%res4 = insertelement <16 x i16> %res3, i16 %a4 , i32 4 %res4 = insertelement <16 x i16> %res3, i16 %a4 , i32 4
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llvm/test/CodeGen/X86/avx2-vbroadcast.ll

Show First 20 Lines • Show All 1,209 Lines • ▼ Show 20 Lines
; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp)
; X32-NEXT: addl $60, %esp ; X32-NEXT: addl $60, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: isel_crash_8w: ; X64-LABEL: isel_crash_8w:
; X64: ## BB#0: ## %entry ; X64: ## BB#0: ## %entry
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; X64-NEXT: movw (%rdi), %ax ; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: vmovd %eax, %xmm1 ; X64-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpbroadcastw %xmm1, %xmm1 ; X64-NEXT: vpbroadcastw %xmm1, %xmm1
; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; X64-NEXT: vmovdqa %xmm1, -{{[0-9]+}}(%rsp) ; X64-NEXT: vmovdqa %xmm1, -{{[0-9]+}}(%rsp)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%__a.addr.i = alloca <2 x i64>, align 16 %__a.addr.i = alloca <2 x i64>, align 16
%__b.addr.i = alloca <2 x i64>, align 16 %__b.addr.i = alloca <2 x i64>, align 16
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; X64-NEXT: .cfi_offset %rbp, -16 ; X64-NEXT: .cfi_offset %rbp, -16
; X64-NEXT: movq %rsp, %rbp ; X64-NEXT: movq %rsp, %rbp
; X64-NEXT: Lcfi5: ; X64-NEXT: Lcfi5:
; X64-NEXT: .cfi_def_cfa_register %rbp ; X64-NEXT: .cfi_def_cfa_register %rbp
; X64-NEXT: andq $-32, %rsp ; X64-NEXT: andq $-32, %rsp
; X64-NEXT: subq $128, %rsp ; X64-NEXT: subq $128, %rsp
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vmovaps %ymm0, (%rsp) ; X64-NEXT: vmovaps %ymm0, (%rsp)
; X64-NEXT: movw (%rdi), %ax ; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: vmovd %eax, %xmm1 ; X64-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpbroadcastw %xmm1, %ymm1 ; X64-NEXT: vpbroadcastw %xmm1, %ymm1
; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-NEXT: movq %rbp, %rsp ; X64-NEXT: movq %rbp, %rsp
; X64-NEXT: popq %rbp ; X64-NEXT: popq %rbp
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
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llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

Show All 17 Lines; X64-NEXT: retq
%res0 = shufflevector <4 x i32> %arg0, <4 x i32> undef, <16 x i32> zeroinitializer %res0 = shufflevector <4 x i32> %arg0, <4 x i32> undef, <16 x i32> zeroinitializer
%res1 = bitcast <16 x i32> %res0 to <8 x i64> %res1 = bitcast <16 x i32> %res0 to <8 x i64>
ret <8 x i64> %res1 ret <8 x i64> %res1
} }
define <8 x i64> @test_mm512_mask_broadcastd_epi32(<8 x i64> %a0, i16 %a1, <2 x i64> %a2) { define <8 x i64> @test_mm512_mask_broadcastd_epi32(<8 x i64> %a0, i16 %a1, <2 x i64> %a2) {
; X32-LABEL: test_mm512_mask_broadcastd_epi32: ; X32-LABEL: test_mm512_mask_broadcastd_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastd %xmm1, %zmm0 {%k1} ; X32-NEXT: vpbroadcastd %xmm1, %zmm0 {%k1}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_broadcastd_epi32: ; X64-LABEL: test_mm512_mask_broadcastd_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpbroadcastd %xmm1, %zmm0 {%k1} ; X64-NEXT: vpbroadcastd %xmm1, %zmm0 {%k1}
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <8 x i64> %a0 to <16 x i32> %arg0 = bitcast <8 x i64> %a0 to <16 x i32>
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%arg2 = bitcast <2 x i64> %a2 to <4 x i32> %arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res0 = shufflevector <4 x i32> %arg2, <4 x i32> undef, <16 x i32> zeroinitializer %res0 = shufflevector <4 x i32> %arg2, <4 x i32> undef, <16 x i32> zeroinitializer
%res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0 %res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0
%res2 = bitcast <16 x i32> %res1 to <8 x i64> %res2 = bitcast <16 x i32> %res1 to <8 x i64>
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
define <8 x i64> @test_mm512_maskz_broadcastd_epi32(i16 %a0, <2 x i64> %a1) { define <8 x i64> @test_mm512_maskz_broadcastd_epi32(i16 %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm512_maskz_broadcastd_epi32: ; X32-LABEL: test_mm512_maskz_broadcastd_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastd %xmm0, %zmm0 {%k1} {z} ; X32-NEXT: vpbroadcastd %xmm0, %zmm0 {%k1} {z}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_broadcastd_epi32: ; X64-LABEL: test_mm512_maskz_broadcastd_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpbroadcastd %xmm0, %zmm0 {%k1} {z} ; X64-NEXT: vpbroadcastd %xmm0, %zmm0 {%k1} {z}
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; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> undef, <16 x i32> zeroinitializer %res = shufflevector <4 x float> %a0, <4 x float> undef, <16 x i32> zeroinitializer
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_mask_broadcastss_ps(<16 x float> %a0, i16 %a1, <4 x float> %a2) { define <16 x float> @test_mm512_mask_broadcastss_ps(<16 x float> %a0, i16 %a1, <4 x float> %a2) {
; X32-LABEL: test_mm512_mask_broadcastss_ps: ; X32-LABEL: test_mm512_mask_broadcastss_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vbroadcastss %xmm1, %zmm0 {%k1} ; X32-NEXT: vbroadcastss %xmm1, %zmm0 {%k1}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_broadcastss_ps: ; X64-LABEL: test_mm512_mask_broadcastss_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vbroadcastss %xmm1, %zmm0 {%k1} ; X64-NEXT: vbroadcastss %xmm1, %zmm0 {%k1}
; X64-NEXT: retq ; X64-NEXT: retq
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%res0 = shufflevector <4 x float> %a2, <4 x float> undef, <16 x i32> zeroinitializer %res0 = shufflevector <4 x float> %a2, <4 x float> undef, <16 x i32> zeroinitializer
%res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0 %res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @test_mm512_maskz_broadcastss_ps(i16 %a0, <4 x float> %a1) { define <16 x float> @test_mm512_maskz_broadcastss_ps(i16 %a0, <4 x float> %a1) {
; X32-LABEL: test_mm512_maskz_broadcastss_ps: ; X32-LABEL: test_mm512_maskz_broadcastss_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vbroadcastss %xmm0, %zmm0 {%k1} {z} ; X32-NEXT: vbroadcastss %xmm0, %zmm0 {%k1} {z}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_broadcastss_ps: ; X64-LABEL: test_mm512_maskz_broadcastss_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vbroadcastss %xmm0, %zmm0 {%k1} {z} ; X64-NEXT: vbroadcastss %xmm0, %zmm0 {%k1} {z}
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; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <16 x float> %a0, <16 x float> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15> %res = shufflevector <16 x float> %a0, <16 x float> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_mask_movehdup_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2) { define <16 x float> @test_mm512_mask_movehdup_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2) {
; X32-LABEL: test_mm512_mask_movehdup_ps: ; X32-LABEL: test_mm512_mask_movehdup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15] ; X32-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_movehdup_ps: ; X64-LABEL: test_mm512_mask_movehdup_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15] ; X64-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; X64-NEXT: retq ; X64-NEXT: retq
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15> %res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
%res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0 %res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @test_mm512_maskz_movehdup_ps(i16 %a0, <16 x float> %a1) { define <16 x float> @test_mm512_maskz_movehdup_ps(i16 %a0, <16 x float> %a1) {
; X32-LABEL: test_mm512_maskz_movehdup_ps: ; X32-LABEL: test_mm512_maskz_movehdup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15] ; X32-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_movehdup_ps: ; X64-LABEL: test_mm512_maskz_movehdup_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15] ; X64-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
Show All 16 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <16 x float> %a0, <16 x float> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14> %res = shufflevector <16 x float> %a0, <16 x float> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_mask_moveldup_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2) { define <16 x float> @test_mm512_mask_moveldup_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2) {
; X32-LABEL: test_mm512_mask_moveldup_ps: ; X32-LABEL: test_mm512_mask_moveldup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14] ; X32-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_moveldup_ps: ; X64-LABEL: test_mm512_mask_moveldup_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14] ; X64-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
; X64-NEXT: retq ; X64-NEXT: retq
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14> %res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
%res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0 %res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @test_mm512_maskz_moveldup_ps(i16 %a0, <16 x float> %a1) { define <16 x float> @test_mm512_maskz_moveldup_ps(i16 %a0, <16 x float> %a1) {
; X32-LABEL: test_mm512_maskz_moveldup_ps: ; X32-LABEL: test_mm512_maskz_moveldup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14] ; X32-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_moveldup_ps: ; X64-LABEL: test_mm512_maskz_moveldup_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14] ; X64-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <16 x float> %a0, <16 x float> undef, <16 x i32> <i32 2, i32 0, i32 0, i32 0, i32 6, i32 4, i32 4, i32 4, i32 10, i32 8, i32 8, i32 8, i32 14, i32 12, i32 12, i32 12> %res = shufflevector <16 x float> %a0, <16 x float> undef, <16 x i32> <i32 2, i32 0, i32 0, i32 0, i32 6, i32 4, i32 4, i32 4, i32 10, i32 8, i32 8, i32 8, i32 14, i32 12, i32 12, i32 12>
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_mask_permute_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2) { define <16 x float> @test_mm512_mask_permute_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2) {
; X32-LABEL: test_mm512_mask_permute_ps: ; X32-LABEL: test_mm512_mask_permute_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpermilps {{.*#+}} zmm0 {%k1} = zmm1[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12] ; X32-NEXT: vpermilps {{.*#+}} zmm0 {%k1} = zmm1[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_permute_ps: ; X64-LABEL: test_mm512_mask_permute_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpermilps {{.*#+}} zmm0 {%k1} = zmm1[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12] ; X64-NEXT: vpermilps {{.*#+}} zmm0 {%k1} = zmm1[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12]
; X64-NEXT: retq ; X64-NEXT: retq
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 2, i32 0, i32 0, i32 0, i32 6, i32 4, i32 4, i32 4, i32 10, i32 8, i32 8, i32 8, i32 14, i32 12, i32 12, i32 12> %res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 2, i32 0, i32 0, i32 0, i32 6, i32 4, i32 4, i32 4, i32 10, i32 8, i32 8, i32 8, i32 14, i32 12, i32 12, i32 12>
%res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0 %res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @test_mm512_maskz_permute_ps(i16 %a0, <16 x float> %a1) { define <16 x float> @test_mm512_maskz_permute_ps(i16 %a0, <16 x float> %a1) {
; X32-LABEL: test_mm512_maskz_permute_ps: ; X32-LABEL: test_mm512_maskz_permute_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpermilps {{.*#+}} zmm0 {%k1} {z} = zmm0[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12] ; X32-NEXT: vpermilps {{.*#+}} zmm0 {%k1} {z} = zmm0[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_permute_ps: ; X64-LABEL: test_mm512_maskz_permute_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpermilps {{.*#+}} zmm0 {%k1} {z} = zmm0[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12] ; X64-NEXT: vpermilps {{.*#+}} zmm0 {%k1} {z} = zmm0[2,0,0,0,6,4,4,4,10,8,8,8,14,12,12,12]
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res0 = shufflevector <16 x i32> %arg0, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4, i32 9, i32 8, i32 8, i32 8, i32 13, i32 12, i32 12, i32 12> %res0 = shufflevector <16 x i32> %arg0, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4, i32 9, i32 8, i32 8, i32 8, i32 13, i32 12, i32 12, i32 12>
%res1 = bitcast <16 x i32> %res0 to <8 x i64> %res1 = bitcast <16 x i32> %res0 to <8 x i64>
ret <8 x i64> %res1 ret <8 x i64> %res1
} }
define <8 x i64> @test_mm512_mask_shuffle_epi32(<8 x i64> %a0, i16 %a1, <8 x i64> %a2) { define <8 x i64> @test_mm512_mask_shuffle_epi32(<8 x i64> %a0, i16 %a1, <8 x i64> %a2) {
; X32-LABEL: test_mm512_mask_shuffle_epi32: ; X32-LABEL: test_mm512_mask_shuffle_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpshufd {{.*#+}} zmm0 {%k1} = zmm1[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12] ; X32-NEXT: vpshufd {{.*#+}} zmm0 {%k1} = zmm1[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_shuffle_epi32: ; X64-LABEL: test_mm512_mask_shuffle_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpshufd {{.*#+}} zmm0 {%k1} = zmm1[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12] ; X64-NEXT: vpshufd {{.*#+}} zmm0 {%k1} = zmm1[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12]
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <8 x i64> %a0 to <16 x i32> %arg0 = bitcast <8 x i64> %a0 to <16 x i32>
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%arg2 = bitcast <8 x i64> %a2 to <16 x i32> %arg2 = bitcast <8 x i64> %a2 to <16 x i32>
%res0 = shufflevector <16 x i32> %arg2, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4, i32 9, i32 8, i32 8, i32 8, i32 13, i32 12, i32 12, i32 12> %res0 = shufflevector <16 x i32> %arg2, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4, i32 9, i32 8, i32 8, i32 8, i32 13, i32 12, i32 12, i32 12>
%res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0 %res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0
%res2 = bitcast <16 x i32> %res1 to <8 x i64> %res2 = bitcast <16 x i32> %res1 to <8 x i64>
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
define <8 x i64> @test_mm512_maskz_shuffle_epi32(i16 %a0, <8 x i64> %a1) { define <8 x i64> @test_mm512_maskz_shuffle_epi32(i16 %a0, <8 x i64> %a1) {
; X32-LABEL: test_mm512_maskz_shuffle_epi32: ; X32-LABEL: test_mm512_maskz_shuffle_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpshufd {{.*#+}} zmm0 {%k1} {z} = zmm0[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12] ; X32-NEXT: vpshufd {{.*#+}} zmm0 {%k1} {z} = zmm0[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_shuffle_epi32: ; X64-LABEL: test_mm512_maskz_shuffle_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpshufd {{.*#+}} zmm0 {%k1} {z} = zmm0[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12] ; X64-NEXT: vpshufd {{.*#+}} zmm0 {%k1} {z} = zmm0[1,0,0,0,5,4,4,4,9,8,8,8,13,12,12,12]
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res0 = shufflevector <16 x i32> %arg0, <16 x i32> %arg1, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31> %res0 = shufflevector <16 x i32> %arg0, <16 x i32> %arg1, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31>
%res1 = bitcast <16 x i32> %res0 to <8 x i64> %res1 = bitcast <16 x i32> %res0 to <8 x i64>
ret <8 x i64> %res1 ret <8 x i64> %res1
} }
define <8 x i64> @test_mm512_mask_unpackhi_epi32(<8 x i64> %a0, i16 %a1, <8 x i64> %a2, <8 x i64> %a3) { define <8 x i64> @test_mm512_mask_unpackhi_epi32(<8 x i64> %a0, i16 %a1, <8 x i64> %a2, <8 x i64> %a3) {
; X32-LABEL: test_mm512_mask_unpackhi_epi32: ; X32-LABEL: test_mm512_mask_unpackhi_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15] ; X32-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_unpackhi_epi32: ; X64-LABEL: test_mm512_mask_unpackhi_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15] ; X64-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15]
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <8 x i64> %a0 to <16 x i32> %arg0 = bitcast <8 x i64> %a0 to <16 x i32>
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%arg2 = bitcast <8 x i64> %a2 to <16 x i32> %arg2 = bitcast <8 x i64> %a2 to <16 x i32>
%arg3 = bitcast <8 x i64> %a3 to <16 x i32> %arg3 = bitcast <8 x i64> %a3 to <16 x i32>
%res0 = shufflevector <16 x i32> %arg2, <16 x i32> %arg3, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31> %res0 = shufflevector <16 x i32> %arg2, <16 x i32> %arg3, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31>
%res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0 %res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0
%res2 = bitcast <16 x i32> %res1 to <8 x i64> %res2 = bitcast <16 x i32> %res1 to <8 x i64>
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
define <8 x i64> @test_mm512_maskz_unpackhi_epi32(i16 %a0, <8 x i64> %a1, <8 x i64> %a2) { define <8 x i64> @test_mm512_maskz_unpackhi_epi32(i16 %a0, <8 x i64> %a1, <8 x i64> %a2) {
; X32-LABEL: test_mm512_maskz_unpackhi_epi32: ; X32-LABEL: test_mm512_maskz_unpackhi_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] ; X32-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_unpackhi_epi32: ; X64-LABEL: test_mm512_maskz_unpackhi_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] ; X64-NEXT: vpunpckhdq {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15]
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <16 x float> %a0, <16 x float> %a1, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31> %res = shufflevector <16 x float> %a0, <16 x float> %a1, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31>
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_mask_unpackhi_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2, <16 x float> %a3) { define <16 x float> @test_mm512_mask_unpackhi_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2, <16 x float> %a3) {
; X32-LABEL: test_mm512_mask_unpackhi_ps: ; X32-LABEL: test_mm512_mask_unpackhi_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15] ; X32-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_unpackhi_ps: ; X64-LABEL: test_mm512_mask_unpackhi_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15] ; X64-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15]
; X64-NEXT: retq ; X64-NEXT: retq
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%res0 = shufflevector <16 x float> %a2, <16 x float> %a3, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31> %res0 = shufflevector <16 x float> %a2, <16 x float> %a3, <16 x i32> <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31>
%res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0 %res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @test_mm512_maskz_unpackhi_ps(i16 %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mm512_maskz_unpackhi_ps(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
; X32-LABEL: test_mm512_maskz_unpackhi_ps: ; X32-LABEL: test_mm512_maskz_unpackhi_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] ; X32-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_unpackhi_ps: ; X64-LABEL: test_mm512_maskz_unpackhi_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] ; X64-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15]
Show All 19 Lines; X64-NEXT: retq
%res0 = shufflevector <16 x i32> %arg0, <16 x i32> %arg1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> %res0 = shufflevector <16 x i32> %arg0, <16 x i32> %arg1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
%res1 = bitcast <16 x i32> %res0 to <8 x i64> %res1 = bitcast <16 x i32> %res0 to <8 x i64>
ret <8 x i64> %res1 ret <8 x i64> %res1
} }
define <8 x i64> @test_mm512_mask_unpacklo_epi32(<8 x i64> %a0, i16 %a1, <8 x i64> %a2, <8 x i64> %a3) { define <8 x i64> @test_mm512_mask_unpacklo_epi32(<8 x i64> %a0, i16 %a1, <8 x i64> %a2, <8 x i64> %a3) {
; X32-LABEL: test_mm512_mask_unpacklo_epi32: ; X32-LABEL: test_mm512_mask_unpacklo_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13] ; X32-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_unpacklo_epi32: ; X64-LABEL: test_mm512_mask_unpacklo_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13] ; X64-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13]
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <8 x i64> %a0 to <16 x i32> %arg0 = bitcast <8 x i64> %a0 to <16 x i32>
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%arg2 = bitcast <8 x i64> %a2 to <16 x i32> %arg2 = bitcast <8 x i64> %a2 to <16 x i32>
%arg3 = bitcast <8 x i64> %a3 to <16 x i32> %arg3 = bitcast <8 x i64> %a3 to <16 x i32>
%res0 = shufflevector <16 x i32> %arg2, <16 x i32> %arg3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> %res0 = shufflevector <16 x i32> %arg2, <16 x i32> %arg3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
%res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0 %res1 = select <16 x i1> %arg1, <16 x i32> %res0, <16 x i32> %arg0
%res2 = bitcast <16 x i32> %res1 to <8 x i64> %res2 = bitcast <16 x i32> %res1 to <8 x i64>
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
define <8 x i64> @test_mm512_maskz_unpacklo_epi32(i16 %a0, <8 x i64> %a1, <8 x i64> %a2) { define <8 x i64> @test_mm512_maskz_unpacklo_epi32(i16 %a0, <8 x i64> %a1, <8 x i64> %a2) {
; X32-LABEL: test_mm512_maskz_unpacklo_epi32: ; X32-LABEL: test_mm512_maskz_unpacklo_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] ; X32-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_unpacklo_epi32: ; X64-LABEL: test_mm512_maskz_unpacklo_epi32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] ; X64-NEXT: vpunpckldq {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
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; X64-NEXT: retq ; X64-NEXT: retq
%res = shufflevector <16 x float> %a0, <16 x float> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> %res = shufflevector <16 x float> %a0, <16 x float> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mm512_mask_unpacklo_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2, <16 x float> %a3) { define <16 x float> @test_mm512_mask_unpacklo_ps(<16 x float> %a0, i16 %a1, <16 x float> %a2, <16 x float> %a3) {
; X32-LABEL: test_mm512_mask_unpacklo_ps: ; X32-LABEL: test_mm512_mask_unpacklo_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13] ; X32-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_mask_unpacklo_ps: ; X64-LABEL: test_mm512_mask_unpacklo_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13] ; X64-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13]
; X64-NEXT: retq ; X64-NEXT: retq
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%res0 = shufflevector <16 x float> %a2, <16 x float> %a3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> %res0 = shufflevector <16 x float> %a2, <16 x float> %a3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
%res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0 %res1 = select <16 x i1> %arg1, <16 x float> %res0, <16 x float> %a0
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @test_mm512_maskz_unpacklo_ps(i16 %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mm512_maskz_unpacklo_ps(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
; X32-LABEL: test_mm512_maskz_unpacklo_ps: ; X32-LABEL: test_mm512_maskz_unpacklo_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] ; X32-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm512_maskz_unpacklo_ps: ; X64-LABEL: test_mm512_maskz_unpacklo_ps:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] ; X64-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
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llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

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; AVX512F-32-NEXT: subl $60, %esp ; AVX512F-32-NEXT: subl $60, %esp
; AVX512F-32-NEXT: .Lcfi7: ; AVX512F-32-NEXT: .Lcfi7:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: .Lcfi8: ; AVX512F-32-NEXT: .Lcfi8:
; AVX512F-32-NEXT: .cfi_offset %esi, -12 ; AVX512F-32-NEXT: .cfi_offset %esi, -12
; AVX512F-32-NEXT: .Lcfi9: ; AVX512F-32-NEXT: .Lcfi9:
; AVX512F-32-NEXT: .cfi_offset %ebx, -8 ; AVX512F-32-NEXT: .cfi_offset %ebx, -8
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: movb %cl, %bl ; AVX512F-32-NEXT: movl %ecx, %ebx
; AVX512F-32-NEXT: andb $15, %bl ; AVX512F-32-NEXT: andb $15, %bl
; AVX512F-32-NEXT: movb %cl, %dl ; AVX512F-32-NEXT: movl %ecx, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k0 ; AVX512F-32-NEXT: kmovd %edx, %k0
; AVX512F-32-NEXT: movb %bl, %dl ; AVX512F-32-NEXT: movl %ebx, %edx
; AVX512F-32-NEXT: shrb $2, %bl ; AVX512F-32-NEXT: shrb $2, %bl
; AVX512F-32-NEXT: kmovd %ebx, %k1 ; AVX512F-32-NEXT: kmovd %ebx, %k1
; AVX512F-32-NEXT: movb %cl, %bl ; AVX512F-32-NEXT: movl %ecx, %ebx
; AVX512F-32-NEXT: shrb $4, %bl ; AVX512F-32-NEXT: shrb $4, %bl
; AVX512F-32-NEXT: shrb $3, %dl ; AVX512F-32-NEXT: shrb $3, %dl
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: kmovd %ecx, %k0 ; AVX512F-32-NEXT: kmovd %ecx, %k0
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
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; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: kmovd %eax, %k0 ; AVX512F-32-NEXT: kmovd %eax, %k0
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vpsllq $40, %xmm3, %xmm3 ; AVX512F-32-NEXT: vpsllq $40, %xmm3, %xmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm2, %ymm3, %ymm3 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm2, %ymm3, %ymm3
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm3[0,1,2,3],zmm2[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm3[0,1,2,3],zmm2[4,5,6,7]
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $6, %al ; AVX512F-32-NEXT: shrb $6, %al
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $7, %al ; AVX512F-32-NEXT: shrb $7, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
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; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6] ; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6]
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %ch, %dl ; AVX512F-32-NEXT: movb %ch, %dl
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
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; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %bl ; AVX512F-32-NEXT: movl %eax, %ebx
; AVX512F-32-NEXT: andb $15, %bl ; AVX512F-32-NEXT: andb $15, %bl
; AVX512F-32-NEXT: movb %bl, %dl ; AVX512F-32-NEXT: movl %ebx, %edx
; AVX512F-32-NEXT: shrb $2, %bl ; AVX512F-32-NEXT: shrb $2, %bl
; AVX512F-32-NEXT: kmovd %ebx, %k1 ; AVX512F-32-NEXT: kmovd %ebx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: shrb $3, %dl ; AVX512F-32-NEXT: shrb $3, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $4, %dl ; AVX512F-32-NEXT: shrb $4, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $5, %dl ; AVX512F-32-NEXT: shrb $5, %dl
; AVX512F-32-NEXT: andb $1, %dl ; AVX512F-32-NEXT: andb $1, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $6, %dl ; AVX512F-32-NEXT: shrb $6, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
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; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm3 ; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm3
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm4 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 ; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm4[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm4[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm3, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm3, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3
; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6] ; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6]
; AVX512F-32-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm4 ; AVX512F-32-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm4
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm5 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm5
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm5, %ymm4, %ymm4 ; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm5, %ymm4, %ymm4
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm4 = zmm4[0,1,2,3],zmm5[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm4 = zmm4[0,1,2,3],zmm5[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm4, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm4, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4
; AVX512F-32-NEXT: vpbroadcastw %xmm4, %xmm4 ; AVX512F-32-NEXT: vpbroadcastw %xmm4, %xmm4
; AVX512F-32-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm5 ; AVX512F-32-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm5
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm6 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm6
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm6, %ymm5, %ymm5 ; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm6, %ymm5, %ymm5
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; AVX512F-32-NEXT: kmovd %ecx, %k1 ; AVX512F-32-NEXT: kmovd %ecx, %k1
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm2, %ymm3 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm2, %ymm3
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm3, %ymm4, %ymm3 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm3, %ymm4, %ymm3
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: andb $2, %al ; AVX512F-32-NEXT: andb $2, %al
; AVX512F-32-NEXT: shrb %al ; AVX512F-32-NEXT: shrb %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %dl ; AVX512F-32-NEXT: movl %ecx, %edx
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: shrb $3, %al ; AVX512F-32-NEXT: shrb $3, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $4, %al ; AVX512F-32-NEXT: shrb $4, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $6, %al ; AVX512F-32-NEXT: shrb $6, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $7, %al ; AVX512F-32-NEXT: shrb $7, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
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; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %ch, %dl ; AVX512F-32-NEXT: movb %ch, %dl
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %dl ; AVX512F-32-NEXT: movl %ebx, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: andb $15, %al ; AVX512F-32-NEXT: andb $15, %al
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $2, %al ; AVX512F-32-NEXT: shrb $2, %al
; AVX512F-32-NEXT: kmovd %eax, %k0 ; AVX512F-32-NEXT: kmovd %eax, %k0
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: shrb $3, %dl ; AVX512F-32-NEXT: shrb $3, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: shrb $4, %al ; AVX512F-32-NEXT: shrb $4, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: shrb $6, %al ; AVX512F-32-NEXT: shrb $6, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255]
Show All 18 Lines
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm2 ; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6] ; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6]
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k0 ; AVX512F-32-NEXT: kmovd %edx, %k0
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
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; AVX512F-32-NEXT: subl $60, %esp ; AVX512F-32-NEXT: subl $60, %esp
; AVX512F-32-NEXT: .Lcfi13: ; AVX512F-32-NEXT: .Lcfi13:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: .Lcfi14: ; AVX512F-32-NEXT: .Lcfi14:
; AVX512F-32-NEXT: .cfi_offset %esi, -12 ; AVX512F-32-NEXT: .cfi_offset %esi, -12
; AVX512F-32-NEXT: .Lcfi15: ; AVX512F-32-NEXT: .Lcfi15:
; AVX512F-32-NEXT: .cfi_offset %ebx, -8 ; AVX512F-32-NEXT: .cfi_offset %ebx, -8
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: movb %cl, %bl ; AVX512F-32-NEXT: movl %ecx, %ebx
; AVX512F-32-NEXT: andb $15, %bl ; AVX512F-32-NEXT: andb $15, %bl
; AVX512F-32-NEXT: movb %cl, %dl ; AVX512F-32-NEXT: movl %ecx, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k0 ; AVX512F-32-NEXT: kmovd %edx, %k0
; AVX512F-32-NEXT: movb %bl, %dl ; AVX512F-32-NEXT: movl %ebx, %edx
; AVX512F-32-NEXT: shrb $2, %bl ; AVX512F-32-NEXT: shrb $2, %bl
; AVX512F-32-NEXT: kmovd %ebx, %k1 ; AVX512F-32-NEXT: kmovd %ebx, %k1
; AVX512F-32-NEXT: movb %cl, %bl ; AVX512F-32-NEXT: movl %ecx, %ebx
; AVX512F-32-NEXT: shrb $4, %bl ; AVX512F-32-NEXT: shrb $4, %bl
; AVX512F-32-NEXT: shrb $3, %dl ; AVX512F-32-NEXT: shrb $3, %dl
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: kmovd %ecx, %k0 ; AVX512F-32-NEXT: kmovd %ecx, %k0
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
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; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: kmovd %eax, %k0 ; AVX512F-32-NEXT: kmovd %eax, %k0
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vpsllq $40, %xmm3, %xmm3 ; AVX512F-32-NEXT: vpsllq $40, %xmm3, %xmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm2, %ymm3, %ymm3 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm2, %ymm3, %ymm3
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm3[0,1,2,3],zmm2[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm3[0,1,2,3],zmm2[4,5,6,7]
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $6, %al ; AVX512F-32-NEXT: shrb $6, %al
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $7, %al ; AVX512F-32-NEXT: shrb $7, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
Show All 14 Lines
; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6] ; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6]
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %ch, %dl ; AVX512F-32-NEXT: movb %ch, %dl
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
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; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %bl ; AVX512F-32-NEXT: movl %eax, %ebx
; AVX512F-32-NEXT: andb $15, %bl ; AVX512F-32-NEXT: andb $15, %bl
; AVX512F-32-NEXT: movb %bl, %dl ; AVX512F-32-NEXT: movl %ebx, %edx
; AVX512F-32-NEXT: shrb $2, %bl ; AVX512F-32-NEXT: shrb $2, %bl
; AVX512F-32-NEXT: kmovd %ebx, %k1 ; AVX512F-32-NEXT: kmovd %ebx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: shrb $3, %dl ; AVX512F-32-NEXT: shrb $3, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $4, %dl ; AVX512F-32-NEXT: shrb $4, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $5, %dl ; AVX512F-32-NEXT: shrb $5, %dl
; AVX512F-32-NEXT: andb $1, %dl ; AVX512F-32-NEXT: andb $1, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $6, %dl ; AVX512F-32-NEXT: shrb $6, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
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; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm3 ; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm3
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm4 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 ; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm4[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm3 = zmm3[0,1,2,3],zmm4[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm3, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm3, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3
; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6] ; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6]
; AVX512F-32-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm4 ; AVX512F-32-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm4
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm5 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm5
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm5, %ymm4, %ymm4 ; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm5, %ymm4, %ymm4
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm4 = zmm4[0,1,2,3],zmm5[4,5,6,7] ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm4 = zmm4[0,1,2,3],zmm5[4,5,6,7]
; AVX512F-32-NEXT: vpmovb2m %zmm4, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm4, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4
; AVX512F-32-NEXT: vpbroadcastw %xmm4, %xmm4 ; AVX512F-32-NEXT: vpbroadcastw %xmm4, %xmm4
; AVX512F-32-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm5 ; AVX512F-32-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm5
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm6 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm6
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm6, %ymm5, %ymm5 ; AVX512F-32-NEXT: vpblendvb %ymm2, %ymm6, %ymm5, %ymm5
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; AVX512F-32-NEXT: kmovd %ecx, %k1 ; AVX512F-32-NEXT: kmovd %ecx, %k1
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm2, %ymm3 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm2, %ymm3
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm3, %ymm4, %ymm3 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm3, %ymm4, %ymm3
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: andb $2, %al ; AVX512F-32-NEXT: andb $2, %al
; AVX512F-32-NEXT: shrb %al ; AVX512F-32-NEXT: shrb %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %dl ; AVX512F-32-NEXT: movl %ecx, %edx
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: shrb $3, %al ; AVX512F-32-NEXT: shrb $3, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $4, %al ; AVX512F-32-NEXT: shrb $4, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $6, %al ; AVX512F-32-NEXT: shrb $6, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %cl, %al ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $7, %al ; AVX512F-32-NEXT: shrb $7, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $56, %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
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; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %ch, %dl ; AVX512F-32-NEXT: movb %ch, %dl
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %dl ; AVX512F-32-NEXT: movl %ebx, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: andb $15, %al ; AVX512F-32-NEXT: andb $15, %al
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: shrb $2, %al ; AVX512F-32-NEXT: shrb $2, %al
; AVX512F-32-NEXT: kmovd %eax, %k0 ; AVX512F-32-NEXT: kmovd %eax, %k0
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: shrb $3, %dl ; AVX512F-32-NEXT: shrb $3, %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpslld $24, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: shrb $4, %al ; AVX512F-32-NEXT: shrb $4, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastd %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2 ; AVX512F-32-NEXT: vpsllq $40, %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %bl, %al ; AVX512F-32-NEXT: movl %ebx, %eax
; AVX512F-32-NEXT: shrb $6, %al ; AVX512F-32-NEXT: shrb $6, %al
; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: kmovd %eax, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255]
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; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm2 ; AVX512F-32-NEXT: vpbroadcastq %xmm2, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $2, %dl ; AVX512F-32-NEXT: andb $2, %dl
; AVX512F-32-NEXT: shrb %dl ; AVX512F-32-NEXT: shrb %dl
; AVX512F-32-NEXT: kmovd %edx, %k1 ; AVX512F-32-NEXT: kmovd %edx, %k1
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2
; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6] ; AVX512F-32-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6]
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; AVX512F-32-NEXT: vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255]
; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2 ; AVX512F-32-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
; AVX512F-32-NEXT: movb %al, %dl ; AVX512F-32-NEXT: movl %eax, %edx
; AVX512F-32-NEXT: andb $15, %dl ; AVX512F-32-NEXT: andb $15, %dl
; AVX512F-32-NEXT: movb %dl, %al ; AVX512F-32-NEXT: movl %edx, %eax
; AVX512F-32-NEXT: shrb $2, %dl ; AVX512F-32-NEXT: shrb $2, %dl
; AVX512F-32-NEXT: kmovd %edx, %k0 ; AVX512F-32-NEXT: kmovd %edx, %k0
; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1 ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k1
; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2 ; AVX512F-32-NEXT: vpmovm2b %k0, %zmm2
; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX512F-32-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 ; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2
; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm3
; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4 ; AVX512F-32-NEXT: vextracti64x4 $1, %zmm3, %ymm4
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llvm/test/CodeGen/X86/avx512bw-intrinsics.ll

Show First 20 Lines • Show All 1,958 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpbroadcastw %edi, %zmm2 ; AVX512BW-NEXT: vpbroadcastw %edi, %zmm2
; AVX512BW-NEXT: vpaddw %zmm0, %zmm2, %zmm0 ; AVX512BW-NEXT: vpaddw %zmm0, %zmm2, %zmm0
; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0 ; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_int_x86_avx512_mask_pbroadcast_w_gpr_512: ; AVX512F-32-LABEL: test_int_x86_avx512_mask_pbroadcast_w_gpr_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: movw {{[0-9]+}}(%esp), %ax ; AVX512F-32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; AVX512F-32-NEXT: vpbroadcastw %eax, %zmm1 {%k1} {z} ; AVX512F-32-NEXT: vpbroadcastw %eax, %zmm1 {%k1} {z}
; AVX512F-32-NEXT: vpbroadcastw %eax, %zmm0 {%k1} ; AVX512F-32-NEXT: vpbroadcastw %eax, %zmm0 {%k1}
; AVX512F-32-NEXT: vpbroadcastw %eax, %zmm2 ; AVX512F-32-NEXT: vpbroadcastw %eax, %zmm2
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm2, %zmm0 ; AVX512F-32-NEXT: vpaddw %zmm0, %zmm2, %zmm0
; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0 ; AVX512F-32-NEXT: vpaddw %zmm0, %zmm1, %zmm0
; AVX512F-32-NEXT: retl ; AVX512F-32-NEXT: retl
%res = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> %x1, i32 -1) %res = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> %x1, i32 -1)
%res1 = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> %x1, i32 %mask) %res1 = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> %x1, i32 %mask)
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llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll

Show All 17 Lines; X64-NEXT: retq
%res0 = shufflevector <16 x i8> %arg0, <16 x i8> undef, <16 x i32> zeroinitializer %res0 = shufflevector <16 x i8> %arg0, <16 x i8> undef, <16 x i32> zeroinitializer
%res1 = bitcast <16 x i8> %res0 to <2 x i64> %res1 = bitcast <16 x i8> %res0 to <2 x i64>
ret <2 x i64> %res1 ret <2 x i64> %res1
} }
define <2 x i64> @test_mm_mask_broadcastb_epi8(<2 x i64> %a0, i16 %a1, <2 x i64> %a2) { define <2 x i64> @test_mm_mask_broadcastb_epi8(<2 x i64> %a0, i16 %a1, <2 x i64> %a2) {
; X32-LABEL: test_mm_mask_broadcastb_epi8: ; X32-LABEL: test_mm_mask_broadcastb_epi8:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovd %eax, %k1 ; X32-NEXT: kmovd %eax, %k1
; X32-NEXT: vpbroadcastb %xmm1, %xmm0 {%k1} ; X32-NEXT: vpbroadcastb %xmm1, %xmm0 {%k1}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm_mask_broadcastb_epi8: ; X64-LABEL: test_mm_mask_broadcastb_epi8:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpbroadcastb %xmm1, %xmm0 {%k1} ; X64-NEXT: vpbroadcastb %xmm1, %xmm0 {%k1}
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <2 x i64> %a0 to <16 x i8> %arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8> %arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res0 = shufflevector <16 x i8> %arg2, <16 x i8> undef, <16 x i32> zeroinitializer %res0 = shufflevector <16 x i8> %arg2, <16 x i8> undef, <16 x i32> zeroinitializer
%res1 = select <16 x i1> %arg1, <16 x i8> %res0, <16 x i8> %arg0 %res1 = select <16 x i1> %arg1, <16 x i8> %res0, <16 x i8> %arg0
%res2 = bitcast <16 x i8> %res1 to <2 x i64> %res2 = bitcast <16 x i8> %res1 to <2 x i64>
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
define <2 x i64> @test_mm_maskz_broadcastb_epi8(i16 %a0, <2 x i64> %a1) { define <2 x i64> @test_mm_maskz_broadcastb_epi8(i16 %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm_maskz_broadcastb_epi8: ; X32-LABEL: test_mm_maskz_broadcastb_epi8:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovd %eax, %k1 ; X32-NEXT: kmovd %eax, %k1
; X32-NEXT: vpbroadcastb %xmm0, %xmm0 {%k1} {z} ; X32-NEXT: vpbroadcastb %xmm0, %xmm0 {%k1} {z}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm_maskz_broadcastb_epi8: ; X64-LABEL: test_mm_maskz_broadcastb_epi8:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpbroadcastb %xmm0, %xmm0 {%k1} {z} ; X64-NEXT: vpbroadcastb %xmm0, %xmm0 {%k1} {z}
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%res0 = shufflevector <8 x i16> %arg0, <8 x i16> undef, <16 x i32> zeroinitializer %res0 = shufflevector <8 x i16> %arg0, <8 x i16> undef, <16 x i32> zeroinitializer
%res1 = bitcast <16 x i16> %res0 to <4 x i64> %res1 = bitcast <16 x i16> %res0 to <4 x i64>
ret <4 x i64> %res1 ret <4 x i64> %res1
} }
define <4 x i64> @test_mm256_mask_broadcastw_epi16(<4 x i64> %a0, i16 %a1, <2 x i64> %a2) { define <4 x i64> @test_mm256_mask_broadcastw_epi16(<4 x i64> %a0, i16 %a1, <2 x i64> %a2) {
; X32-LABEL: test_mm256_mask_broadcastw_epi16: ; X32-LABEL: test_mm256_mask_broadcastw_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovd %eax, %k1 ; X32-NEXT: kmovd %eax, %k1
; X32-NEXT: vpbroadcastw %xmm1, %ymm0 {%k1} ; X32-NEXT: vpbroadcastw %xmm1, %ymm0 {%k1}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_mask_broadcastw_epi16: ; X64-LABEL: test_mm256_mask_broadcastw_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpbroadcastw %xmm1, %ymm0 {%k1} ; X64-NEXT: vpbroadcastw %xmm1, %ymm0 {%k1}
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <4 x i64> %a0 to <16 x i16> %arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast i16 %a1 to <16 x i1> %arg1 = bitcast i16 %a1 to <16 x i1>
%arg2 = bitcast <2 x i64> %a2 to <8 x i16> %arg2 = bitcast <2 x i64> %a2 to <8 x i16>
%res0 = shufflevector <8 x i16> %arg2, <8 x i16> undef, <16 x i32> zeroinitializer %res0 = shufflevector <8 x i16> %arg2, <8 x i16> undef, <16 x i32> zeroinitializer
%res1 = select <16 x i1> %arg1, <16 x i16> %res0, <16 x i16> %arg0 %res1 = select <16 x i1> %arg1, <16 x i16> %res0, <16 x i16> %arg0
%res2 = bitcast <16 x i16> %res1 to <4 x i64> %res2 = bitcast <16 x i16> %res1 to <4 x i64>
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
define <4 x i64> @test_mm256_maskz_broadcastw_epi16(i16 %a0, <2 x i64> %a1) { define <4 x i64> @test_mm256_maskz_broadcastw_epi16(i16 %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm256_maskz_broadcastw_epi16: ; X32-LABEL: test_mm256_maskz_broadcastw_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovd %eax, %k1 ; X32-NEXT: kmovd %eax, %k1
; X32-NEXT: vpbroadcastw %xmm0, %ymm0 {%k1} {z} ; X32-NEXT: vpbroadcastw %xmm0, %ymm0 {%k1} {z}
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_maskz_broadcastw_epi16: ; X64-LABEL: test_mm256_maskz_broadcastw_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpbroadcastw %xmm0, %ymm0 {%k1} {z} ; X64-NEXT: vpbroadcastw %xmm0, %ymm0 {%k1} {z}
Show All 11 Lines

llvm/test/CodeGen/X86/bitreverse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
; These tests just check that the plumbing is in place for @llvm.bitreverse. The ; These tests just check that the plumbing is in place for @llvm.bitreverse. The
; actual output is massive at the moment as llvm.bitreverse is not yet legal. ; actual output is massive at the moment as llvm.bitreverse is not yet legal.
declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) nounwind { define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) nounwind {
; X86-LABEL: test_bitreverse_v2i16: ; X86-LABEL: test_bitreverse_v2i16:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: movw {{[0-9]+}}(%esp), %cx ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movw {{[0-9]+}}(%esp), %ax ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: rolw $8, %ax ; X86-NEXT: rolw $8, %ax
; X86-NEXT: movl %eax, %edx ; X86-NEXT: movl %eax, %edx
; X86-NEXT: andl $3855, %edx # imm = 0xF0F ; X86-NEXT: andl $3855, %edx # imm = 0xF0F
; X86-NEXT: shll $4, %edx ; X86-NEXT: shll $4, %edx
; X86-NEXT: andl $61680, %eax # imm = 0xF0F0 ; X86-NEXT: andl $61680, %eax # imm = 0xF0F0
; X86-NEXT: shrl $4, %eax ; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %edx, %eax ; X86-NEXT: orl %edx, %eax
; X86-NEXT: movl %eax, %edx ; X86-NEXT: movl %eax, %edx
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ret i24 %b ret i24 %b
} }
declare i16 @llvm.bitreverse.i16(i16) readnone declare i16 @llvm.bitreverse.i16(i16) readnone
define i16 @test_bitreverse_i16(i16 %a) nounwind { define i16 @test_bitreverse_i16(i16 %a) nounwind {
; X86-LABEL: test_bitreverse_i16: ; X86-LABEL: test_bitreverse_i16:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: movw {{[0-9]+}}(%esp), %ax ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: rolw $8, %ax ; X86-NEXT: rolw $8, %ax
; X86-NEXT: movl %eax, %ecx ; X86-NEXT: movl %eax, %ecx
; X86-NEXT: andl $3855, %ecx # imm = 0xF0F ; X86-NEXT: andl $3855, %ecx # imm = 0xF0F
; X86-NEXT: shll $4, %ecx ; X86-NEXT: shll $4, %ecx
; X86-NEXT: andl $61680, %eax # imm = 0xF0F0 ; X86-NEXT: andl $61680, %eax # imm = 0xF0F0
; X86-NEXT: shrl $4, %eax ; X86-NEXT: shrl $4, %eax
; X86-NEXT: orl %ecx, %eax ; X86-NEXT: orl %ecx, %eax
; X86-NEXT: movl %eax, %ecx ; X86-NEXT: movl %eax, %ecx
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llvm/test/CodeGen/X86/cmov.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB3_2 ; CHECK-NEXT: je .LBB3_2
; CHECK-NEXT: # BB#1: # %bb.i.i.i ; CHECK-NEXT: # BB#1: # %bb.i.i.i
; CHECK-NEXT: movb {{.*}}(%rip), %cl ; CHECK-NEXT: movb {{.*}}(%rip), %cl
; CHECK-NEXT: .LBB3_2: # %func_4.exit.i ; CHECK-NEXT: .LBB3_2: # %func_4.exit.i
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: testb %dl, %dl ; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: setne %bl ; CHECK-NEXT: setne %bl
; CHECK-NEXT: movb %al, %cl ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: je .LBB3_4 ; CHECK-NEXT: je .LBB3_4
; CHECK-NEXT: # BB#3: # %func_4.exit.i ; CHECK-NEXT: # BB#3: # %func_4.exit.i
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: .LBB3_4: # %func_4.exit.i ; CHECK-NEXT: .LBB3_4: # %func_4.exit.i
; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB3_7 ; CHECK-NEXT: je .LBB3_7
; CHECK-NEXT: # BB#5: # %func_4.exit.i ; CHECK-NEXT: # BB#5: # %func_4.exit.i
; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: jne .LBB3_7 ; CHECK-NEXT: jne .LBB3_7
; CHECK-NEXT: # BB#6: # %bb.i.i ; CHECK-NEXT: # BB#6: # %bb.i.i
; CHECK-NEXT: movb {{.*}}(%rip), %cl ; CHECK-NEXT: movb {{.*}}(%rip), %cl
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: movb %al, %cl ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: .LBB3_7: # %func_1.exit ; CHECK-NEXT: .LBB3_7: # %func_1.exit
; CHECK-NEXT: movb %cl, {{.*}}(%rip) ; CHECK-NEXT: movb %cl, {{.*}}(%rip)
; CHECK-NEXT: movzbl %cl, %esi ; CHECK-NEXT: movzbl %cl, %esi
; CHECK-NEXT: movl $_2E_str, %edi ; CHECK-NEXT: movl $_2E_str, %edi
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq printf ; CHECK-NEXT: callq printf
; CHECK-NEXT: movl %ebx, %eax ; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
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; Don't try to use a 16-bit conditional move to do an 8-bit select, ; Don't try to use a 16-bit conditional move to do an 8-bit select,
; because it isn't worth it. Just use a branch instead. ; because it isn't worth it. Just use a branch instead.
define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind { define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
; CHECK-LABEL: test7: ; CHECK-LABEL: test7:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB6_2 ; CHECK-NEXT: jne .LBB6_2
; CHECK-NEXT: # BB#1: ; CHECK-NEXT: # BB#1:
; CHECK-NEXT: movb %dl, %sil ; CHECK-NEXT: movl %edx, %esi
; CHECK-NEXT: .LBB6_2: ; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%d = select i1 %c, i8 %a, i8 %b %d = select i1 %c, i8 %a, i8 %b
ret i8 %d ret i8 %d
} }
define i32 @smin(i32 %x) { define i32 @smin(i32 %x) {
Show All 13 Lines

llvm/test/CodeGen/X86/fixup-bw-inst.mir

  • This file was added.
# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass x86-fixup-bw-insts %s -o - | FileCheck %s
--- |
define void @test1() { ret void }
define void @test2() { ret void }
define i16 @test3(i16* readonly %p) {
; Keep original IR to show how the situation like this might happen
; due to preceding CG passes.
;
; %0 is used in %if.end BB (before tail-duplication), so its
; corresponding super-register (EAX) is live-in into that BB (%if.end)
; and also has an EAX<imp-def> flag. Make sure that we still change
; the movw into movzwl because EAX is not live before the load (which
; can be seen by the fact that EAX<imp-use> flag is missing).
entry:
%tobool = icmp eq i16* %p, null
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
%0 = load i16, i16* %p, align 2
br label %if.end
if.end: ; preds = %if.then, %entry
%i.0 = phi i16 [ %0, %if.then ], [ 0, %entry ]
ret i16 %i.0
}
...
---
# CHECK-LABEL: name: test1
name: test1
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '%rax' }
frameInfo:
stackSize: 0
fixedStack:
stack:
constants:
# Verify that "movw (%rax), %ax" is changed to "movzwl (%rax), %rax".
#
# For that to happen, the liveness information after the MOV16rm
# instruction should be used, not before it because %rax is live
# before the MOV and is killed by it.
body: |
bb.0:
liveins: %rax
%ax = MOV16rm killed %rax, 1, _, 0, _
; CHECK: %eax = MOVZX32rm16 killed %rax
RETQ %ax
...
---
# CHECK-LABEL: name: test2
name: test2
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '%rax' }
frameInfo:
stackSize: 0
fixedStack:
stack:
constants:
# Imp-use of any super-register means the register is live before the MOV
body: |
bb.0:
liveins: %dl, %rbx, %rcx, %r14
%cl = MOV8rr killed %dl, implicit killed %rcx, implicit-def %rcx
; CHECK: %cl = MOV8rr killed %dl, implicit killed %rcx, implicit-def %rcx
JMP_1 %bb.1
bb.1:
liveins: %rcx
RETQ %cl
...
---
# CHECK-LABEL: name: test3
name: test3
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '%rdi', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
# After MOV16rm the whole %eax is not *really* live, as can be seen by
# missing implicit-uses of it in that MOV. Make sure that MOV is
# transformed into MOVZX.
# See the comment near the original IR on what preceding decisions can
# lead to that.
body: |
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2.if.then(0x50000000)
liveins: %rdi
TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.1, implicit %eflags
bb.2.if.then:
liveins: %rdi
%ax = MOV16rm killed %rdi, 1, _, 0, _, implicit-def %eax :: (load 2 from %ir.p)
; CHECK: %eax = MOVZX32rm16 killed %rdi, 1, _, 0, _, implicit-def %eax :: (load 2 from %ir.p)
%ax = KILL %ax, implicit killed %eax
RETQ %ax
bb.1:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
%ax = KILL %ax, implicit killed %eax
RETQ %ax
...

llvm/test/CodeGen/X86/pr32345.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; 6860-NEXT: popl %edi ; 6860-NEXT: popl %edi
; 6860-NEXT: popl %ebx ; 6860-NEXT: popl %ebx
; 6860-NEXT: popl %ebp ; 6860-NEXT: popl %ebp
; 6860-NEXT: retl ; 6860-NEXT: retl
; ;
; X64-LABEL: foo: ; X64-LABEL: foo:
; X64: # BB#0: # %bb ; X64: # BB#0: # %bb
; X64-NEXT: movzwl {{.*}}(%rip), %ecx ; X64-NEXT: movzwl {{.*}}(%rip), %ecx
; X64-NEXT: movw {{.*}}(%rip), %ax ; X64-NEXT: movzwl {{.*}}(%rip), %eax
; X64-NEXT: xorw %cx, %ax ; X64-NEXT: xorw %cx, %ax
; X64-NEXT: xorl %ecx, %eax ; X64-NEXT: xorl %ecx, %eax
; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: movzwl %ax, %eax
; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; X64-NEXT: addl $-16610, %ecx # imm = 0xBF1E ; X64-NEXT: addl $-16610, %ecx # imm = 0xBF1E
; X64-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> ; X64-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
; X64-NEXT: shrq %cl, %rax ; X64-NEXT: shrq %cl, %rax
; X64-NEXT: movb %al, (%rax) ; X64-NEXT: movb %al, (%rax)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; 686-LABEL: foo: ; 686-LABEL: foo:
; 686: # BB#0: # %bb ; 686: # BB#0: # %bb
; 686-NEXT: pushl %ebp ; 686-NEXT: pushl %ebp
; 686-NEXT: .Lcfi0: ; 686-NEXT: .Lcfi0:
; 686-NEXT: .cfi_def_cfa_offset 8 ; 686-NEXT: .cfi_def_cfa_offset 8
; 686-NEXT: .Lcfi1: ; 686-NEXT: .Lcfi1:
; 686-NEXT: .cfi_offset %ebp, -8 ; 686-NEXT: .cfi_offset %ebp, -8
; 686-NEXT: movl %esp, %ebp ; 686-NEXT: movl %esp, %ebp
; 686-NEXT: .Lcfi2: ; 686-NEXT: .Lcfi2:
; 686-NEXT: .cfi_def_cfa_register %ebp ; 686-NEXT: .cfi_def_cfa_register %ebp
; 686-NEXT: andl $-8, %esp ; 686-NEXT: andl $-8, %esp
; 686-NEXT: subl $8, %esp ; 686-NEXT: subl $8, %esp
; 686-NEXT: movzwl var_27, %ecx ; 686-NEXT: movzwl var_27, %ecx
; 686-NEXT: movw var_22, %ax ; 686-NEXT: movzwl var_22, %eax
; 686-NEXT: xorw %cx, %ax ; 686-NEXT: xorw %cx, %ax
; 686-NEXT: xorl %ecx, %eax ; 686-NEXT: xorl %ecx, %eax
; 686-NEXT: movzwl %ax, %eax ; 686-NEXT: movzwl %ax, %eax
; 686-NEXT: movl %eax, (%esp) ; 686-NEXT: movl %eax, (%esp)
; 686-NEXT: movl $0, {{[0-9]+}}(%esp) ; 686-NEXT: movl $0, {{[0-9]+}}(%esp)
; 686-NEXT: addl $-16610, %ecx # imm = 0xBF1E ; 686-NEXT: addl $-16610, %ecx # imm = 0xBF1E
; 686-NEXT: xorl %edx, %edx ; 686-NEXT: xorl %edx, %edx
; 686-NEXT: shrdl %cl, %edx, %eax ; 686-NEXT: shrdl %cl, %edx, %eax
Show All 39 Lines

llvm/test/CodeGen/X86/pr32420.ll

Show All 10 Lines
; CHECK-LABEL: PR32420: ; CHECK-LABEL: PR32420:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movq _a@{{.*}}(%rip), %rax ; CHECK-NEXT: movq _a@{{.*}}(%rip), %rax
; CHECK-NEXT: movzwl (%rax), %eax ; CHECK-NEXT: movzwl (%rax), %eax
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shll $12, %ecx ; CHECK-NEXT: shll $12, %ecx
; CHECK-NEXT: sarw $12, %cx ; CHECK-NEXT: sarw $12, %cx
; CHECK-NEXT: movq _b@{{.*}}(%rip), %rdx ; CHECK-NEXT: movq _b@{{.*}}(%rip), %rdx
; CHECK-NEXT: movw %cx, %si ; CHECK-NEXT: movl %ecx, %esi
; CHECK-NEXT: orw (%rdx), %si ; CHECK-NEXT: orw (%rdx), %si
; CHECK-NEXT: andl %ecx, %esi ; CHECK-NEXT: andl %ecx, %esi
; CHECK-NEXT: movw %si, (%rdx) ; CHECK-NEXT: movw %si, (%rdx)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%load2 = load i16, i16* @a, align 4 %load2 = load i16, i16* @a, align 4
%shl3 = shl i16 %load2, 12 %shl3 = shl i16 %load2, 12
%ashr4 = ashr i16 %shl3, 12 %ashr4 = ashr i16 %shl3, 12
%t2 = load volatile i16, i16* @b, align 4 %t2 = load volatile i16, i16* @b, align 4
Show All 9 Lines

llvm/test/CodeGen/X86/pr34137.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
@var_3 = external global i16, align 2 @var_3 = external global i16, align 2
@var_13 = external global i16, align 2 @var_13 = external global i16, align 2
@var_212 = external global i64, align 8 @var_212 = external global i64, align 8
define void @pr34127() { define void @pr34127() {
; CHECK-LABEL: pr34127: ; CHECK-LABEL: pr34127:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: movzwl {{.*}}(%rip), %eax ; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
; CHECK-NEXT: movw {{.*}}(%rip), %cx ; CHECK-NEXT: movzwl {{.*}}(%rip), %ecx
; CHECK-NEXT: andw %ax, %cx ; CHECK-NEXT: andw %ax, %cx
; CHECK-NEXT: andl %eax, %ecx ; CHECK-NEXT: andl %eax, %ecx
; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: testw %cx, %cx ; CHECK-NEXT: testw %cx, %cx
; CHECK-NEXT: sete %dl ; CHECK-NEXT: sete %dl
; CHECK-NEXT: andl %eax, %edx ; CHECK-NEXT: andl %eax, %edx
; CHECK-NEXT: movq %rdx, {{.*}}(%rip) ; CHECK-NEXT: movq %rdx, {{.*}}(%rip)
Show All 33 Lines

llvm/test/CodeGen/X86/select.ll

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; ;
; MCU-LABEL: test5: ; MCU-LABEL: test5:
; MCU: # BB#0: ; MCU: # BB#0:
; MCU-NEXT: pushl %esi ; MCU-NEXT: pushl %esi
; MCU-NEXT: movl {{[0-9]+}}(%esp), %esi ; MCU-NEXT: movl {{[0-9]+}}(%esp), %esi
; MCU-NEXT: testb $1, %al ; MCU-NEXT: testb $1, %al
; MCU-NEXT: jne .LBB4_2 ; MCU-NEXT: jne .LBB4_2
; MCU-NEXT: # BB#1: ; MCU-NEXT: # BB#1:
; MCU-NEXT: movw {{[0-9]+}}(%esp), %cx ; MCU-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; MCU-NEXT: movw {{[0-9]+}}(%esp), %dx ; MCU-NEXT: movzwl {{[0-9]+}}(%esp), %edx
; MCU-NEXT: .LBB4_2: ; MCU-NEXT: .LBB4_2:
; MCU-NEXT: movw %cx, 2(%esi) ; MCU-NEXT: movw %cx, 2(%esi)
; MCU-NEXT: movw %dx, (%esi) ; MCU-NEXT: movw %dx, (%esi)
; MCU-NEXT: popl %esi ; MCU-NEXT: popl %esi
; MCU-NEXT: retl ; MCU-NEXT: retl
%x = select i1 %c, <2 x i16> %a, <2 x i16> %b %x = select i1 %c, <2 x i16> %a, <2 x i16> %b
store <2 x i16> %x, <2 x i16>* %p store <2 x i16> %x, <2 x i16>* %p
ret void ret void
▲ Show 20 Lines • Show All 990 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 1,396 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%ext = extractelement <8 x i16> %arg0, i32 1 %ext = extractelement <8 x i16> %arg0, i32 1
%res = zext i16 %ext to i32 %res = zext i16 %ext to i32
ret i32 %res ret i32 %res
} }
define <2 x i64> @test_mm_insert_epi16(<2 x i64> %a0, i16 %a1) nounwind { define <2 x i64> @test_mm_insert_epi16(<2 x i64> %a0, i16 %a1) nounwind {
; X32-LABEL: test_mm_insert_epi16: ; X32-LABEL: test_mm_insert_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pinsrw $1, %eax, %xmm0 ; X32-NEXT: pinsrw $1, %eax, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm_insert_epi16: ; X64-LABEL: test_mm_insert_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pinsrw $1, %edi, %xmm0 ; X64-NEXT: pinsrw $1, %edi, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%arg0 = bitcast <2 x i64> %a0 to <8 x i16> %arg0 = bitcast <2 x i64> %a0 to <8 x i16>
▲ Show 20 Lines • Show All 769 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res15 = insertelement <16 x i8> %res14, i8 %a0 , i32 15 %res15 = insertelement <16 x i8> %res14, i8 %a0 , i32 15
%res = bitcast <16 x i8> %res15 to <2 x i64> %res = bitcast <16 x i8> %res15 to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64> @test_mm_set_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { define <2 x i64> @test_mm_set_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
; X32-LABEL: test_mm_set_epi16: ; X32-LABEL: test_mm_set_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm1 ; X32-NEXT: movd %eax, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm2 ; X32-NEXT: movd %eax, %xmm2
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm3 ; X32-NEXT: movd %eax, %xmm3
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm4 ; X32-NEXT: movd %eax, %xmm4
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm5 ; X32-NEXT: movd %eax, %xmm5
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm6 ; X32-NEXT: movd %eax, %xmm6
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm7 ; X32-NEXT: movd %eax, %xmm7
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm0 ; X32-NEXT: movd %eax, %xmm0
; X32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; X32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
; X32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; X32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; X32-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3]
; X32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3]
; X32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1] ; X32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1]
; X32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0] ; X32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm_set_epi16: ; X64-LABEL: test_mm_set_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: movw {{[0-9]+}}(%rsp), %r10w ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: movd %edi, %xmm0 ; X64-NEXT: movd %edi, %xmm0
; X64-NEXT: movd %esi, %xmm1 ; X64-NEXT: movd %esi, %xmm1
; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; X64-NEXT: movd %edx, %xmm0 ; X64-NEXT: movd %edx, %xmm0
; X64-NEXT: movd %ecx, %xmm2 ; X64-NEXT: movd %ecx, %xmm2
; X64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; X64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X64-NEXT: movd %r8d, %xmm0 ; X64-NEXT: movd %r8d, %xmm0
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res15 = insertelement <16 x i8> %res14, i8 %a0, i32 15 %res15 = insertelement <16 x i8> %res14, i8 %a0, i32 15
%res = bitcast <16 x i8> %res15 to <2 x i64> %res = bitcast <16 x i8> %res15 to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64> @test_mm_set1_epi16(i16 %a0) nounwind { define <2 x i64> @test_mm_set1_epi16(i16 %a0) nounwind {
; X32-LABEL: test_mm_set1_epi16: ; X32-LABEL: test_mm_set1_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm0 ; X32-NEXT: movd %eax, %xmm0
; X32-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] ; X32-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm_set1_epi16: ; X64-LABEL: test_mm_set1_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: movd %edi, %xmm0 ; X64-NEXT: movd %edi, %xmm0
▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res15 = insertelement <16 x i8> %res14, i8 %a15, i32 15 %res15 = insertelement <16 x i8> %res14, i8 %a15, i32 15
%res = bitcast <16 x i8> %res15 to <2 x i64> %res = bitcast <16 x i8> %res15 to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64> @test_mm_setr_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { define <2 x i64> @test_mm_setr_epi16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
; X32-LABEL: test_mm_setr_epi16: ; X32-LABEL: test_mm_setr_epi16:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm1 ; X32-NEXT: movd %eax, %xmm1
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm2 ; X32-NEXT: movd %eax, %xmm2
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm3 ; X32-NEXT: movd %eax, %xmm3
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm4 ; X32-NEXT: movd %eax, %xmm4
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm5 ; X32-NEXT: movd %eax, %xmm5
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm6 ; X32-NEXT: movd %eax, %xmm6
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm7 ; X32-NEXT: movd %eax, %xmm7
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm0 ; X32-NEXT: movd %eax, %xmm0
; X32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; X32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
; X32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; X32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; X32-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3]
; X32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3] ; X32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3]
; X32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1] ; X32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1]
; X32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0] ; X32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm_setr_epi16: ; X64-LABEL: test_mm_setr_epi16:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: movw {{[0-9]+}}(%rsp), %ax ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
; X64-NEXT: movw {{[0-9]+}}(%rsp), %r10w ; X64-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
; X64-NEXT: movd %eax, %xmm0 ; X64-NEXT: movd %eax, %xmm0
; X64-NEXT: movd %r10d, %xmm1 ; X64-NEXT: movd %r10d, %xmm1
; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; X64-NEXT: movd %r9d, %xmm0 ; X64-NEXT: movd %r9d, %xmm0
; X64-NEXT: movd %r8d, %xmm2 ; X64-NEXT: movd %r8d, %xmm2
; X64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; X64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X64-NEXT: movd %ecx, %xmm0 ; X64-NEXT: movd %ecx, %xmm0
▲ Show 20 Lines • Show All 1,255 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-half-conversions.ll

Show First 20 Lines • Show All 4,297 Lines • ▼ Show 20 Lines
define <2 x i16> @cvt_2f64_to_2i16(<2 x double> %a0) nounwind { define <2 x i16> @cvt_2f64_to_2i16(<2 x double> %a0) nounwind {
; ALL-LABEL: cvt_2f64_to_2i16: ; ALL-LABEL: cvt_2f64_to_2i16:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: pushq %rbx ; ALL-NEXT: pushq %rbx
; ALL-NEXT: subq $16, %rsp ; ALL-NEXT: subq $16, %rsp
; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; ALL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; ALL-NEXT: callq __truncdfhf2 ; ALL-NEXT: callq __truncdfhf2
; ALL-NEXT: movw %ax, %bx ; ALL-NEXT: movl %eax, %ebx
; ALL-NEXT: shll $16, %ebx ; ALL-NEXT: shll $16, %ebx
; ALL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; ALL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; ALL-NEXT: callq __truncdfhf2 ; ALL-NEXT: callq __truncdfhf2
; ALL-NEXT: movzwl %ax, %eax ; ALL-NEXT: movzwl %ax, %eax
; ALL-NEXT: orl %ebx, %eax ; ALL-NEXT: orl %ebx, %eax
; ALL-NEXT: vmovd %eax, %xmm0 ; ALL-NEXT: vmovd %eax, %xmm0
; ALL-NEXT: addq $16, %rsp ; ALL-NEXT: addq $16, %rsp
; ALL-NEXT: popq %rbx ; ALL-NEXT: popq %rbx
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = fptrunc <2 x double> %a0 to <2 x half> %1 = fptrunc <2 x double> %a0 to <2 x half>
%2 = bitcast <2 x half> %1 to <2 x i16> %2 = bitcast <2 x half> %1 to <2 x i16>
ret <2 x i16> %2 ret <2 x i16> %2
} }
define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind { define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind {
; AVX1-LABEL: cvt_4f64_to_4i16: ; AVX1-LABEL: cvt_4f64_to_4i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: subq $40, %rsp ; AVX1-NEXT: subq $40, %rsp
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %r14d ; AVX1-NEXT: movzwl %ax, %r14d
; AVX1-NEXT: orl %ebx, %r14d ; AVX1-NEXT: orl %ebx, %r14d
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax ; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax ; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax ; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r14, %rax ; AVX1-NEXT: orq %r14, %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: addq $40, %rsp ; AVX1-NEXT: addq $40, %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: cvt_4f64_to_4i16: ; AVX2-LABEL: cvt_4f64_to_4i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $40, %rsp ; AVX2-NEXT: subq $40, %rsp
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r14d ; AVX2-NEXT: movzwl %ax, %r14d
; AVX2-NEXT: orl %ebx, %r14d ; AVX2-NEXT: orl %ebx, %r14d
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax ; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebx, %eax ; AVX2-NEXT: orl %ebx, %eax
; AVX2-NEXT: shlq $32, %rax ; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %r14, %rax ; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: addq $40, %rsp ; AVX2-NEXT: addq $40, %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: cvt_4f64_to_4i16: ; AVX512-LABEL: cvt_4f64_to_4i16:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: pushq %r14 ; AVX512-NEXT: pushq %r14
; AVX512-NEXT: pushq %rbx ; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: subq $40, %rsp ; AVX512-NEXT: subq $40, %rsp
; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movw %ax, %bx ; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %r14d ; AVX512-NEXT: movzwl %ax, %r14d
; AVX512-NEXT: orl %ebx, %r14d ; AVX512-NEXT: orl %ebx, %r14d
; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movw %ax, %bx ; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %eax ; AVX512-NEXT: movzwl %ax, %eax
; AVX512-NEXT: orl %ebx, %eax ; AVX512-NEXT: orl %ebx, %eax
; AVX512-NEXT: shlq $32, %rax ; AVX512-NEXT: shlq $32, %rax
; AVX512-NEXT: orq %r14, %rax ; AVX512-NEXT: orq %r14, %rax
; AVX512-NEXT: vmovq %rax, %xmm0 ; AVX512-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: subq $40, %rsp ; AVX1-NEXT: subq $40, %rsp
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %r14d ; AVX1-NEXT: movzwl %ax, %r14d
; AVX1-NEXT: orl %ebx, %r14d ; AVX1-NEXT: orl %ebx, %r14d
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax ; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax ; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax ; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r14, %rax ; AVX1-NEXT: orq %r14, %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: addq $40, %rsp ; AVX1-NEXT: addq $40, %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: cvt_4f64_to_8i16_undef: ; AVX2-LABEL: cvt_4f64_to_8i16_undef:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $40, %rsp ; AVX2-NEXT: subq $40, %rsp
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r14d ; AVX2-NEXT: movzwl %ax, %r14d
; AVX2-NEXT: orl %ebx, %r14d ; AVX2-NEXT: orl %ebx, %r14d
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax ; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebx, %eax ; AVX2-NEXT: orl %ebx, %eax
; AVX2-NEXT: shlq $32, %rax ; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %r14, %rax ; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; AVX2-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-NEXT: addq $40, %rsp ; AVX2-NEXT: addq $40, %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: cvt_4f64_to_8i16_undef: ; AVX512F-LABEL: cvt_4f64_to_8i16_undef:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %r14 ; AVX512F-NEXT: pushq %r14
; AVX512F-NEXT: pushq %rbx ; AVX512F-NEXT: pushq %rbx
; AVX512F-NEXT: subq $40, %rsp ; AVX512F-NEXT: subq $40, %rsp
; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bx ; AVX512F-NEXT: movl %eax, %ebx
; AVX512F-NEXT: shll $16, %ebx ; AVX512F-NEXT: shll $16, %ebx
; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %r14d ; AVX512F-NEXT: movzwl %ax, %r14d
; AVX512F-NEXT: orl %ebx, %r14d ; AVX512F-NEXT: orl %ebx, %r14d
; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bx ; AVX512F-NEXT: movl %eax, %ebx
; AVX512F-NEXT: shll $16, %ebx ; AVX512F-NEXT: shll $16, %ebx
; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %eax ; AVX512F-NEXT: movzwl %ax, %eax
; AVX512F-NEXT: orl %ebx, %eax ; AVX512F-NEXT: orl %ebx, %eax
; AVX512F-NEXT: shlq $32, %rax ; AVX512F-NEXT: shlq $32, %rax
; AVX512F-NEXT: orq %r14, %rax ; AVX512F-NEXT: orq %r14, %rax
; AVX512F-NEXT: vmovq %rax, %xmm0 ; AVX512F-NEXT: vmovq %rax, %xmm0
; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512F-NEXT: addq $40, %rsp ; AVX512F-NEXT: addq $40, %rsp
; AVX512F-NEXT: popq %rbx ; AVX512F-NEXT: popq %rbx
; AVX512F-NEXT: popq %r14 ; AVX512F-NEXT: popq %r14
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: cvt_4f64_to_8i16_undef: ; AVX512VL-LABEL: cvt_4f64_to_8i16_undef:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: pushq %r14 ; AVX512VL-NEXT: pushq %r14
; AVX512VL-NEXT: pushq %rbx ; AVX512VL-NEXT: pushq %rbx
; AVX512VL-NEXT: subq $40, %rsp ; AVX512VL-NEXT: subq $40, %rsp
; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bx ; AVX512VL-NEXT: movl %eax, %ebx
; AVX512VL-NEXT: shll $16, %ebx ; AVX512VL-NEXT: shll $16, %ebx
; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %r14d ; AVX512VL-NEXT: movzwl %ax, %r14d
; AVX512VL-NEXT: orl %ebx, %r14d ; AVX512VL-NEXT: orl %ebx, %r14d
; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bx ; AVX512VL-NEXT: movl %eax, %ebx
; AVX512VL-NEXT: shll $16, %ebx ; AVX512VL-NEXT: shll $16, %ebx
; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %eax ; AVX512VL-NEXT: movzwl %ax, %eax
; AVX512VL-NEXT: orl %ebx, %eax ; AVX512VL-NEXT: orl %ebx, %eax
; AVX512VL-NEXT: shlq $32, %rax ; AVX512VL-NEXT: shlq $32, %rax
; AVX512VL-NEXT: orq %r14, %rax ; AVX512VL-NEXT: orq %r14, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm0 ; AVX512VL-NEXT: vmovq %rax, %xmm0
Show All 14 Lines
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: subq $40, %rsp ; AVX1-NEXT: subq $40, %rsp
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %r14d ; AVX1-NEXT: movzwl %ax, %r14d
; AVX1-NEXT: orl %ebx, %r14d ; AVX1-NEXT: orl %ebx, %r14d
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax ; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax ; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax ; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r14, %rax ; AVX1-NEXT: orq %r14, %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: addq $40, %rsp ; AVX1-NEXT: addq $40, %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: cvt_4f64_to_8i16_zero: ; AVX2-LABEL: cvt_4f64_to_8i16_zero:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $40, %rsp ; AVX2-NEXT: subq $40, %rsp
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r14d ; AVX2-NEXT: movzwl %ax, %r14d
; AVX2-NEXT: orl %ebx, %r14d ; AVX2-NEXT: orl %ebx, %r14d
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax ; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebx, %eax ; AVX2-NEXT: orl %ebx, %eax
; AVX2-NEXT: shlq $32, %rax ; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %r14, %rax ; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero ; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-NEXT: addq $40, %rsp ; AVX2-NEXT: addq $40, %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: cvt_4f64_to_8i16_zero: ; AVX512F-LABEL: cvt_4f64_to_8i16_zero:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %r14 ; AVX512F-NEXT: pushq %r14
; AVX512F-NEXT: pushq %rbx ; AVX512F-NEXT: pushq %rbx
; AVX512F-NEXT: subq $40, %rsp ; AVX512F-NEXT: subq $40, %rsp
; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bx ; AVX512F-NEXT: movl %eax, %ebx
; AVX512F-NEXT: shll $16, %ebx ; AVX512F-NEXT: shll $16, %ebx
; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %r14d ; AVX512F-NEXT: movzwl %ax, %r14d
; AVX512F-NEXT: orl %ebx, %r14d ; AVX512F-NEXT: orl %ebx, %r14d
; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bx ; AVX512F-NEXT: movl %eax, %ebx
; AVX512F-NEXT: shll $16, %ebx ; AVX512F-NEXT: shll $16, %ebx
; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %eax ; AVX512F-NEXT: movzwl %ax, %eax
; AVX512F-NEXT: orl %ebx, %eax ; AVX512F-NEXT: orl %ebx, %eax
; AVX512F-NEXT: shlq $32, %rax ; AVX512F-NEXT: shlq $32, %rax
; AVX512F-NEXT: orq %r14, %rax ; AVX512F-NEXT: orq %r14, %rax
; AVX512F-NEXT: vmovq %rax, %xmm0 ; AVX512F-NEXT: vmovq %rax, %xmm0
; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero ; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero
; AVX512F-NEXT: addq $40, %rsp ; AVX512F-NEXT: addq $40, %rsp
; AVX512F-NEXT: popq %rbx ; AVX512F-NEXT: popq %rbx
; AVX512F-NEXT: popq %r14 ; AVX512F-NEXT: popq %r14
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: cvt_4f64_to_8i16_zero: ; AVX512VL-LABEL: cvt_4f64_to_8i16_zero:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: pushq %r14 ; AVX512VL-NEXT: pushq %r14
; AVX512VL-NEXT: pushq %rbx ; AVX512VL-NEXT: pushq %rbx
; AVX512VL-NEXT: subq $40, %rsp ; AVX512VL-NEXT: subq $40, %rsp
; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bx ; AVX512VL-NEXT: movl %eax, %ebx
; AVX512VL-NEXT: shll $16, %ebx ; AVX512VL-NEXT: shll $16, %ebx
; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %r14d ; AVX512VL-NEXT: movzwl %ax, %r14d
; AVX512VL-NEXT: orl %ebx, %r14d ; AVX512VL-NEXT: orl %ebx, %r14d
; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bx ; AVX512VL-NEXT: movl %eax, %ebx
; AVX512VL-NEXT: shll $16, %ebx ; AVX512VL-NEXT: shll $16, %ebx
; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %eax ; AVX512VL-NEXT: movzwl %ax, %eax
; AVX512VL-NEXT: orl %ebx, %eax ; AVX512VL-NEXT: orl %ebx, %eax
; AVX512VL-NEXT: shlq $32, %rax ; AVX512VL-NEXT: shlq $32, %rax
; AVX512VL-NEXT: orq %r14, %rax ; AVX512VL-NEXT: orq %r14, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm0 ; AVX512VL-NEXT: vmovq %rax, %xmm0
Show All 18 Lines
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: subq $64, %rsp ; AVX1-NEXT: subq $64, %rsp
; AVX1-NEXT: vmovups %ymm1, (%rsp) # 32-byte Spill ; AVX1-NEXT: vmovups %ymm1, (%rsp) # 32-byte Spill
; AVX1-NEXT: vmovupd %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill ; AVX1-NEXT: vmovupd %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %r15d ; AVX1-NEXT: movzwl %ax, %r15d
; AVX1-NEXT: orl %ebx, %r15d ; AVX1-NEXT: orl %ebx, %r15d
; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %r14d ; AVX1-NEXT: movzwl %ax, %r14d
; AVX1-NEXT: orl %ebx, %r14d ; AVX1-NEXT: orl %ebx, %r14d
; AVX1-NEXT: shlq $32, %r14 ; AVX1-NEXT: shlq $32, %r14
; AVX1-NEXT: orq %r15, %r14 ; AVX1-NEXT: orq %r15, %r14
; AVX1-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload ; AVX1-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: # xmm0 = mem[1,0] ; AVX1-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %r15d ; AVX1-NEXT: movzwl %ax, %r15d
; AVX1-NEXT: orl %ebx, %r15d ; AVX1-NEXT: orl %ebx, %r15d
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bx ; AVX1-NEXT: movl %eax, %ebx
; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: shll $16, %ebx
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax ; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax ; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax ; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r15, %rax ; AVX1-NEXT: orq %r15, %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $64, %rsp ; AVX2-NEXT: subq $64, %rsp
; AVX2-NEXT: vmovups %ymm1, (%rsp) # 32-byte Spill ; AVX2-NEXT: vmovups %ymm1, (%rsp) # 32-byte Spill
; AVX2-NEXT: vmovupd %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill ; AVX2-NEXT: vmovupd %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r15d ; AVX2-NEXT: movzwl %ax, %r15d
; AVX2-NEXT: orl %ebx, %r15d ; AVX2-NEXT: orl %ebx, %r15d
; AVX2-NEXT: vmovupd {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r14d ; AVX2-NEXT: movzwl %ax, %r14d
; AVX2-NEXT: orl %ebx, %r14d ; AVX2-NEXT: orl %ebx, %r14d
; AVX2-NEXT: shlq $32, %r14 ; AVX2-NEXT: shlq $32, %r14
; AVX2-NEXT: orq %r15, %r14 ; AVX2-NEXT: orq %r15, %r14
; AVX2-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload ; AVX2-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
; AVX2-NEXT: # xmm0 = mem[1,0] ; AVX2-NEXT: # xmm0 = mem[1,0]
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r15d ; AVX2-NEXT: movzwl %ax, %r15d
; AVX2-NEXT: orl %ebx, %r15d ; AVX2-NEXT: orl %ebx, %r15d
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bx ; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax ; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebx, %eax ; AVX2-NEXT: orl %ebx, %eax
; AVX2-NEXT: shlq $32, %rax ; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %r15, %rax ; AVX2-NEXT: orq %r15, %rax
; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vmovq %rax, %xmm0
Show All 10 Lines
; AVX512-NEXT: pushq %r15 ; AVX512-NEXT: pushq %r15
; AVX512-NEXT: pushq %r14 ; AVX512-NEXT: pushq %r14
; AVX512-NEXT: pushq %rbx ; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: subq $96, %rsp ; AVX512-NEXT: subq $96, %rsp
; AVX512-NEXT: vmovupd %zmm0, (%rsp) # 64-byte Spill ; AVX512-NEXT: vmovupd %zmm0, (%rsp) # 64-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movw %ax, %bx ; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload ; AVX512-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %r15d ; AVX512-NEXT: movzwl %ax, %r15d
; AVX512-NEXT: orl %ebx, %r15d ; AVX512-NEXT: orl %ebx, %r15d
; AVX512-NEXT: vmovupd (%rsp), %zmm0 # 64-byte Reload ; AVX512-NEXT: vmovupd (%rsp), %zmm0 # 64-byte Reload
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovapd %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill ; AVX512-NEXT: vmovapd %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movw %ax, %bx ; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload ; AVX512-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %r14d ; AVX512-NEXT: movzwl %ax, %r14d
; AVX512-NEXT: orl %ebx, %r14d ; AVX512-NEXT: orl %ebx, %r14d
; AVX512-NEXT: shlq $32, %r14 ; AVX512-NEXT: shlq $32, %r14
; AVX512-NEXT: orq %r15, %r14 ; AVX512-NEXT: orq %r15, %r14
; AVX512-NEXT: vmovupd (%rsp), %zmm0 # 64-byte Reload ; AVX512-NEXT: vmovupd (%rsp), %zmm0 # 64-byte Reload
; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm0 ; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm0
; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movw %ax, %bx ; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %r15d ; AVX512-NEXT: movzwl %ax, %r15d
; AVX512-NEXT: orl %ebx, %r15d ; AVX512-NEXT: orl %ebx, %r15d
; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movw %ax, %bx ; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %eax ; AVX512-NEXT: movzwl %ax, %eax
; AVX512-NEXT: orl %ebx, %eax ; AVX512-NEXT: orl %ebx, %eax
; AVX512-NEXT: shlq $32, %rax ; AVX512-NEXT: shlq $32, %rax
; AVX512-NEXT: orq %r15, %rax ; AVX512-NEXT: orq %r15, %rax
; AVX512-NEXT: vmovq %rax, %xmm0 ; AVX512-NEXT: vmovq %rax, %xmm0
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: subq $32, %rsp ; AVX1-NEXT: subq $32, %rsp
; AVX1-NEXT: movq %rdi, %r14 ; AVX1-NEXT: movq %rdi, %r14
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bp ; AVX1-NEXT: movl %eax, %ebp
; AVX1-NEXT: shll $16, %ebp ; AVX1-NEXT: shll $16, %ebp
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %ebx ; AVX1-NEXT: movzwl %ax, %ebx
; AVX1-NEXT: orl %ebp, %ebx ; AVX1-NEXT: orl %ebp, %ebx
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bp ; AVX1-NEXT: movl %eax, %ebp
; AVX1-NEXT: shll $16, %ebp ; AVX1-NEXT: shll $16, %ebp
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax ; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebp, %eax ; AVX1-NEXT: orl %ebp, %eax
; AVX1-NEXT: shlq $32, %rax ; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %rbx, %rax ; AVX1-NEXT: orq %rbx, %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $32, %rsp ; AVX2-NEXT: subq $32, %rsp
; AVX2-NEXT: movq %rdi, %r14 ; AVX2-NEXT: movq %rdi, %r14
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bp ; AVX2-NEXT: movl %eax, %ebp
; AVX2-NEXT: shll $16, %ebp ; AVX2-NEXT: shll $16, %ebp
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %ebx ; AVX2-NEXT: movzwl %ax, %ebx
; AVX2-NEXT: orl %ebp, %ebx ; AVX2-NEXT: orl %ebp, %ebx
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bp ; AVX2-NEXT: movl %eax, %ebp
; AVX2-NEXT: shll $16, %ebp ; AVX2-NEXT: shll $16, %ebp
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax ; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebp, %eax ; AVX2-NEXT: orl %ebp, %eax
; AVX2-NEXT: shlq $32, %rax ; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %rbx, %rax ; AVX2-NEXT: orq %rbx, %rax
; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX512F-NEXT: pushq %r14 ; AVX512F-NEXT: pushq %r14
; AVX512F-NEXT: pushq %rbx ; AVX512F-NEXT: pushq %rbx
; AVX512F-NEXT: subq $32, %rsp ; AVX512F-NEXT: subq $32, %rsp
; AVX512F-NEXT: movq %rdi, %r14 ; AVX512F-NEXT: movq %rdi, %r14
; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bp ; AVX512F-NEXT: movl %eax, %ebp
; AVX512F-NEXT: shll $16, %ebp ; AVX512F-NEXT: shll $16, %ebp
; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %ebx ; AVX512F-NEXT: movzwl %ax, %ebx
; AVX512F-NEXT: orl %ebp, %ebx ; AVX512F-NEXT: orl %ebp, %ebx
; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bp ; AVX512F-NEXT: movl %eax, %ebp
; AVX512F-NEXT: shll $16, %ebp ; AVX512F-NEXT: shll $16, %ebp
; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %eax ; AVX512F-NEXT: movzwl %ax, %eax
; AVX512F-NEXT: orl %ebp, %eax ; AVX512F-NEXT: orl %ebp, %eax
; AVX512F-NEXT: shlq $32, %rax ; AVX512F-NEXT: shlq $32, %rax
; AVX512F-NEXT: orq %rbx, %rax ; AVX512F-NEXT: orq %rbx, %rax
; AVX512F-NEXT: vmovq %rax, %xmm0 ; AVX512F-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX512VL-NEXT: pushq %r14 ; AVX512VL-NEXT: pushq %r14
; AVX512VL-NEXT: pushq %rbx ; AVX512VL-NEXT: pushq %rbx
; AVX512VL-NEXT: subq $32, %rsp ; AVX512VL-NEXT: subq $32, %rsp
; AVX512VL-NEXT: movq %rdi, %r14 ; AVX512VL-NEXT: movq %rdi, %r14
; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bp ; AVX512VL-NEXT: movl %eax, %ebp
; AVX512VL-NEXT: shll $16, %ebp ; AVX512VL-NEXT: shll $16, %ebp
; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %ebx ; AVX512VL-NEXT: movzwl %ax, %ebx
; AVX512VL-NEXT: orl %ebp, %ebx ; AVX512VL-NEXT: orl %ebp, %ebx
; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bp ; AVX512VL-NEXT: movl %eax, %ebp
; AVX512VL-NEXT: shll $16, %ebp ; AVX512VL-NEXT: shll $16, %ebp
; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %eax ; AVX512VL-NEXT: movzwl %ax, %eax
; AVX512VL-NEXT: orl %ebp, %eax ; AVX512VL-NEXT: orl %ebp, %eax
; AVX512VL-NEXT: shlq $32, %rax ; AVX512VL-NEXT: shlq $32, %rax
; AVX512VL-NEXT: orq %rbx, %rax ; AVX512VL-NEXT: orq %rbx, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm0 ; AVX512VL-NEXT: vmovq %rax, %xmm0
Show All 19 Lines
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: subq $32, %rsp ; AVX1-NEXT: subq $32, %rsp
; AVX1-NEXT: movq %rdi, %r14 ; AVX1-NEXT: movq %rdi, %r14
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bp ; AVX1-NEXT: movl %eax, %ebp
; AVX1-NEXT: shll $16, %ebp ; AVX1-NEXT: shll $16, %ebp
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %ebx ; AVX1-NEXT: movzwl %ax, %ebx
; AVX1-NEXT: orl %ebp, %ebx ; AVX1-NEXT: orl %ebp, %ebx
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movw %ax, %bp ; AVX1-NEXT: movl %eax, %ebp
; AVX1-NEXT: shll $16, %ebp ; AVX1-NEXT: shll $16, %ebp
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax ; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebp, %eax ; AVX1-NEXT: orl %ebp, %eax
; AVX1-NEXT: shlq $32, %rax ; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %rbx, %rax ; AVX1-NEXT: orq %rbx, %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $32, %rsp ; AVX2-NEXT: subq $32, %rsp
; AVX2-NEXT: movq %rdi, %r14 ; AVX2-NEXT: movq %rdi, %r14
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bp ; AVX2-NEXT: movl %eax, %ebp
; AVX2-NEXT: shll $16, %ebp ; AVX2-NEXT: shll $16, %ebp
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %ebx ; AVX2-NEXT: movzwl %ax, %ebx
; AVX2-NEXT: orl %ebp, %ebx ; AVX2-NEXT: orl %ebp, %ebx
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movw %ax, %bp ; AVX2-NEXT: movl %eax, %ebp
; AVX2-NEXT: shll $16, %ebp ; AVX2-NEXT: shll $16, %ebp
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax ; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebp, %eax ; AVX2-NEXT: orl %ebp, %eax
; AVX2-NEXT: shlq $32, %rax ; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %rbx, %rax ; AVX2-NEXT: orq %rbx, %rax
; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vmovq %rax, %xmm0
Show All 11 Lines
; AVX512F-NEXT: pushq %r14 ; AVX512F-NEXT: pushq %r14
; AVX512F-NEXT: pushq %rbx ; AVX512F-NEXT: pushq %rbx
; AVX512F-NEXT: subq $32, %rsp ; AVX512F-NEXT: subq $32, %rsp
; AVX512F-NEXT: movq %rdi, %r14 ; AVX512F-NEXT: movq %rdi, %r14
; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bp ; AVX512F-NEXT: movl %eax, %ebp
; AVX512F-NEXT: shll $16, %ebp ; AVX512F-NEXT: shll $16, %ebp
; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %ebx ; AVX512F-NEXT: movzwl %ax, %ebx
; AVX512F-NEXT: orl %ebp, %ebx ; AVX512F-NEXT: orl %ebp, %ebx
; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movw %ax, %bp ; AVX512F-NEXT: movl %eax, %ebp
; AVX512F-NEXT: shll $16, %ebp ; AVX512F-NEXT: shll $16, %ebp
; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %eax ; AVX512F-NEXT: movzwl %ax, %eax
; AVX512F-NEXT: orl %ebp, %eax ; AVX512F-NEXT: orl %ebp, %eax
; AVX512F-NEXT: shlq $32, %rax ; AVX512F-NEXT: shlq $32, %rax
; AVX512F-NEXT: orq %rbx, %rax ; AVX512F-NEXT: orq %rbx, %rax
; AVX512F-NEXT: vmovq %rax, %xmm0 ; AVX512F-NEXT: vmovq %rax, %xmm0
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; AVX512VL-NEXT: pushq %r14 ; AVX512VL-NEXT: pushq %r14
; AVX512VL-NEXT: pushq %rbx ; AVX512VL-NEXT: pushq %rbx
; AVX512VL-NEXT: subq $32, %rsp ; AVX512VL-NEXT: subq $32, %rsp
; AVX512VL-NEXT: movq %rdi, %r14 ; AVX512VL-NEXT: movq %rdi, %r14
; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bp ; AVX512VL-NEXT: movl %eax, %ebp
; AVX512VL-NEXT: shll $16, %ebp ; AVX512VL-NEXT: shll $16, %ebp
; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %ebx ; AVX512VL-NEXT: movzwl %ax, %ebx
; AVX512VL-NEXT: orl %ebp, %ebx ; AVX512VL-NEXT: orl %ebp, %ebx
; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload ; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movw %ax, %bp ; AVX512VL-NEXT: movl %eax, %ebp
; AVX512VL-NEXT: shll $16, %ebp ; AVX512VL-NEXT: shll $16, %ebp
; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %eax ; AVX512VL-NEXT: movzwl %ax, %eax
; AVX512VL-NEXT: orl %ebp, %eax ; AVX512VL-NEXT: orl %ebp, %eax
; AVX512VL-NEXT: shlq $32, %rax ; AVX512VL-NEXT: shlq $32, %rax
; AVX512VL-NEXT: orq %rbx, %rax ; AVX512VL-NEXT: orq %rbx, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm0 ; AVX512VL-NEXT: vmovq %rax, %xmm0
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