This is an archive of the discontinued LLVM Phabricator instance.

Differential D37114

AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
ClosedPublic

Authored by tstellar on Aug 24 2017, 11:09 AM.

Details

Reviewers
arsenm
Commits
rG3ae38d271e1b: AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
rL323709: AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
Summary

This is only used by R600.

Diff Detail

Event Timeline

tstellar created this revision.Aug 24 2017, 11:09 AM
Harbormaster completed remote builds in B9606: Diff 112585.Aug 24 2017, 11:09 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptAug 24 2017, 11:09 AM
arsenm accepted this revision.Aug 24 2017, 11:14 AM

LGTM

lib/Target/AMDGPU/CMakeLists.txt
16

Extra whitespace change

This revision is now accepted and ready to land.Aug 24 2017, 11:14 AM
Closed by commit rL323709: AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td (authored by tstellar). · Explain WhyJan 29 2018, 3:33 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
1 line
1 line
1 line

Diff 112585

lib/Target/AMDGPU/AMDGPUInstructions.td

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
} }
def FP16Denormals : Predicate<"Subtarget.hasFP16Denormals()">; def FP16Denormals : Predicate<"Subtarget.hasFP16Denormals()">;
def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">; def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">; def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">; def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>; def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
def u16ImmTarget : AsmOperandClass { def u16ImmTarget : AsmOperandClass {
let Name = "U16Imm"; let Name = "U16Imm";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
} }
def s16ImmTarget : AsmOperandClass { def s16ImmTarget : AsmOperandClass {
let Name = "S16Imm"; let Name = "S16Imm";
▲ Show 20 Lines • Show All 674 Lines • Show Last 20 Lines

lib/Target/AMDGPU/CMakeLists.txt

set(LLVM_TARGET_DEFINITIONS AMDGPU.td) set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info) tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info) tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel) tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv) tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic) tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer) tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering) tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank) tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
arsenmUnsubmitted
Not Done
ReplyInline Actions

Extra whitespace change

arsenm: Extra whitespace change
add_public_tablegen_target(AMDGPUCommonTableGen) add_public_tablegen_target(AMDGPUCommonTableGen)
add_llvm_target(AMDGPUCodeGen add_llvm_target(AMDGPUCodeGen
AMDGPUAliasAnalysis.cpp AMDGPUAliasAnalysis.cpp
AMDGPUAlwaysInlinePass.cpp AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp AMDGPUAnnotateKernelFeatures.cpp
AMDGPUAnnotateUniformValues.cpp AMDGPUAnnotateUniformValues.cpp
AMDGPUArgumentUsageInfo.cpp AMDGPUArgumentUsageInfo.cpp
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

lib/Target/AMDGPU/R600Instructions.td

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Linesdef FRAMEri : Operand<iPTR> {
let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
} }
def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
(ops PRED_SEL_OFF)>; (ops PRED_SEL_OFF)>;
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
▲ Show 20 Lines • Show All 1,661 Lines • Show Last 20 Lines