AMDGPU: Turn int pack pattern into build_vector

[arsenm]

Summary

build_vector is a more useful canonical form when
pattern matching packed operations, so turn shift
into high element into a build_vector.

Should show no change for now.

[rampitec]

Test is needed.

[arsenm]

In D37094#855712, @rampitec wrote:

Test is needed.

There's no visible change with this. Without it some of the tests added in D37222 and subsequent patches fail

[rampitec]

LGTM

[arsenm]

r312282

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SelectionDAG &DAG = DCI.DAG;
 
   switch (LHS->getOpcode()) {
   default:
     break;
   case ISD::ZERO_EXTEND:
   case ISD::SIGN_EXTEND:
   case ISD::ANY_EXTEND: {
+    SDValue X = LHS->getOperand(0);
+
+    if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
+        isTypeLegal(MVT::v2i16)) {
+      // Prefer build_vector as the canonical form if packed types are legal.
+      // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
+      SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
+       { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
+      return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
+    }
+
     // shl (ext x) => zext (shl x), if shift does not overflow int
     if (VT != MVT::i64)
       break;
     KnownBits Known;
-    SDValue X = LHS->getOperand(0);
     DAG.computeKnownBits(X, Known);
     unsigned LZ = Known.countMinLeadingZeros();
     if (LZ < RHSVal)
       break;
     EVT XVT = X.getValueType();
     SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
     return DAG.getZExtOrTrunc(Shl, SL, VT);
   }

lib/Target/AMDGPU/SIInstructions.td

 def : ExpPattern<AMDGPUexport, i32, EXP>;
 def : ExpPattern<AMDGPUexport_done, i32, EXP_DONE>;
 
 def : Pat <
   (v2i16 (build_vector i16:$src0, i16:$src1)),
   (v2i16 (S_PACK_LL_B32_B16 $src0, $src1))
 >;
 
+// COPY_TO_REGCLASS is workaround tablegen bug from multiple outputs
+// from S_LSHL_B32's multiple outputs from implicit scc def.
+def : Pat <
+  (v2i16 (build_vector (i16 0), i16:$src1)),
+  (v2i16 (COPY_TO_REGCLASS (S_LSHL_B32 i16:$src1, (i16 16)), SReg_32_XM0))
+>;
+
 // With multiple uses of the shift, this will duplicate the shift and
 // increase register pressure.
 def : Pat <
   (v2i16 (build_vector i16:$src0, (i16 (trunc (srl_oneuse i32:$src1, (i32 16)))))),
   (v2i16 (S_PACK_LH_B32_B16 i16:$src0, i32:$src1))
 >;
 
 def : Pat <