[ARM] Add missing patterns for insert_subvector.

[fhahn]

Summary

In some cases, shufflevector instruction can be transformed involving insert_subvector instructions. The ARM backend was missing some insert_subvector patterns, causing a failure during instruction selection. AArch64 has similar patterns.

[javed.absar]

LGTM. Maybe elaborate a bit more on the summary part

lib/Target/ARM/ARMInstrNEON.td

 
 def : Pat<(vector_insert (v2f32 DPR:$src),
                          (f32 (load addrmode6:$addr)), imm:$lane),
           (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
 def : Pat<(vector_insert (v4f32 QPR:$src),
                          (f32 (load addrmode6:$addr)), imm:$lane),
           (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
 
+// A 64-bit subvector insert to the first 128-bit vector position
+// is a subregister copy that needs no instruction.
+def : Pat<(insert_subvector undef, (v1i64 DPR:$src), (i32 0)),
+          (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
+def : Pat<(insert_subvector undef, (v2i32 DPR:$src), (i32 0)),
+          (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
+def : Pat<(insert_subvector undef, (v2f32 DPR:$src), (i32 0)),
+          (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
+def : Pat<(insert_subvector undef, (v4i16 DPR:$src), (i32 0)),
+          (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
+def : Pat<(insert_subvector undef, (v4f16 DPR:$src), (i32 0)),
+          (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
+def : Pat<(insert_subvector (v16i8 undef), (v8i8 DPR:$src), (i32 0)),
+          (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
+
+
 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
 
 // ...with address register writeback:
 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
   : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
           (ins addrmode6:$Rn, am6offset:$Rm,
            DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
           "\\{$Vd[$lane]\\}, $Rn$Rm",

test/CodeGen/ARM/arm-insert-subvector.ll

+; RUN: llc -start-before=isel -stop-after=isel -mtriple armv8-unknown-linux -o - < %s | FileCheck %s
+
+define <2 x float> @test_float(<6 x float>* %src) {
+  %v= load <6 x float>, <6 x float>* %src, align 1
+  %r = shufflevector <6 x float> %v, <6 x float> undef, <2 x i32> <i32 2, i32 5>
+  ret <2 x float> %r
+}
+; CHECK: name: test_float
+; CHECK: INSERT_SUBREG
+
+define <2 x i32> @test_i32(<6 x i32>* %src) {
+  %v= load <6 x i32>, <6 x i32>* %src, align 1
+  %r = shufflevector <6 x i32> %v, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
+  ret <2 x i32> %r
+}
+; CHECK: name: test_i32
+; CHECK: INSERT_SUBREG
+
+define <4 x i16> @test_i16(<12 x i16>* %src) {
+  %v= load <12 x i16>, <12 x i16>* %src, align 1
+  %r = shufflevector <12 x i16> %v, <12 x i16> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 7>
+  ret <4 x i16> %r
+}
+; CHECK: name: test_i16
+; CHECK: INSERT_SUBREG
+
+define <8 x i8> @test_i8(<24 x i8>* %src) {
+  %v= load <24 x i8>, <24 x i8>* %src, align 1
+  %r = shufflevector <24 x i8> %v, <24 x i8> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
+  ret <8 x i8> %r
+}
+; CHECK: name: test_i8
+; CHECK: INSERT_SUBREG