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Differential D36785

[ARM][AArch64] v8.3-A Javascript Conversion
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Authored by samparker on Aug 16 2017, 1:50 AM.

Details

Reviewers
dmgreen
Commits
rG6dc3fcb1c6cf: [ARM][AArch64] v8.3-A Javascript Conversion
rL311448: [ARM][AArch64] v8.3-A Javascript Conversion
Summary

Armv8.3-A adds instructions that convert a double-precision floating-point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance.

Diff Detail

Event Timeline

samparker created this revision.Aug 16 2017, 1:50 AM
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson. · View Herald TranscriptAug 16 2017, 1:50 AM
dmgreen accepted this revision.Aug 22 2017, 1:35 AM
dmgreen added a subscriber: dmgreen.

Looks like a simple addition. LGTM.

This revision is now accepted and ready to land.Aug 22 2017, 1:35 AM
Closed by commit rL311448: [ARM][AArch64] v8.3-A Javascript Conversion (authored by sam_parker). · Explain WhyAug 22 2017, 4:09 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AArch64/
7 lines
ARM/
9 lines
test/
MC/
AArch64/
10 lines
ARM/
16 lines
Disassembler/
AArch64/
3 lines
ARM/
10 lines
10 lines

Diff 111319

lib/Target/AArch64/AArch64InstrInfo.td

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def RETAB : AuthReturn<0b010, 1, "retab">; def RETAB : AuthReturn<0b010, 1, "retab">;
def ERETAA : AuthReturn<0b100, 0, "eretaa">; def ERETAA : AuthReturn<0b100, 0, "eretaa">;
def ERETAB : AuthReturn<0b100, 1, "eretab">; def ERETAB : AuthReturn<0b100, 1, "eretab">;
} }
defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>;
defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>;
// v8.3a floating point conversion for javascript
let Predicates = [HasV8_3a, HasFPARMv8] in
def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
"fjcvtzs", []> {
let Inst{31} = 0;
}
} // HasV8_3A } // HasV8_3A
def : InstAlias<"clrex", (CLREX 0xf)>; def : InstAlias<"clrex", (CLREX 0xf)>;
def : InstAlias<"isb", (ISB 0xf)>; def : InstAlias<"isb", (ISB 0xf)>;
def MRS : MRSI; def MRS : MRSI;
def MSR : MSRI; def MSR : MSRI;
def MSRpstateImm1 : MSRpstateImm0_1; def MSRpstateImm1 : MSRpstateImm0_1;
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lib/Target/ARM/ARMInstrVFP.td

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(outs SPR:$Sd), (ins SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm", IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 0; // Z bit let Inst{7} = 0; // Z bit
} }
} }
// v8.3-a Javascript Convert to Signed fixed-point
def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011,
(outs SPR:$Sd), (ins DPR:$Dm),
IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",
[]>,
Requires<[HasFPARMv8, HasV8_3a]> {
let Inst{7} = 1; // Z bit
}
// Convert between floating-point and fixed-point // Convert between floating-point and fixed-point
// Data type for fixed-point naming convention: // Data type for fixed-point naming convention:
// S16 (U=0, sx=0) -> SH // S16 (U=0, sx=0) -> SH
// U16 (U=1, sx=0) -> UH // U16 (U=1, sx=0) -> UH
// S32 (U=0, sx=1) -> SL // S32 (U=0, sx=1) -> SL
// U32 (U=1, sx=1) -> UL // U32 (U=1, sx=1) -> UL
let Constraints = "$a = $dst" in { let Constraints = "$a = $dst" in {
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test/MC/AArch64/armv8.3a-js.s

  • This file was added.
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-REQ < %t %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fp-armv8 < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NOFP < %t %s
fjcvtzs w0, d0
// CHECK: fjcvtzs w0, d0 // encoding: [0x00,0x00,0x7e,0x1e]
// CHECK-REQ: error: instruction requires: armv8.3a
// CHECK-NOFP: error: instruction requires: fp-armv8

test/MC/ARM/armv8.3a-js.s

  • This file was added.
// RUN: llvm-mc -triple arm-none-none-eabi -show-encoding -mattr=+v8.3a,+fp-armv8 < %s 2>&1 | FileCheck %s --check-prefix=ARM
// RUN: llvm-mc -triple thumb-none-none-eabi -show-encoding -mattr=+v8.3a,+fp-armv8 < %s 2>&1 | FileCheck %s --check-prefix=THUMB
// RUN: not llvm-mc -triple arm-none-none-eabi -show-encoding -mattr=+v8.2a,+fp-armv8 < %s 2>&1 | FileCheck --check-prefix=REQ-V83 %s
// RUN: not llvm-mc -triple arm-none-none-eabi -show-encoding -mattr=+v8.3a,-fp-armv8 < %s 2>&1 | FileCheck --check-prefix=REQ-FP %s
vjcvt.s32.f64 s1, d2
// ARM: vjcvt.s32.f64 s1, d2 @ encoding: [0xc2,0x0b,0xf9,0xee]
// THUMB: vjcvt.s32.f64 s1, d2 @ encoding: [0xf9,0xee,0xc2,0x0b]
// REQ-V83: error: instruction requires: armv8.3a
// REQ-FP: error: instruction requires: FPARMv8
vjcvt.s32.f64 s17, d18
// ARM: vjcvt.s32.f64 s17, d18 @ encoding: [0xe2,0x8b,0xf9,0xee]
// THUMB: vjcvt.s32.f64 s17, d18 @ encoding: [0xf9,0xee,0xe2,0x8b]
// REQ-V83: error: instruction requires: armv8.3a
// REQ-FP: error: instruction requires: FPARMv8

test/MC/Disassembler/AArch64/armv8.3a-js.txt

  • This file was added.
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
# CHECK: fjcvtzs w0, d0
[0x00,0x00,0x7e,0x1e]

test/MC/Disassembler/ARM/armv8.3a-js-arm.txt

  • This file was added.
# RUN: llvm-mc -triple arm-none-eabi -mattr=+v8.3a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple arm-none-eabi -mattr=+v8.2a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
# RUN: not llvm-mc -triple arm-none-eabi -mattr=+v8.3a,-fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
[0xc2,0x0b,0xf9,0xee]
# CHECK: vjcvt.s32.f64 s1, d2
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding
[0xe2,0x8b,0xf9,0xee]
# CHECK: vjcvt.s32.f64 s17, d18
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding

test/MC/Disassembler/ARM/armv8.3a-js-thumb.txt

  • This file was added.
# RUN: llvm-mc -triple thumb-none-eabi -mattr=+v8.3a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple thumb-none-eabi -mattr=+v8.2a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
# RUN: not llvm-mc -triple thumb-none-eabi -mattr=+v8.3a,-fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
[0xf9,0xee,0xc2,0x0b]
# CHECK: vjcvt.s32.f64 s1, d2
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding
[0xf9,0xee,0xe2,0x8b]
# CHECK: vjcvt.s32.f64 s17, d18
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding