[AMDGPU][MC] Enabled expressions as operands

[dp]

Summary

See bug 33579: https://bugs.llvm.org//show_bug.cgi?id=33579

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
       getLexer().is(AsmToken::EndOfStatement))
     return ResTy;
 
   ResTy = parseRegOrImm(Operands);
 
   if (ResTy == MatchOperand_Success)
     return ResTy;
 
-  if (getLexer().getKind() == AsmToken::Identifier) {
-    // If this identifier is a symbol, we want to create an expression for it.
-    // It is a little difficult to distinguish between a symbol name, and
-    // an instruction flag like 'gds'.  In order to do this, we parse
-    // all tokens as expressions and then treate the symbol name as the token
-    // string when we want to interpret the operand as a token.
-    const auto &Tok = Parser.getTok();
-    SMLoc S = Tok.getLoc();
-    const MCExpr *Expr = nullptr;
-    if (!Parser.parseExpression(Expr)) {
-      Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
-      return MatchOperand_Success;
-    }
+
 
-    Operands.push_back(AMDGPUOperand::CreateToken(this, Tok.getString(), Tok.getLoc()));
+  // Possibly this is an instruction flag like 'gds'.
+  if (Tok.getKind() == AsmToken::Identifier) {
+    Operands.push_back(AMDGPUOperand::CreateToken(this, Tok.getString(), S));
     Parser.Lex();
     return MatchOperand_Success;
   }
+
   return MatchOperand_NoMatch;
 }
 
 StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
   // Clear any forced encodings from the previous instruction.
   setForcedEncodingSize(0);
   setForcedDPP(false);
   setForcedSDWA(false);

llvm/trunk/test/MC/AMDGPU/expressions.s

 .set foo, 4
 s_mov_b32 s0, foo+2
 // VI: s_mov_b32 s0, 6 ; encoding: [0x86,0x00,0x80,0xbe]
 
 // Use a computed expression that results in a non-inline immediate.
 .set foo, 512
 s_mov_b32 s0, foo+2
 // VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]
+
+BB1:
+v_nop_e64
+BB2:
+s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1
+// VI: s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1 ; encoding: [0x6a,0xff,0xea,0x80,A,A,A,A]
+// VI-NEXT: ;   fixup A - offset: 4, value: (BB2+4)-BB1, kind: FK_Data_4

llvm/trunk/test/MC/AMDGPU/vop3p-err.s

 //
 // Regular modifiers on packed instructions
 //
 
 // FIXME: should be invalid operand for instruction
 // GFX9: :18: error: not a valid operand.
 v_pk_add_f16 v1, |v2|, v3
 
-// GFX9: :21: error: not a valid operand.
+// GFX9: :18: error: invalid operand for instruction
 v_pk_add_f16 v1, abs(v2), v3
 
 // GFX9: :22: error: not a valid operand.
 v_pk_add_f16 v1, v2, |v3|
 
-// GFX9: :25: error: not a valid operand.
+// GFX9: :22: error: invalid operand for instruction
 v_pk_add_f16 v1, v2, abs(v3)
 
 // GFX9: :19: error: invalid operand for instruction
 v_pk_add_f16 v1, -v2, v3
 
 // GFX9: :23: error: invalid operand for instruction
 v_pk_add_f16 v1, v2, -v3
 
-// GFX9: :21: error: not a valid operand.
+// GFX9: :18: error: invalid operand for instruction
 v_pk_add_u16 v1, abs(v2), v3
 
 // GFX9: :19: error: invalid operand for instruction
 v_pk_add_u16 v1, -v2, v3
 
 //
 // Constant bus restrictions
 //
 
 // GFX9: invalid operand (violates constant bus restrictions)
 v_pk_add_f16 v255, s1, s2