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AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
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Authored by tstellar on Jul 26 2017, 8:59 PM.

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Summary

This is only used by R600.

Build Status

Buildable 8634
Build 8634: arc lint + arc unit

LGTM. I've been meaning to remove the reservation for it from getReservedRegs too, can you get that one also?

This revision is now accepted and ready to land.Jul 26 2017, 9:05 PM

This revision was automatically updated to reflect the committed changes.

Path

Size

lib/

Target/

AMDGPU/

2 lines

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	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	let Namespace = "AMDGPU" in {			let Namespace = "AMDGPU" in {

	foreach Index = 0-15 in {			foreach Index = 0-15 in {
	def sub#Index : SubRegIndex<32, !shl(Index, 5)>;			def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
	}			}

	def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;

	}			}

	include "R600RegisterInfo.td"			include "R600RegisterInfo.td"
	include "SIRegisterInfo.td"			include "SIRegisterInfo.td"

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	def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;			def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;
	def PV_W : R600RegWithChan<"PV.W", 254, "W">;			def PV_W : R600RegWithChan<"PV.W", 254, "W">;
	def PS: R600Reg<"PS", 255>;			def PS: R600Reg<"PS", 255>;
	def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;			def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
	def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;			def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
	def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;			def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
	def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;			def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
	def AR_X : R600Reg<"AR.x", 0>;			def AR_X : R600Reg<"AR.x", 0>;
				def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;

	def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,			def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
	(add (sequence "ArrayBase%u", 448, 480))>;			(add (sequence "ArrayBase%u", 448, 480))>;
	// special registers for ALU src operands			// special registers for ALU src operands
	// const buffer reference, SRCx_SEL contains index			// const buffer reference, SRCx_SEL contains index
	def ALU_CONST : R600Reg<"CBuf", 0>;			def ALU_CONST : R600Reg<"CBuf", 0>;
	// interpolation param reference, SRCx_SEL contains index			// interpolation param reference, SRCx_SEL contains index
	def ALU_PARAM : R600Reg<"Param", 0>;			def ALU_PARAM : R600Reg<"Param", 0>;
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