AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files

[tstellar]

Summary

This is only used by R600.

[arsenm]

LGTM. I've been meaning to remove the reservation for it from getReservedRegs too, can you get that one also?

llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td

 //===----------------------------------------------------------------------===//
 
 let Namespace = "AMDGPU" in {
 
 foreach Index = 0-15 in {
   def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
-def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
-
 }
 
 include "R600RegisterInfo.td"
 include "SIRegisterInfo.td"

llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td

 def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;
 def PV_W : R600RegWithChan<"PV.W", 254, "W">;
 def PS: R600Reg<"PS", 255>;
 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 def AR_X : R600Reg<"AR.x", 0>;
+def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;
 
 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
                           (add (sequence "ArrayBase%u", 448, 480))>;
 // special registers for ALU src operands
 // const buffer reference, SRCx_SEL contains index
 def ALU_CONST : R600Reg<"CBuf", 0>;
 // interpolation param reference, SRCx_SEL contains index
 def ALU_PARAM : R600Reg<"Param", 0>;

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

 
 unsigned SIRegisterInfo::reservedStackPtrOffsetReg(
   const MachineFunction &MF) const {
   return AMDGPU::SGPR32;
 }
 
 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
-  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
 
   // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
   // this seems likely to result in bugs, so I'm marking them as reserved.
   reserveRegisterTuples(Reserved, AMDGPU::EXEC);
   reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
 
   // M0 has to be reserved so that llvm accepts it as a live-in into a block.
   reserveRegisterTuples(Reserved, AMDGPU::M0);