[ARM] Use Swift error registers on non-Darwin targets

[modocache]

Summary

Remove a check for ARMSubtarget::isTargetDarwin when determining
whether to use Swift error registers, so that Swift errors work
properly on non-Darwin ARM32 targets (specifically Android).

Before this patch, generated code would save and restores ARM register r8 at
the entry and returns of a function that throws. As r8 is used as a virtual
return value for the object being thrown, this gets overwritten by the restore,
and calling code is unable to catch the error. In turn this caused Swift code
that used do/try/catch to work improperly on Android ARM32 targets.

Addresses Swift bug report https://bugs.swift.org/browse/SR-5438.

Patch by John Holdsworth.

[aschwaighofer]

The change looks good but can you add a test case to test/CodeGen/ARM/swifterror.ll that r8 is not spilled say for a target triple of 'armv7-linux-androideabi'. For example, the function params_and_return_in_reg should not spill r8 as part of CSR spilling.

You would add the following run line to that file:

; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-linux-androideabi | FileCheck --check-prefix=CHECK-ANDROID %s

And then copy the check located next to the params_and_return_in_reg function but for 'CHECK-ANDROID'.

Thank you for the contribution!

[modocache]

Yup, can do! Thanks for the suggestion.

[modocache]

Added some tests to test/CodeGen/ARM/swifterror.ll, also courtesy of John Holdsworth.

[aschwaighofer]

LGTM.

lib/Target/ARM/ARMBaseRegisterInfo.cpp

if (STI.isMClass()) {
       return CSR_FIQ_SaveList;
     } else {
       // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
       // exception handling.
       return CSR_GenericInt_SaveList;
     }
   }
 
-  if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
+  if (STI.getTargetLowering()->supportSwiftError() &&
       F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
     return CSR_iOS_SwiftError_SaveList;
 
   if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
     return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
                ? CSR_iOS_CXX_TLS_PE_SaveList
                : CSR_iOS_CXX_TLS_SaveList;
   return RegList;

 const uint32_t *
 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                           CallingConv::ID CC) const {
   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
   if (CC == CallingConv::GHC)
     // This is academic because all GHC calls are (supposed to be) tail calls
     return CSR_NoRegs_RegMask;
 
-  if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
+  if (STI.getTargetLowering()->supportSwiftError() &&
       MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
     return CSR_iOS_SwiftError_RegMask;
 
   if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
     return CSR_iOS_CXX_TLS_RegMask;
   return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
 }
 

test/CodeGen/ARM/swifterror.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-APPLE --check-prefix=CHECK-ARMV7 %s
 ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-O0 %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-linux-androideabi | FileCheck --check-prefix=CHECK-ANDROID %s
 
 declare i8* @malloc(i64)
 declare void @free(i8*)
 %swift_error = type { i64, i8 }
 %struct.S = type { i32, i32, i32, i32, i32, i32 }
 
 ; This tests the basic usage of a swifterror parameter. "foo" is the function
 ; that takes a swifterror parameter and "caller" is the caller of "foo".

 ; Load swifterror %err;
 ; CHECK-ARMV7-DAG:  ldr     r8, [s[[STK1]]]
 ; Restore return values for returning.
 ; CHECK-ARMV7-DAG:  mov     r0, r4
 ; CHECK-ARMV7-DAG:  mov     r1, r5
 ; CHECK-ARMV7-DAG:  mov     r2, r6
 ; CHECK-ARMV7-DAG:  mov     r3, r11
 ; CHECK-ARMV7:  pop     {r4, r5, r6, r7, r10, r11, pc}
+
+; CHECK-ANDROID-LABEL: params_and_return_in_reg
+; CHECK-ANDROID:  push  {r4, r5, r6, r7, r10, r11, lr}
+; CHECK-ANDROID:  sub sp, sp, #12
+; CHECK-ANDROID:  mov r5, r8
+; CHECK-ANDROID:  str r10, [sp, #4]           @ 4-byte Spill
+; CHECK-ANDROID:  mov r6, r3
+; CHECK-ANDROID:  mov r7, r2
+; CHECK-ANDROID:  mov r4, r1
+; CHECK-ANDROID:  mov r11, r0
+; CHECK-ANDROID:  mov r0, #1
+; CHECK-ANDROID:  mov r1, #2
+; CHECK-ANDROID:  mov r2, #3
+; CHECK-ANDROID:  mov r3, #4
+; CHECK-ANDROID:  mov r10, #0
+; CHECK-ANDROID:  mov r8, #0
+; CHECK-ANDROID:  bl  params_in_reg2
+; CHECK-ANDROID:  ldr r10, [sp, #4]           @ 4-byte Reload
+; CHECK-ANDROID:  mov r0, r11
+; CHECK-ANDROID:  str r8, [sp]                @ 4-byte Spill
+; CHECK-ANDROID:  mov r1, r4
+; CHECK-ANDROID:  mov r2, r7
+; CHECK-ANDROID:  mov r3, r6
+; CHECK-ANDROID:  mov r8, r5
+; CHECK-ANDROID:  bl  params_and_return_in_reg2
+; CHECK-ANDROID:  mov r11, r8
+; CHECK-ANDROID:  ldr r8, [sp]                @ 4-byte Reload
+; CHECK-ANDROID:  mov r4, r0
+; CHECK-ANDROID:  mov r6, r1
+; CHECK-ANDROID:  mov r7, r2
+; CHECK-ANDROID:  mov r5, r3
+; CHECK-ANDROID:  mov r0, #1
+; CHECK-ANDROID:  mov r1, #2
+; CHECK-ANDROID:  mov r2, #3
+; CHECK-ANDROID:  mov r3, #4
+; CHECK-ANDROID:  mov r10, #0
+; CHECK-ANDROID:  bl  params_in_reg2
+; CHECK-ANDROID:  mov r0, r4
+; CHECK-ANDROID:  mov r1, r6
+; CHECK-ANDROID:  mov r2, r7
+; CHECK-ANDROID:  mov r3, r5
+; CHECK-ANDROID:  mov r8, r11
+; CHECK-ANDROID:  add sp, sp, #12
+; CHECK-ANDROID:  pop {r4, r5, r6, r7, r10, r11, pc}
+
 define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
   %error_ptr_ref = alloca swifterror %swift_error*, align 8
   store %swift_error* null, %swift_error** %error_ptr_ref
   call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
   %val = call swiftcc  { i32, i32, i32, i32 } @params_and_return_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
   call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
   ret { i32, i32, i32, i32 }%val
 }
 
 declare swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
 
 
 declare void @acallee(i8*)
 
 ; Make sure we don't tail call if the caller returns a swifterror value. We
 ; would have to move into the swifterror register before the tail call.
 ; CHECK-APPLE: tailcall_from_swifterror:
 ; CHECK-APPLE-NOT: b _acallee
 ; CHECK-APPLE: bl _acallee
+; CHECK-ANDROID: tailcall_from_swifterror:
+; CHECK-ANDROID-NOT: b acallee
+; CHECK-ANDROID: bl acallee
 
 define swiftcc void @tailcall_from_swifterror(%swift_error** swifterror %error_ptr_ref) {
 entry:
   tail call void @acallee(i8* null)
   ret void
 }
 
 
 declare swiftcc void @foo2(%swift_error** swifterror)
 
 ; Make sure we properly assign registers during fast-isel.
 ; CHECK-O0-LABEL: testAssign
 ; CHECK-O0: mov     r8, #0
 ; CHECK-O0: bl      _foo2
 ; CHECK-O0: str     r8, [s[[STK:p.*]]]
 ; CHECK-O0: ldr     r0, [s[[STK]]]
 ; CHECK-O0: pop
 
 ; CHECK-APPLE-LABEL: testAssign
 ; CHECK-APPLE:  mov     r8, #0
 ; CHECK-APPLE:  bl      _foo2
 ; CHECK-APPLE:  mov     r0, r8
 
+; CHECK-ANDROID-LABEL: testAssign
+; CHECK-ANDROID:  mov     r8, #0
+; CHECK-ANDROID:  bl      foo2
+; CHECK-ANDROID:  mov     r0, r8
+
 define swiftcc %swift_error* @testAssign(i8* %error_ref) {
 entry:
   %error_ptr = alloca swifterror %swift_error*
   store %swift_error* null, %swift_error** %error_ptr
   call swiftcc void @foo2(%swift_error** swifterror %error_ptr)
   br label %a
 
 a:
   %error = load %swift_error*, %swift_error** %error_ptr
   ret %swift_error* %error
 }