[LV][X86] Support of AVX2 Gathers code generation and update the LV with this

[magabari]

Summary

This patch depends on: https://reviews.llvm.org/D35348

Support of pattern selection of masked gathers on AVX2 (in X86\AVX2 code gen)
Update LoopVectorize to generate gathers for AVX2 processors.

[RKSimon]

../llvm/lib/Analysis/TargetTransformInfo.cpp

158

Why on earth was this calling TTIImpl->isLegalMaskedGather? Make this change separately since it affects all targets not just X86?

../llvm/lib/Target/X86/X86ISelLowering.cpp

893

This should be later on with the other AVX2 settings.

23770

MSCATTER isn't supported on AVX2 - update the assertion comment, I don't think it needs to refer to MSCATTER.

23827

Drop the innermost brackets around (Subtarget.hasAVX2())

23843

Src0?

23860

Drop the innermost brackets around (Subtarget.hasAVX2())

23875

Src0?

../llvm/lib/Target/X86/X86TargetTransformInfo.cpp

2217

AVX-512 & SKL client with AVX2 allows gather

2219

(ST->hasAVX2()) --> ST->hasAVX2()

../llvm/test/CodeGen/X86/avx2_masked_gather.ll

2

You should be able to use utils/update_llc_test_checks.py to autogenerate the codegen.

Usual convention is to use X86 and X64 for the prefixes.

Why are you needing to pipe stderr?

4

Remove the triple/datalayout lines - you should be driving this from the -mtriples in the command line

[magabari]

fixed simon notes

[RKSimon]

lib/Target/X86/X86ISelLowering.cpp

23861 ↗

(On Diff #107858)

clang-format?

lib/Target/X86/X86TargetTransformInfo.cpp

2106 ↗

(On Diff #107858)

clang-format?

2219 ↗

(On Diff #107858)

clang-format?

test/CodeGen/X86/avx2_masked_gather.ll

3 ↗

(On Diff #107858)

Please can you submit this test file with the current trunk codegen and update this patch to show the diff?

29 ↗

(On Diff #107858)

It might be useful to either update this test to return <4x i32> (concat the v2i32 gather result with v2i32 undef) or add a separate test case that does this. Same for the <2 x float> tests. What do you think?

[RKSimon]

test/CodeGen/X86/avx2_masked_gather.ll

3 ↗

(On Diff #107858)

And to match existing test files please can you rename it avx2-masked-gather.ll?

[RKSimon]

@magabari What is happening with this?

[magabari]

In D35772#864707, @RKSimon wrote:

@magabari What is happening with this?

will update it soon ..

[magabari]

ping

[magabari]

ping ping

[delena]

lib/Target/X86/X86ISelLowering.cpp

23915 ↗

(On Diff #115618)

if the subtarget has VLX it always has AVX2. Gather is not supported under AVX2..

23933 ↗

(On Diff #115618)

clang-format

23966 ↗

(On Diff #115618)

clang-format

[magabari]

fixed Elena comments

[delena]

lib/Target/X86/X86ISelLowering.cpp

1010 ↗

(On Diff #120943)

if (Subtarget.hasAVX2())
  setOperationAction(ISD::MGATHER, MVT::v2i64, Custom);

23915 ↗

(On Diff #120943)

512 includes AVX2

23986 ↗

(On Diff #120943)

if (Subtarget.hasVLX())
  Mask = ExtendToType(Mask, MVT::v4i1, DAG, false);
else
  Mask =  DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Mask),
                                                    DAG.getUNDEF(MVT::v4i32), {0, 2, -1, -1});

24004 ↗

(On Diff #120943)

VLX contains AVX2

24018 ↗

(On Diff #120943)

I fixed the code above.

[delena]

lib/Target/X86/X86ISelLowering.cpp

24197 ↗

(On Diff #121120)

I think that this transformation of mask is wrong for V2F32. unlike integer, it was widened to v4f32 and the mask should be correct.

lib/Target/X86/X86TargetTransformInfo.cpp

2462 ↗

(On Diff #121120)

this "if" is not clear. Please add appropriate comments and describe what you are going to check.

2515 ↗

(On Diff #121120)

512 includes avx2

[magabari]

updating masked-intrinsic-cost.ll with the new costs of AVX2 and adding SKL check

[magabari]

gathers will be allowed for Skylake currently

../llvm/lib/Analysis/TargetTransformInfo.cpp

bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
   return TTIImpl->isLegalMaskedLoad(DataType);
 }
 
 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
   return TTIImpl->isLegalMaskedGather(DataType);
 }
 
 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
-  return TTIImpl->isLegalMaskedGather(DataType);
+  return TTIImpl->isLegalMaskedScatter(DataType);
 }
 
 bool TargetTransformInfo::prefersVectorizedAddressing() const {
   return TTIImpl->prefersVectorizedAddressing();
 }
 
 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
                                               int64_t BaseOffset,

../llvm/lib/Target/X86/X86ISelLowering.cpp

if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
     // in AVX2 will be recognized.
     for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
       setOperationAction(ISD::SRL,              VT, Custom);
       setOperationAction(ISD::SHL,              VT, Custom);
       setOperationAction(ISD::SRA,              VT, Custom);
     }
   }
 
+  if (Subtarget.hasAVX2()) {
+    for (auto VT : { MVT::v2i64 }) {
+      setOperationAction(ISD::MGATHER,  VT, Custom);
+    }
+  }
+
   if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
     setOperationAction(ISD::ABS,                MVT::v16i8, Legal);
     setOperationAction(ISD::ABS,                MVT::v8i16, Legal);
     setOperationAction(ISD::ABS,                MVT::v4i32, Legal);
     setOperationAction(ISD::BITREVERSE,         MVT::v16i8, Custom);
     setOperationAction(ISD::CTLZ,               MVT::v16i8, Custom);
     setOperationAction(ISD::CTLZ,               MVT::v8i16, Custom);
     setOperationAction(ISD::CTLZ,               MVT::v4i32, Custom);
Mask = DAG.getNode(ISD::TRUNCATE, dl,
                        MVT::getVectorVT(MVT::i1, NumEltsInWideVec), Mask);
   return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
                             Mask, N->getMemoryVT(), N->getMemOperand(),
                             N->isTruncatingStore(), N->isCompressingStore());
 }
 
 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget,
                             SelectionDAG &DAG) {
-  assert(Subtarget.hasAVX512() &&
-         "MGATHER/MSCATTER are supported on AVX-512 arch only");
-
+  assert((Subtarget.hasAVX512() || Subtarget.hasAVX2()) &&
+         "MGATHER/MSCATTER are supported on AVX-512/AVX-2 arch only");
   MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
   SDValue Index = N->getIndex();
   SDValue Mask = N->getMask();
   SDValue Src0 = N->getValue();
   MVT IndexVT = Index.getSimpleValueType();
   MVT MaskVT = Mask.getSimpleValueType();
 
   unsigned NumElts = VT.getVectorNumElements();
   assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
 
-  if (!Subtarget.hasVLX() && !VT.is512BitVector() &&
+  if (Subtarget.hasAVX512() && !Subtarget.hasVLX() && !VT.is512BitVector() &&
       !Index.getSimpleValueType().is512BitVector()) {
     // AVX512F supports only 512-bit vectors. Or data or index should
     // be 512 bit wide. If now the both index and data are 256-bit, but
     // the vector contains 8 elements, we just sign-extend the index
     if (NumElts == 8) {
       Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
       SDValue Ops[] = { N->getOperand(0), N->getOperand(1),  N->getOperand(2),
                         N->getOperand(3), Index };
SDValue NewGather = DAG.getMaskedGather(DAG.getVTList(NewVT, MVT::Other),
                                             N->getMemoryVT(), dl, Ops,
                                             N->getMemOperand());
     SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
                                  NewGather.getValue(0),
                                  DAG.getIntPtrConstant(0, dl));
     SDValue RetOps[] = {Exract, NewGather.getValue(1)};
     return DAG.getMergeValues(RetOps, dl);
   }
-  if (N->getMemoryVT() == MVT::v2i32 && Subtarget.hasVLX()) {
+  if (N->getMemoryVT() == MVT::v2i32 && (Subtarget.hasVLX() || 
+        (Subtarget.hasAVX2()))) {
     // There is a special case when the return type is v2i32 is illegal and
     // the type legaizer extended it to v2i64. Without this conversion we end up
     // with VPGATHERQQ (reading q-words from the memory) instead of VPGATHERQD.
     // In order to avoid this situation, we'll build an X86 specific Gather node
     // with index v2i64 and value type v4i32.
     assert(VT == MVT::v2i64 && Src0.getValueType() == MVT::v2i64 &&
            "Unexpected type in masked gather");
     Src0 = DAG.getVectorShuffle(MVT::v4i32, dl,
                                 DAG.getBitcast(MVT::v4i32, Src0),
                                 DAG.getUNDEF(MVT::v4i32), { 0, 2, -1, -1 });
     // The mask should match the destination type. Extending mask with zeroes
     // is not necessary since instruction itself reads only two values from
     // memory.
+    if (Subtarget.hasAVX2()) {
+      Mask = DAG.getVectorShuffle(MVT::v4i32, dl,
+                                  DAG.getBitcast(MVT::v4i32, Src0),
+                                  DAG.getUNDEF(MVT::v4i32), { 0, 2, -1, -1 });
+    }
+    else {
       Mask = ExtendToType(Mask, MVT::v4i1, DAG, false);
+    }  
     SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
     SDValue NewGather = DAG.getTargetMemSDNode<X86MaskedGatherSDNode>(
       DAG.getVTList(MVT::v4i32, MVT::Other), Ops, dl, N->getMemoryVT(),
       N->getMemOperand());
 
     SDValue Sext = getExtendInVec(X86ISD::VSEXT, dl, MVT::v2i64,
                                   NewGather.getValue(0), DAG);
     SDValue RetOps[] = { Sext, NewGather.getValue(1) };
     return DAG.getMergeValues(RetOps, dl);
   }
-  if (N->getMemoryVT() == MVT::v2f32 && Subtarget.hasVLX()) {
+  if (N->getMemoryVT() == MVT::v2f32 && (Subtarget.hasVLX() || 
+        (Subtarget.hasAVX2()))) {
     // This transformation is for optimization only.
     // The type legalizer extended mask and index to 4 elements vector
     // in order to match requirements of the common gather node - same
     // vector width of index and value. X86 Gather node allows mismatch
     // of vector width in order to select more optimal instruction at the
     // end.
     assert(VT == MVT::v4f32 && Src0.getValueType() == MVT::v4f32 &&
            "Unexpected type in masked gather");
     if (Mask.getOpcode() == ISD::CONCAT_VECTORS &&
         ISD::isBuildVectorAllZeros(Mask.getOperand(1).getNode()) &&
         Index.getOpcode() == ISD::CONCAT_VECTORS &&
         Index.getOperand(1).isUndef()) {
-      Mask = ExtendToType(Mask.getOperand(0), MVT::v4i1, DAG, false);
+      if (Subtarget.hasAVX2()) {
+        Mask = DAG.getVectorShuffle(MVT::v4i32, dl,
+                                    DAG.getBitcast(MVT::v4i32, Src0),
+                                    DAG.getUNDEF(MVT::v4i32), { 0, 2, -1, -1 });
+      }
+      else {
+        Mask = ExtendToType(Mask, MVT::v4i1, DAG, false);
+      }
       Index = Index.getOperand(0);
     } else
       return Op;
     SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
     SDValue NewGather = DAG.getTargetMemSDNode<X86MaskedGatherSDNode>(
       DAG.getVTList(MVT::v4f32, MVT::Other), Ops, dl, N->getMemoryVT(),
       N->getMemOperand());
 

../llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
 }]>;
 
 def assertzext_i1 :
   PatFrag<(ops node:$src), (assertzext node:$src), [{
     return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i1;
 }]>;
+
+// AVX2 special nodes
+// masked gather of AVX2 where mask elements are i32
+def avx2_x86_masked_gather_32 : SDNode<"X86ISD::MGATHER",
+      SDTypeProfile<2, 3, [
+        SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
+        SDTCisPtrTy<4>, SDTCVecEltisVT<1, i32>, SDTCisSameNumEltsAs<0, 1>]>,
+      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+
+def avx2_masked_gather_32 : SDNode<"ISD::MGATHER",
+      SDTypeProfile<2, 3, [
+        SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
+        SDTCisPtrTy<4>, SDTCVecEltisVT<1, i32>, SDTCisSameNumEltsAs<0, 1>]>,
+      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+
+// masked gather of AVX2 where mask elements are i64
+def avx2_masked_gather_64 : SDNode<"ISD::MGATHER",
+      SDTypeProfile<2, 3, [
+        SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
+        SDTCisPtrTy<4>, SDTCVecEltisVT<1, i64>, SDTCisSameNumEltsAs<0, 1>]>,
+      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+
+// dword gathers
+def avx2_mvpgatherdd_ps_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
+            Mgt->getBasePtr().getValueType() == MVT::v4i32);
+  return false;
+}]>;
+
+def avx2_mvpgatherqd_ps_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_x86_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  if (X86MaskedGatherSDNode *Mgt = dyn_cast<X86MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
+            Mgt->getBasePtr().getValueType() == MVT::v2i64);
+  return false;
+}]>;
+
+def avx2_mvpgatherdd_ps_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
+            Mgt->getBasePtr().getValueType() == MVT::v8i32);
+  return false;
+}]>;
+
+def avx2_mvpgatherqd_ps_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
+            Mgt->getBasePtr().getValueType() == MVT::v4i64);
+  return false;
+}]>;
+
+// qwords
+def avx2_mvpgatherdq_pd_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v2i32 ||
+            Mgt->getBasePtr().getValueType() == MVT::v2i32);
+  return false;
+}]>;
+
+def avx2_mvpgatherqq_pd_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
+            Mgt->getBasePtr().getValueType() == MVT::v2i64) &&
+            Mgt->getMemoryVT().is128BitVector();
+  return false;
+}]>;
+
+def avx2_mvpgatherdq_pd_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
+            Mgt->getBasePtr().getValueType() == MVT::v4i32);
+  return false;
+}]>;
+
+def avx2_mvpgatherqq_pd_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
+  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
+    return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
+            Mgt->getBasePtr().getValueType() == MVT::v4i64);
+  return false;
+}]>;

../llvm/lib/Target/X86/X86InstrSSE.td

def : Pat<(v8i32 (X86vsrav VR256:$src1,
                     (bitconvert (loadv4i64 addr:$src2)))),
             (VPSRAVDYrm VR256:$src1, addr:$src2)>;
 }
 
 
 
 //===----------------------------------------------------------------------===//
 // VGATHER - GATHER Operations
-multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
+multiclass avx2_gather<bits<8> opc, string OpcodeStr, ValueType VTx,
+                       ValueType VTy, PatFrag GatherNode128, 
+                       PatFrag GatherNode256, RegisterClass RC256,
                        X86MemOperand memop128, X86MemOperand memop256> {
   def rm  : AVX28I<opc, MRMSrcMem4VOp3, (outs VR128:$dst, VR128:$mask_wb),
             (ins VR128:$src1, memop128:$src2, VR128:$mask),
             !strconcat(OpcodeStr,
               "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
-            []>, VEX;
+            [(set (VTx VR128:$dst), VR128:$mask_wb,
+                  (GatherNode128  (VTx VR128:$src1), VR128:$mask,
+                                vectoraddr:$src2))]>, VEX;
   def Yrm : AVX28I<opc, MRMSrcMem4VOp3, (outs RC256:$dst, RC256:$mask_wb),
             (ins RC256:$src1, memop256:$src2, RC256:$mask),
             !strconcat(OpcodeStr,
               "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
-            []>, VEX, VEX_L;
+            [(set (VTy RC256:$dst), RC256:$mask_wb,
+                  (GatherNode256  (VTy RC256:$src1), RC256:$mask,
+                                vectoraddr:$src2))]>, VEX, VEX_L;
 }
 
+let Predicates = [UseAVX2] in {
   let mayLoad = 1, hasSideEffects = 0, Constraints
     = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
     in {
-  defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx128mem, vx256mem>, VEX_W;
-  defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx128mem, vy256mem>, VEX_W;
-  defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx128mem, vy256mem>;
-  defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx64mem, vy128mem>;
+    defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", v2i64, v4i64, avx2_mvpgatherdq_pd_xmm,
+                        avx2_mvpgatherdq_pd_ymm, VR256, vx128mem, vx256mem>, VEX_W;
+    defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", v2i64, v4i64, avx2_mvpgatherqq_pd_xmm,
+                        avx2_mvpgatherqq_pd_ymm, VR256, vx128mem, vy256mem>, VEX_W;
+    defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", v4i32, v8i32, avx2_mvpgatherdd_ps_xmm,
+                        avx2_mvpgatherdd_ps_ymm, VR256, vx128mem, vy256mem>;
+    defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", v4i32, v4i32, avx2_mvpgatherqd_ps_xmm,
+                        avx2_mvpgatherqd_ps_ymm, VR128, vx64mem, vy128mem>;
 
     let ExeDomain = SSEPackedDouble in {
-    defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx128mem, vx256mem>, VEX_W;
-    defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx128mem, vy256mem>, VEX_W;
+      defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", v2f64, v4f64, avx2_mvpgatherdq_pd_xmm,
+                          avx2_mvpgatherdq_pd_ymm, VR256, vx128mem, vx256mem>, VEX_W;
+      defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", v2f64, v4f64, avx2_mvpgatherqq_pd_xmm,
+                          avx2_mvpgatherqq_pd_ymm, VR256, vx128mem, vy256mem>, VEX_W;
     }
 
     let ExeDomain = SSEPackedSingle in {
-    defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx128mem, vy256mem>;
-    defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx64mem, vy128mem>;
+      defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", v4f32, v8f32, avx2_mvpgatherdd_ps_xmm,
+                          avx2_mvpgatherdd_ps_ymm, VR256, vx128mem, vy256mem>;
+      defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", v4f32, v4f32, avx2_mvpgatherqd_ps_xmm,
+                          avx2_mvpgatherqd_ps_ymm, VR128, vx64mem, vy128mem>;    
+    }
   }
 }
 
 //===----------------------------------------------------------------------===//
 // Extra selection patterns for FR128, f128, f128mem
 
 // movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
 def : Pat<(store (f128 FR128:$src), addr:$dst),

../llvm/lib/Target/X86/X86TargetTransformInfo.cpp

for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
         return IndexSize; // 64
     }
     return (unsigned)32;
   };
 
 
   // Trying to reduce IndexSize to 32 bits for vector 16.
   // By default the IndexSize is equal to pointer size.
-  unsigned IndexSize = (VF >= 16) ? getIndexSizeInBits(Ptr, DL) :
+  unsigned IndexSize = (ST->hasAVX512() && VF >= 16) ? getIndexSizeInBits(Ptr, DL) :
     DL.getPointerSizeInBits();
 
   Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(),
                                                     IndexSize), VF);
   std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy);
   std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy);
   int SplitFactor = std::max(IdxsLT.first, SrcLT.first);
   if (SplitFactor > 1) {
     // Handle splitting of vector of pointers
     Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
     return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
                                          AddressSpace);
   }
 
   // The gather / scatter cost is given by Intel architects. It is a rough
   // number since we are looking at one instruction in a time.
-  const int GSOverhead = 2;
+  const int GSOverhead = (Opcode == Instruction::Load) ? ST->getGatherOverhead() :
+                           ST->getScatterOverhead();
   return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
                                            Alignment, AddressSpace);
 }
 
 /// Return the cost of full scalarization of gather / scatter operation.
 ///
 /// Opcode - Load or Store instruction.
 /// SrcVTy - The type of the data vector that should be gathered or scattered.
if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) ||
       (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy)))
     Scalarize = true;
   // Gather / Scatter for vector 2 is not profitable on KNL / SKX
   // Vector-4 of gather/scatter instruction does not exist on KNL.
   // We can extend it to 8 elements, but zeroing upper bits of
   // the mask vector will add more instructions. Right now we give the scalar
   // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
   // is better in the VariableMask case.
-  if (VF == 2 || (VF == 4 && !ST->hasVLX()))
+  if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX())))
     Scalarize = true;
 
   if (Scalarize)
     return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
                            AddressSpace);
 
   return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
 }
bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
   // The Scalarizer asks again about legality. It sends a vector type.
   // In this case we can reject non-power-of-2 vectors.
   if (isa<VectorType>(DataTy) && !isPowerOf2_32(DataTy->getVectorNumElements()))
     return false;
   Type *ScalarTy = DataTy->getScalarType();
   int DataWidth = isa<PointerType>(ScalarTy) ?
     DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
 
-  // AVX-512 allows gather and scatter
-  return (DataWidth == 32 || DataWidth == 64) && ST->hasAVX512();
+  // AVX-512 & SKL client with AVX2 allows gather and scatter
+  return (DataWidth == 32 || DataWidth == 64) && (ST->hasAVX512() ||
+    (ST->hasAVX2()));
 }
 
 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
+  // AVX2 doesn't support scatter
+  if (!ST->hasAVX512())
+    return false;
   return isLegalMaskedGather(DataType);
 }
 
 bool X86TTIImpl::areInlineCompatible(const Function *Caller,
                                      const Function *Callee) const {
   const TargetMachine &TM = getTLI()->getTargetMachine();
 
   // Work this as a subsetting of subtarget features.

../llvm/test/CodeGen/X86/avx2_masked_gather.ll

+; CHECK: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=skylake 2>&1 | FileCheck --check-prefix=CHECK32 %s
+; CHECK: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake 2>&1 | FileCheck --check-prefix=CHECK64 %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %ptrs, i32 %align, <2 x i1> %masks, <2 x i32> %passthro)
+
+define <2 x i32> @masked_gather_v2i32(<2 x i32*>* %ptr, <2 x i1> %masks, <2 x i32> %passthro) {
+entry:
+; CHECK64-LABEL: masked_gather_v2i32
+; CHECK64: vpshufd $232, %xmm1, %xmm1      
+; CHECK64: vpshufd $232, %xmm1, %xmm2      
+; CHECK64: vpgatherqd  %xmm2, (,%xmm0), %xmm1
+  %ld  = load <2 x i32*>, <2 x i32*>* %ptr
+  %res = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %ld, i32 0, <2 x i1> %masks, <2 x i32> %passthro)
+  ret <2 x i32> %res
+}
+
+declare <2 x float> @llvm.masked.gather.v2float(<2 x float*> %ptrs, i32 %align, <2 x i1> %masks, <2 x float> %passthro)
+
+define <2 x float> @masked_gather_v2float(<2 x float*>* %ptr, <2 x i1> %masks, <2 x float> %passthro) {
+entry:
+; CHECK64-LABEL: masked_gather_v2float
+; CHECK64: vgatherqps  %xmm{{.*}}, (,%xmm{{.*}}), %xmm{{.*}}
+  %ld  = load <2 x float*>, <2 x float*>* %ptr
+  %res = call <2 x float> @llvm.masked.gather.v2float(<2 x float*> %ld, i32 0, <2 x i1> %masks, <2 x float> %passthro)
+  ret <2 x float> %res
+}
+
+declare <4 x i32> @llvm.masked.gather.v4i32(<4 x i32*> %ptrs, i32 %align, <4 x i1> %masks, <4 x i32> %passthro)
+
+define <4 x i32> @masked_gather_v4i32(<4 x i32*> %ptrs, <4 x i1> %masks, <4 x i32> %passthro) {
+entry:
+; CHECK32-LABEL: masked_gather_v4i32
+; CHECK32: vpgatherdd %xmm{{.*}}, (,%xmm{{.*}}), %xmm{{.*}}
+; CHECK64-LABEL: masked_gather_v4i32
+; CHECK64: vpgatherqd  %xmm{{.*}}, (,%ymm{{.*}}), %xmm{{.*}} 
+  %res = call <4 x i32> @llvm.masked.gather.v4i32(<4 x i32*> %ptrs, i32 0, <4 x i1> %masks, <4 x i32> %passthro)
+  ret <4 x i32> %res
+}
+
+declare <4 x float> @llvm.masked.gather.v4float(<4 x float*> %ptrs, i32 %align, <4 x i1> %masks, <4 x float> %passthro)
+
+define <4 x float> @masked_gather_v4float(<4 x float*> %ptrs, <4 x i1> %masks, <4 x float> %passthro) {
+entry:
+; CHECK32-LABEL: masked_gather_v4float
+; CHECK32: vgatherdps  %xmm{{.*}}, (,%xmm{{.*}}), %xmm{{.*}} 
+; CHECK64-LABEL: masked_gather_v4float
+; CHECK64: vgatherqps  %xmm{{.*}}, (,%ymm{{.*}}), %xmm{{.*}}
+  %res = call <4 x float> @llvm.masked.gather.v4float(<4 x float*> %ptrs, i32 0, <4 x i1> %masks, <4 x float> %passthro)
+  ret <4 x float> %res
+}
+
+declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ptrs, i32 %align, <8 x i1> %masks, <8 x i32> %passthro)
+
+define <8 x i32> @masked_gather_v8i32(<8 x i32*>* %ptr, <8 x i1> %masks, <8 x i32> %passthro) {
+entry:
+; CHECK32-LABEL: masked_gather_v8i32
+; CHECK32:  vpgatherdd  %ymm{{.*}}, (,%ymm{{.*}}), %ymm{{.*}}
+  %ld  = load <8 x i32*>, <8 x i32*>* %ptr
+  %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ld, i32 0, <8 x i1> %masks, <8 x i32> %passthro)
+  ret <8 x i32> %res
+}
+
+declare <8 x float> @llvm.masked.gather.v8float(<8 x float*> %ptrs, i32 %align, <8 x i1> %masks, <8 x float> %passthro)
+
+define <8 x float> @masked_gather_v8float(<8 x float*>* %ptr, <8 x i1> %masks, <8 x float> %passthro) {
+entry:
+; CHECK32-LABEL: masked_gather_v8float
+; CHECK32:  vgatherdps  %ymm{{.*}}, (,%ymm{{.*}}), %ymm{{.*}}
+  %ld  = load <8 x float*>, <8 x float*>* %ptr
+  %res = call <8 x float> @llvm.masked.gather.v8float(<8 x float*> %ld, i32 0, <8 x i1> %masks, <8 x float> %passthro)
+  ret <8 x float> %res
+}
+
+declare <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*> %ptrs, i32 %align, <4 x i1> %masks, <4 x i64> %passthro)
+
+define <4 x i64> @masked_gather_v4i64(<4 x i64*>* %ptr, <4 x i1> %masks, <4 x i64> %passthro) {
+entry:
+; CHECK32-LABEL: masked_gather_v4i64
+; CHECK32:  vpgatherdq  %ymm{{.*}}, (,%xmm{{.*}}), %ymm{{.*}}
+; CHECK64-LABEL: masked_gather_v4i64
+; CHECK64:  vpgatherqq  %ymm{{.*}}, (,%ymm{{.*}}), %ymm{{.*}}
+  %ld  = load <4 x i64*>, <4 x i64*>* %ptr
+  %res = call <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*> %ld, i32 0, <4 x i1> %masks, <4 x i64> %passthro)
+  ret <4 x i64> %res
+}
+
+declare <4 x double> @llvm.masked.gather.v4double(<4 x double*> %ptrs, i32 %align, <4 x i1> %masks, <4 x double> %passthro)
+
+define <4 x double> @masked_gather_v4double(<4 x double*>* %ptr, <4 x i1> %masks, <4 x double> %passthro) {
+entry:
+; CHECK32-LABEL: masked_gather_v4double
+; CHECK32:  vgatherdpd  %ymm{{.*}}, (,%xmm{{.*}}), %ymm{{.*}}
+; CHECK64-LABEL: masked_gather_v4double
+; CHECK64:  vgatherqpd  %ymm{{.*}}, (,%ymm{{.*}}), %ymm{{.*}}
+  %ld  = load <4 x double*>, <4 x double*>* %ptr
+  %res = call <4 x double> @llvm.masked.gather.v4double(<4 x double*> %ld, i32 0, <4 x i1> %masks, <4 x double> %passthro)
+  ret <4 x double> %res
+}
+
+declare <2 x i64> @llvm.masked.gather.v2i64(<2 x i64*> %ptrs, i32 %align, <2 x i1> %masks, <2 x i64> %passthro)
+
+define <2 x i64> @masked_gather_v2i64(<2 x i64*>* %ptr, <2 x i1> %masks, <2 x i64> %passthro) {
+entry:
+; CHECK64-LABEL: masked_gather_v2i64
+; CHECK64:  vpgatherqq  %xmm{{.*}}, (,%xmm{{.*}}), %xmm{{.*}}
+  %ld  = load <2 x i64*>, <2 x i64*>* %ptr
+  %res = call <2 x i64> @llvm.masked.gather.v2i64(<2 x i64*> %ld, i32 0, <2 x i1> %masks, <2 x i64> %passthro)
+  ret <2 x i64> %res
+}
+
+declare <2 x double> @llvm.masked.gather.v2double(<2 x double*> %ptrs, i32 %align, <2 x i1> %masks, <2 x double> %passthro)
+
+define <2 x double> @masked_gather_v2double(<2 x double*>* %ptr, <2 x i1> %masks, <2 x double> %passthro) {
+entry:
+; CHECK64-LABEL: masked_gather_v2double
+; CHECK64:  vgatherqpd  %xmm{{.*}}, (,%xmm{{.*}}), %xmm{{.*}}
+  %ld  = load <2 x double*>, <2 x double*>* %ptr
+  %res = call <2 x double> @llvm.masked.gather.v2double(<2 x double*> %ld, i32 0, <2 x i1> %masks, <2 x double> %passthro)
+  ret <2 x double> %res
+}
+