[GSel]: Support Widening G_ICMP's destination operand.

[aditya_nandakumar]

Added support for G_FCMP as well.

[aditya_nandakumar]

Ping?

[volkan]

Could you add a test case or an explanation if it's not possible to add a test case?

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

611

Could you use local variables for the operands to reduce duplication?

617

The result type is boolean. Why do we need to build a G_FPTRUNC instead of G_TRUNC?

628

Same here.

[aditya_nandakumar]

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

617

Good point. I used G_FPTRUNC to be consistent - but I guess it makes more sense to use G_TRUNC here. I'll update it.

[aditya_nandakumar]

Updated based on feedback.

[volkan]

LGTM except:

• Missing test case
• The title needs be updated

[aditya_nandakumar]

Updated AArch64 G_ICMP/FCMP's destination to be widened to s16. Also updated the test cases.

[t.p.northover]

AArch64 has no 16-bit instructions (at least outside the SIMD unit). The first sensible type to legalize to is s32.

[aditya_nandakumar]

Updated to legalize to s32. (Based on Tim's comment).

[t.p.northover]

Thanks. Looks reasonable to me.

[aditya_nandakumar]

Landed in r309579

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
   }
   case TargetOpcode::G_BRCOND: {
     unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
     MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
     MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
     MI.eraseFromParent();
     return Legalized;
   }
+  case TargetOpcode::G_FCMP: {
+    unsigned Op0Ext, Op1Ext, DstReg;
+    if (TypeIdx == 0) {
+      Op0Ext = MI.getOperand(2).getReg();
+      Op1Ext = MI.getOperand(3).getReg();
+      DstReg = MRI.createGenericVirtualRegister(WideTy);
+    } else {
+      Op0Ext = MRI.createGenericVirtualRegister(WideTy);
+      Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+      DstReg = MI.getOperand(0).getReg();
+      MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op0Ext, MI.getOperand(2).getReg());
+      MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op1Ext, MI.getOperand(3).getReg());
+    }
+    MIRBuilder.buildFCmp(
+        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
+        DstReg, Op0Ext, Op1Ext);
+    if (TypeIdx == 0)
+      MIRBuilder.buildInstr(TargetOpcode::G_FPTRUNC, MI.getOperand(0).getReg(),
+                            DstReg);
+    MI.eraseFromParent();
+    return Legalized;
+  }
   case TargetOpcode::G_ICMP: {
-    assert(TypeIdx == 1 && "unable to legalize predicate");
     bool IsSigned = CmpInst::isSigned(
         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
-    unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
-    unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+    unsigned Op0Ext, Op1Ext, DstReg;
+    if (TypeIdx == 0) {
+      Op0Ext = MI.getOperand(2).getReg();
+      Op1Ext = MI.getOperand(3).getReg();
+      DstReg = MRI.createGenericVirtualRegister(WideTy);
+    } else {
+      Op0Ext = MRI.createGenericVirtualRegister(WideTy);
+      Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+      DstReg = MI.getOperand(0).getReg();
       if (IsSigned) {
         MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
         MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
       } else {
         MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
         MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
       }
+    }
     MIRBuilder.buildICmp(
         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
-        MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
+        DstReg, Op0Ext, Op1Ext);
+    if (TypeIdx == 0)
+      MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
+                            DstReg);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_GEP: {
     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
     unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
     MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
     MI.getOperand(2).setReg(OffsetExt);