[GSel]: Support Widening G_ICMP's destination operand.

[aditya_nandakumar]

Added support for G_FCMP as well.

[aditya_nandakumar]

Ping?

[volkan]

Could you add a test case or an explanation if it's not possible to add a test case?

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

611

Could you use local variables for the operands to reduce duplication?

617

The result type is boolean. Why do we need to build a G_FPTRUNC instead of G_TRUNC?

630

Same here.

[aditya_nandakumar]

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

617

Good point. I used G_FPTRUNC to be consistent - but I guess it makes more sense to use G_TRUNC here. I'll update it.

[aditya_nandakumar]

Updated based on feedback.

[volkan]

LGTM except:

• Missing test case
• The title needs be updated

[aditya_nandakumar]

Updated AArch64 G_ICMP/FCMP's destination to be widened to s16. Also updated the test cases.

[t.p.northover]

AArch64 has no 16-bit instructions (at least outside the SIMD unit). The first sensible type to legalize to is s32.

[aditya_nandakumar]

Updated to legalize to s32. (Based on Tim's comment).

[t.p.northover]

Thanks. Looks reasonable to me.

[aditya_nandakumar]

Landed in r309579

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
   }
   case TargetOpcode::G_BRCOND: {
     unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
     MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
     MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
     MI.eraseFromParent();
     return Legalized;
   }
+  case TargetOpcode::G_FCMP: {
+    unsigned Op0Ext, Op1Ext, DstReg;
+    unsigned Cmp1 = MI.getOperand(2).getReg();
+    unsigned Cmp2 = MI.getOperand(3).getReg();
+    if (TypeIdx == 0) {
+      Op0Ext = Cmp1;
+      Op1Ext = Cmp2;
+      DstReg = MRI.createGenericVirtualRegister(WideTy);
+    } else {
+      Op0Ext = MRI.createGenericVirtualRegister(WideTy);
+      Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+      DstReg = MI.getOperand(0).getReg();
+      MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op0Ext, Cmp1);
+      MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op1Ext, Cmp2);
+    }
+    MIRBuilder.buildFCmp(
+        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
+        DstReg, Op0Ext, Op1Ext);
+    if (TypeIdx == 0)
+      MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
+                            DstReg);
+    MI.eraseFromParent();
+    return Legalized;
+  }
   case TargetOpcode::G_ICMP: {
-    assert(TypeIdx == 1 && "unable to legalize predicate");
     bool IsSigned = CmpInst::isSigned(
         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
-    unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
-    unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+    unsigned Cmp1 = MI.getOperand(2).getReg();
+    unsigned Cmp2 = MI.getOperand(3).getReg();
+    unsigned Op0Ext, Op1Ext, DstReg;
+    if (TypeIdx == 0) {
+      Op0Ext = Cmp1;
+      Op1Ext = Cmp2;
+      DstReg = MRI.createGenericVirtualRegister(WideTy);
+    } else {
+      Op0Ext = MRI.createGenericVirtualRegister(WideTy);
+      Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+      DstReg = MI.getOperand(0).getReg();
       if (IsSigned) {
-      MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
-      MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
+        MIRBuilder.buildSExt(Op0Ext, Cmp1);
+        MIRBuilder.buildSExt(Op1Ext, Cmp2);
       } else {
-      MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
-      MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
+        MIRBuilder.buildZExt(Op0Ext, Cmp1);
+        MIRBuilder.buildZExt(Op1Ext, Cmp2);
+      }
     }
     MIRBuilder.buildICmp(
         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
-        MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
+        DstReg, Op0Ext, Op1Ext);
+    if (TypeIdx == 0)
+      MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
+                            DstReg);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_GEP: {
     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
     unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
     MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
     MI.getOperand(2).setReg(OffsetExt);

lib/Target/AArch64/AArch64InstructionSelector.cpp

 }
 
 bool AArch64InstructionSelector::selectCompareBranch(
     MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
 
   const unsigned CondReg = I.getOperand(0).getReg();
   MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
   MachineInstr *CCMI = MRI.getVRegDef(CondReg);
+  if (CCMI->getOpcode() == TargetOpcode::G_TRUNC)
+    CCMI = MRI.getVRegDef(CCMI->getOperand(1).getReg());
   if (CCMI->getOpcode() != TargetOpcode::G_ICMP)
     return false;
 
   unsigned LHS = CCMI->getOperand(2).getReg();
   unsigned RHS = CCMI->getOperand(3).getReg();
   if (!getConstantVRegVal(RHS, MRI))
     std::swap(RHS, LHS);
 
case TargetOpcode::G_SELECT: {
 
     constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
     constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
 
     I.eraseFromParent();
     return true;
   }
   case TargetOpcode::G_ICMP: {
-    if (Ty != LLT::scalar(1)) {
+    if (Ty != LLT::scalar(32)) {
       DEBUG(dbgs() << "G_ICMP result has type: " << Ty
-                   << ", expected: " << LLT::scalar(1) << '\n');
+                   << ", expected: " << LLT::scalar(32) << '\n');
       return false;
     }
 
     unsigned CmpOpc = 0;
     unsigned ZReg = 0;
 
     LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
     if (CmpTy == LLT::scalar(32)) {
case TargetOpcode::G_ICMP: {
     constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
     constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
 
     I.eraseFromParent();
     return true;
   }
 
   case TargetOpcode::G_FCMP: {
-    if (Ty != LLT::scalar(1)) {
+    if (Ty != LLT::scalar(32)) {
       DEBUG(dbgs() << "G_FCMP result has type: " << Ty
-                   << ", expected: " << LLT::scalar(1) << '\n');
+                   << ", expected: " << LLT::scalar(32) << '\n');
       return false;
     }
 
     unsigned CmpOpc = 0;
     LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
     if (CmpTy == LLT::scalar(32)) {
       CmpOpc = AArch64::FCMPSrr;
     } else if (CmpTy == LLT::scalar(64)) {

lib/Target/AArch64/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo() {
 
   setAction({G_CONSTANT, p0}, Legal);
 
   for (auto Ty : {s1, s8, s16})
     setAction({TargetOpcode::G_CONSTANT, Ty}, WidenScalar);
 
   setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
 
-  setAction({G_ICMP, s1}, Legal);
   setAction({G_ICMP, 1, s32}, Legal);
   setAction({G_ICMP, 1, s64}, Legal);
   setAction({G_ICMP, 1, p0}, Legal);
 
   for (auto Ty : {s1, s8, s16}) {
+    setAction({G_ICMP, Ty}, WidenScalar);
+    setAction({G_FCMP, Ty}, WidenScalar);
     setAction({G_ICMP, 1, Ty}, WidenScalar);
   }
 
-  setAction({G_FCMP, s1}, Legal);
+  setAction({G_ICMP, s32}, Legal);
+  setAction({G_FCMP, s32}, Legal);
   setAction({G_FCMP, 1, s32}, Legal);
   setAction({G_FCMP, 1, s64}, Legal);
 
   // Extensions
   for (auto Ty : { s1, s8, s16, s32, s64 }) {
     setAction({G_ZEXT, Ty}, Legal);
     setAction({G_SEXT, Ty}, Legal);
     setAction({G_ANYEXT, Ty}, Legal);

test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     %0(s64) = COPY %x0
     %1(s64) = COPY %x0
 
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
-    ; CHECK: %4(s1) = G_ICMP intpred(sge), %0(s64), %1
+    ; CHECK: [[CMP1:%[0-9]+]](s32) = G_ICMP intpred(sge), %0(s64), %1
+    ; CHECK: [[CMP_T1:%[0-9]+]](s1) = G_TRUNC [[CMP1]]
     %4(s1) = G_ICMP intpred(sge), %0, %1
 
     ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2
     ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
-    ; CHECK: %8(s1) = G_ICMP intpred(ult), [[LHS32]](s32), [[RHS32]]
+    ; CHECK: [[CMP2:%[0-9]+]](s32) = G_ICMP intpred(ult), [[LHS32]](s32), [[RHS32]]
+    ; CHECK: [[CMP_T2:%[0-9]+]](s1) = G_TRUNC [[CMP2]]
     %8(s1) = G_ICMP intpred(ult), %2, %3
 
     %9(p0) = G_INTTOPTR %0(s64)
     %10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
 ...

test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir

 name:            test_icmp
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
+  - { id: 6, class: _ }
+  - { id: 7, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     %0(s64) = COPY %x0
     %1(s64) = COPY %x0
 
     %2(s32) = G_TRUNC %0
     %3(s32) = G_TRUNC %1
 
-    ; CHECK: %4(s1) = G_FCMP floatpred(oge), %0(s64), %1
-    %4(s1) = G_FCMP floatpred(oge), %0, %1
+    ; CHECK: [[CMP1:%[0-9]+]](s32) = G_FCMP floatpred(oge), %0(s64), %1
+    ; CHECK: [[TRUNC1:%[0-9]+]](s1) = G_TRUNC [[CMP1]]
+    %4(s32) = G_FCMP floatpred(oge), %0, %1
+    %6(s1) = G_TRUNC %4(s32)
 
-    ; CHECK: %5(s1) = G_FCMP floatpred(uno), %2(s32), %3
-    %5(s1) = G_FCMP floatpred(uno), %2, %3
+    ; CHECK: [[CMP2:%[0-9]+]](s32) = G_FCMP floatpred(uno), %2(s32), %3
+    ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[CMP2]]
+    %5(s32) = G_FCMP floatpred(uno), %2, %3
+    %7(s1) = G_TRUNC %5(s32)
 ...

test/CodeGen/AArch64/GlobalISel/legalize-mul.mir

bb.0:
 
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
 
     ; CHECK-LABEL: name: test_mul_overflow
     ; CHECK: %2(s64) = G_MUL %0, %1
     ; CHECK: [[HI:%[0-9]+]](s64) = G_SMULH %0, %1
     ; CHECK: [[ZERO:%[0-9]+]](s64) = G_CONSTANT i64 0
-    ; CHECK: %3(s1) = G_ICMP intpred(ne), [[HI]](s64), [[ZERO]]
+    ; CHECK: [[CMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[HI]](s64), [[ZERO]]
+    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[CMP]]
     %2:_(s64), %3:_(s1) = G_SMULO %0, %1
 
 ...

test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

 name:            test_icmp_s32
 legalized:       true
 # CHECK: registers:
 # CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 # CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
+  - { id: 2, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s1) = G_ICMP intpred(ne), %0(s32), %0
+    ; CHECK:      %1(s32) = G_ICMP intpred(ne), %0(s32), %0
+    ; CHECK:      %2(s1) = G_TRUNC %1(s32)
     %0(s32) = COPY %w0
-    %1(s1) = G_ICMP intpred(ne), %0, %0
+    %1(s32) = G_ICMP intpred(ne), %0, %0
+    %2(s1) = G_TRUNC %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: test_icmp_p0
 name:            test_icmp_p0
 legalized:       true
 # CHECK: registers:
 # CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 # CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
+  - { id: 2, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK:      %0(p0) = COPY %x0
-    ; CHECK:      %1(s1) = G_ICMP intpred(ne), %0(p0), %0
+    ; CHECK:      %1(s32) = G_ICMP intpred(ne), %0(p0), %0
+    ; CHECK:      %2(s1) = G_TRUNC %1(s32)
     %0(p0) = COPY %x0
-    %1(s1) = G_ICMP intpred(ne), %0, %0
+    %1(s32) = G_ICMP intpred(ne), %0, %0
+    %2(s1) = G_TRUNC %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: test_frame_index_p0
 name:            test_frame_index_p0
 legalized:       true
 # CHECK: registers:
 # CHECK:   - { id: 0, class: gpr, preferred-register: '' }

 name:            test_fcmp_s32
 legalized:       true
 # CHECK: registers:
 # CHECK:   - { id: 0, class: fpr, preferred-register: '' }
 # CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
+  - { id: 2, class: _ }
 body: |
   bb.0:
     liveins: %s0
     ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s1) = G_FCMP floatpred(olt), %0(s32), %0
+    ; CHECK:      [[FCMP:%[0-9]+]](s32) = G_FCMP floatpred(olt), %0(s32), %0
+    ; CHECK:      [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FCMP]]
     %0(s32) = COPY %s0
-    %1(s1) = G_FCMP floatpred(olt), %0, %0
+    %1(s32) = G_FCMP floatpred(olt), %0, %0
+    %2(s1) = G_TRUNC %1(s32)
 ...
 
 ---
 # CHECK-LABEL: name: test_sitofp_s64_s32
 name:            test_sitofp_s64_s32
 legalized:       true
 # CHECK: registers:
 # CHECK:   - { id: 0, class: gpr, preferred-register: '' }

test/CodeGen/AArch64/GlobalISel/select-cbz.mir

 # CHECK:    B %bb.0
 body:             |
   bb.0:
     liveins: %w0
     successors: %bb.0, %bb.1
 
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_CONSTANT i32 0
-    %2:gpr(s1) = G_ICMP intpred(eq), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 # CHECK-LABEL: name: cbz_s64
 name:            cbz_s64
 legalized:       true
 regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
 # CHECK:    %0 = COPY %x0
 # CHECK:    CBZX %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
   bb.0:
     liveins: %x0
     successors: %bb.0, %bb.1
 
     %0:gpr(s64) = COPY %x0
     %1:gpr(s64) = G_CONSTANT i64 0
-    %2:gpr(s1) = G_ICMP intpred(eq), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 # CHECK-LABEL: name: cbnz_s32
 name:            cbnz_s32
 legalized:       true
 regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
 # CHECK:    %0 = COPY %w0
 # CHECK:    CBNZW %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
   bb.0:
     liveins: %w0
     successors: %bb.0, %bb.1
 
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_CONSTANT i32 0
-    %2:gpr(s1) = G_ICMP intpred(ne), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 # CHECK-LABEL: name: cbnz_s64
 name:            cbnz_s64
 legalized:       true
 regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
 # CHECK:    %0 = COPY %x0
 # CHECK:    CBNZX %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
   bb.0:
     liveins: %x0
     successors: %bb.0, %bb.1
 
     %0:gpr(s64) = COPY %x0
     %1:gpr(s64) = G_CONSTANT i64 0
-    %2:gpr(s1) = G_ICMP intpred(ne), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
 ...

test/CodeGen/AArch64/GlobalISel/select.mir

 # CHECK-NEXT:  - { id: 5, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+  - { id: 8, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %wzr = SUBSWrr %0, %0, implicit-def %nzcv
 # CHECK:    %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
 
 # CHECK:    %xzr = SUBSXrr %2, %2, implicit-def %nzcv
 # CHECK:    %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
 
 # CHECK:    %xzr = SUBSXrr %4, %4, implicit-def %nzcv
 # CHECK:    %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
 
 body:             |
   bb.0:
     liveins: %w0, %x0
 
     %0(s32) = COPY %w0
-    %1(s1) = G_ICMP intpred(eq), %0, %0
-    %w0 = COPY %1(s1)
+    %1(s32) = G_ICMP intpred(eq), %0, %0
+    %6(s1) = G_TRUNC %1(s32)
+    %w0 = COPY %6(s1)
 
     %2(s64) = COPY %x0
-    %3(s1) = G_ICMP intpred(uge), %2, %2
-    %w0 = COPY %3(s1)
+    %3(s32) = G_ICMP intpred(uge), %2, %2
+    %7(s1) = G_TRUNC %3(s32)
+    %w0 = COPY %7(s1)
 
     %4(p0) = COPY %x0
-    %5(s1) = G_ICMP intpred(ne), %4, %4
-    %w0 = COPY %5(s1)
+    %5(s32) = G_ICMP intpred(ne), %4, %4
+    %8(s1) = G_TRUNC %5(s32)
+    %w0 = COPY %8(s1)
 ...
 
 ---
 # CHECK-LABEL: name: fcmp
 name:            fcmp
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 4, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 5, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
 
 # CHECK:  body:
 # CHECK:    FCMPSrr %0, %0, implicit-def %nzcv
 # CHECK:    [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv
 # CHECK:    [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv
 # CHECK:    %1 = ORRWrr [[TST_MI]], [[TST_GT]]
 
 # CHECK:    FCMPDrr %2, %2, implicit-def %nzcv
 # CHECK:    %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
 
 body:             |
   bb.0:
     liveins: %w0, %x0
 
     %0(s32) = COPY %s0
-    %1(s1) = G_FCMP floatpred(one), %0, %0
-    %w0 = COPY %1(s1)
+    %1(s32) = G_FCMP floatpred(one), %0, %0
+    %4(s1) = G_TRUNC %1(s32)
+    %w0 = COPY %4(s1)
 
     %2(s64) = COPY %d0
-    %3(s1) = G_FCMP floatpred(uge), %2, %2
-    %w0 = COPY %3(s1)
+    %3(s32) = G_FCMP floatpred(uge), %2, %2
+    %5(s1) = G_TRUNC %3(s32)
+    %w0 = COPY %5(s1)
 
 ...
 
 ---
 # CHECK-LABEL: name: phi
 name:            phi
 legalized:       true
 regBankSelected: true