AMDGPU: Add encodings for global atomics

[vpykhtin]

LGTM.

[arsenm]

r308638

lib/Target/AMDGPU/FLATInstructions.td

multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
   }
 }
 
 class FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> :
   FLAT_Store_Pseudo<opName, regClass, 1> {
   let is_flat_scratch = 1;
 }
 
+class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
+                               string asm, list<dag> pattern = []> :
+  FLAT_Pseudo<opName, outs, ins, asm, pattern> {
+    let mayLoad = 1;
+    let mayStore = 1;
+    let has_glc  = 0;
+    let glcValue = 0;
+    let has_vdst = 0;
+}
+
+class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
+                            string asm, list<dag> pattern = []>
+  : FLAT_AtomicNoRet_Pseudo<opName, outs, ins, asm, pattern> {
+  let hasPostISelHook = 1;
+  let has_vdst = 1;
+  let glcValue = 1;
+  let PseudoInstr = NAME # "_RTN";
+}
+
 multiclass FLAT_Atomic_Pseudo<
   string opName,
   RegisterClass vdst_rc,
   ValueType vt,
   SDPatternOperator atomic = null_frag,
   ValueType data_vt = vt,
-  RegisterClass data_rc = vdst_rc,
-  bit HasSignedOffset = 0> {
+  RegisterClass data_rc = vdst_rc> {
+  def "" : FLAT_AtomicNoRet_Pseudo <opName,
+    (outs),
+    (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
+    " $vaddr, $vdata$offset$slc">,
+    AtomicNoRet <opName, 0> {
+    let PseudoInstr = NAME;
+  }
+
+  def _RTN : FLAT_AtomicRet_Pseudo <opName,
+    (outs vdst_rc:$vdst),
+    (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
+    " $vdst, $vaddr, $vdata$offset glc$slc",
+    [(set vt:$vdst,
+      (atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
+       AtomicNoRet <opName, 1>;
+}
 
-  def "" : FLAT_Pseudo <opName,
+multiclass FLAT_Global_Atomic_Pseudo<
+  string opName,
+  RegisterClass vdst_rc,
+  ValueType vt,
+  SDPatternOperator atomic = null_frag,
+  ValueType data_vt = vt,
+  RegisterClass data_rc = vdst_rc> {
+
+  def "" : FLAT_AtomicNoRet_Pseudo <opName,
     (outs),
-    !if(HasSignedOffset,
-      (ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
-      (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc)),
-    " $vaddr, $vdata$offset$slc",
-    []>,
-    AtomicNoRet <NAME, 0> {
-    let mayLoad = 1;
-    let mayStore = 1;
-    let has_glc  = 0;
-    let glcValue = 0;
-    let has_vdst = 0;
+    " $vaddr, $vdata, off$offset$slc">,
+    AtomicNoRet <opName, 0> {
+    let has_saddr = 1;
     let PseudoInstr = NAME;
   }
 
-  def _RTN : FLAT_Pseudo <opName,
+  def _RTN : FLAT_AtomicRet_Pseudo <opName,
     (outs vdst_rc:$vdst),
-    !if(HasSignedOffset,
       (ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
-      (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc)),
-    " $vdst, $vaddr, $vdata$offset glc$slc",
+    " $vdst, $vaddr, $vdata, off$offset glc$slc",
     [(set vt:$vdst,
       (atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
-    AtomicNoRet <NAME, 1> {
-    let mayLoad  = 1;
-    let mayStore = 1;
-    let hasPostISelHook = 1;
-    let has_glc  = 0;
-    let glcValue = 1;
-    let PseudoInstr = NAME # "_RTN";
+      AtomicNoRet <opName, 1> {
+    let has_saddr = 1;
+  }
+
+  def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
+    (outs),
+    (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
+    " $vaddr, $vdata$saddr$offset$slc">,
+    AtomicNoRet <opName#"_saddr", 0> {
+    let has_saddr = 1;
+    let enabled_saddr = 1;
+    let PseudoInstr = NAME#"_SADDR";
+  }
+
+  def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
+    (outs vdst_rc:$vdst),
+      (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
+    " $vdst, $vaddr, $vdata$saddr$offset glc$slc">,
+    AtomicNoRet <opName#"_saddr", 1> {
+     let has_saddr = 1;
+     let enabled_saddr = 1;
+     let PseudoInstr = NAME#"_SADDR_RTN";
   }
 }
 
 class flat_binary_atomic_op<SDNode atomic_op> : PatFrag<
   (ops node:$ptr, node:$value),
   (atomic_op node:$ptr, node:$value),
   [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.FLAT_ADDRESS;}]
 >;

 
 defm GLOBAL_STORE_BYTE    : FLAT_Global_Store_Pseudo <"global_store_byte", VGPR_32>;
 defm GLOBAL_STORE_SHORT   : FLAT_Global_Store_Pseudo <"global_store_short", VGPR_32>;
 defm GLOBAL_STORE_DWORD   : FLAT_Global_Store_Pseudo <"global_store_dword", VGPR_32>;
 defm GLOBAL_STORE_DWORDX2 : FLAT_Global_Store_Pseudo <"global_store_dwordx2", VReg_64>;
 defm GLOBAL_STORE_DWORDX3 : FLAT_Global_Store_Pseudo <"global_store_dwordx3", VReg_96>;
 defm GLOBAL_STORE_DWORDX4 : FLAT_Global_Store_Pseudo <"global_store_dwordx4", VReg_128>;
 
+
+let is_flat_global = 1 in {
+defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap",
+                               VGPR_32, i32, AMDGPUatomic_cmp_swap_global,
+                               v2i32, VReg_64>;
+
+defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap_x2",
+                                  VReg_64, i64, AMDGPUatomic_cmp_swap_global,
+                                  v2i64, VReg_128>;
+
+defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_swap",
+                             VGPR_32, i32, atomic_swap_global>;
+
+defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_swap_x2",
+                                VReg_64, i64, atomic_swap_global>;
+
+defm GLOBAL_ATOMIC_ADD : FLAT_Global_Atomic_Pseudo <"global_atomic_add",
+                           VGPR_32, i32, atomic_add_global>;
+
+defm GLOBAL_ATOMIC_SUB : FLAT_Global_Atomic_Pseudo <"global_atomic_sub",
+                           VGPR_32, i32, atomic_sub_global>;
+
+defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_smin",
+                            VGPR_32, i32, atomic_min_global>;
+
+defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_umin",
+                            VGPR_32, i32, atomic_umin_global>;
+
+defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_smax",
+                            VGPR_32, i32, atomic_max_global>;
+
+defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_umax",
+                            VGPR_32, i32, atomic_umax_global>;
+
+defm GLOBAL_ATOMIC_AND : FLAT_Global_Atomic_Pseudo <"global_atomic_and",
+                           VGPR_32, i32, atomic_and_global>;
+
+defm GLOBAL_ATOMIC_OR : FLAT_Global_Atomic_Pseudo <"global_atomic_or",
+                          VGPR_32, i32, atomic_or_global>;
+
+defm GLOBAL_ATOMIC_XOR : FLAT_Global_Atomic_Pseudo <"global_atomic_xor",
+                           VGPR_32, i32, atomic_xor_global>;
+
+defm GLOBAL_ATOMIC_INC : FLAT_Global_Atomic_Pseudo <"global_atomic_inc",
+                           VGPR_32, i32, atomic_inc_global>;
+
+defm GLOBAL_ATOMIC_DEC : FLAT_Global_Atomic_Pseudo <"global_atomic_dec",
+                           VGPR_32, i32, atomic_dec_global>;
+
+defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_add_x2",
+                              VReg_64, i64, atomic_add_global>;
+
+defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_sub_x2",
+                              VReg_64, i64, atomic_sub_global>;
+
+defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smin_x2",
+                               VReg_64, i64, atomic_min_global>;
+
+defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umin_x2",
+                               VReg_64, i64, atomic_umin_global>;
+
+defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smax_x2",
+                               VReg_64, i64, atomic_max_global>;
+
+defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umax_x2",
+                               VReg_64, i64, atomic_umax_global>;
+
+defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_and_x2",
+                              VReg_64, i64, atomic_and_global>;
+
+defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_or_x2",
+                             VReg_64, i64, atomic_or_global>;
+
+defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_xor_x2",
+                              VReg_64, i64, atomic_xor_global>;
+
+defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_inc_x2",
+                              VReg_64, i64, atomic_inc_global>;
+
+defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_dec_x2",
+                              VReg_64, i64, atomic_dec_global>;
+} // End is_flat_global = 1
+
 } // End SubtargetPredicate = HasFlatGlobalInsts
 
 
 //===----------------------------------------------------------------------===//
 // Flat Patterns
 //===----------------------------------------------------------------------===//
 
 class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),

 def FLAT_STORE_DWORDX4_vi      : FLAT_Real_vi <0x1f, FLAT_STORE_DWORDX4>;
 def FLAT_STORE_DWORDX3_vi      : FLAT_Real_vi <0x1e, FLAT_STORE_DWORDX3>;
 
 multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
   def _vi     : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
   def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
 }
 
+multiclass FLAT_Global_Real_Atomics_vi<bits<7> op> :
+  FLAT_Real_AllAddr_vi<op> {
+  def _RTN_vi  : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
+  def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
+}
+
+
 defm FLAT_ATOMIC_SWAP       : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
 defm FLAT_ATOMIC_CMPSWAP    : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
 defm FLAT_ATOMIC_ADD        : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
 defm FLAT_ATOMIC_SUB        : FLAT_Real_Atomics_vi <0x43, FLAT_ATOMIC_SUB>;
 defm FLAT_ATOMIC_SMIN       : FLAT_Real_Atomics_vi <0x44, FLAT_ATOMIC_SMIN>;
 defm FLAT_ATOMIC_UMIN       : FLAT_Real_Atomics_vi <0x45, FLAT_ATOMIC_UMIN>;
 defm FLAT_ATOMIC_SMAX       : FLAT_Real_Atomics_vi <0x46, FLAT_ATOMIC_SMAX>;
 defm FLAT_ATOMIC_UMAX       : FLAT_Real_Atomics_vi <0x47, FLAT_ATOMIC_UMAX>;

 defm GLOBAL_LOAD_DWORDX3 : FLAT_Real_AllAddr_vi <0x16>;
 
 defm GLOBAL_STORE_BYTE : FLAT_Real_AllAddr_vi <0x18>;
 defm GLOBAL_STORE_SHORT : FLAT_Real_AllAddr_vi <0x1a>;
 defm GLOBAL_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>;
 defm GLOBAL_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
 defm GLOBAL_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
 defm GLOBAL_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
+
+defm GLOBAL_ATOMIC_SWAP       : FLAT_Global_Real_Atomics_vi <0x40>;
+defm GLOBAL_ATOMIC_CMPSWAP    : FLAT_Global_Real_Atomics_vi <0x41>;
+defm GLOBAL_ATOMIC_ADD        : FLAT_Global_Real_Atomics_vi <0x42>;
+defm GLOBAL_ATOMIC_SUB        : FLAT_Global_Real_Atomics_vi <0x43>;
+defm GLOBAL_ATOMIC_SMIN       : FLAT_Global_Real_Atomics_vi <0x44>;
+defm GLOBAL_ATOMIC_UMIN       : FLAT_Global_Real_Atomics_vi <0x45>;
+defm GLOBAL_ATOMIC_SMAX       : FLAT_Global_Real_Atomics_vi <0x46>;
+defm GLOBAL_ATOMIC_UMAX       : FLAT_Global_Real_Atomics_vi <0x47>;
+defm GLOBAL_ATOMIC_AND        : FLAT_Global_Real_Atomics_vi <0x48>;
+defm GLOBAL_ATOMIC_OR         : FLAT_Global_Real_Atomics_vi <0x49>;
+defm GLOBAL_ATOMIC_XOR        : FLAT_Global_Real_Atomics_vi <0x4a>;
+defm GLOBAL_ATOMIC_INC        : FLAT_Global_Real_Atomics_vi <0x4b>;
+defm GLOBAL_ATOMIC_DEC        : FLAT_Global_Real_Atomics_vi <0x4c>;
+defm GLOBAL_ATOMIC_SWAP_X2    : FLAT_Global_Real_Atomics_vi <0x60>;
+defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Real_Atomics_vi <0x61>;
+defm GLOBAL_ATOMIC_ADD_X2     : FLAT_Global_Real_Atomics_vi <0x62>;
+defm GLOBAL_ATOMIC_SUB_X2     : FLAT_Global_Real_Atomics_vi <0x63>;
+defm GLOBAL_ATOMIC_SMIN_X2    : FLAT_Global_Real_Atomics_vi <0x64>;
+defm GLOBAL_ATOMIC_UMIN_X2    : FLAT_Global_Real_Atomics_vi <0x65>;
+defm GLOBAL_ATOMIC_SMAX_X2    : FLAT_Global_Real_Atomics_vi <0x66>;
+defm GLOBAL_ATOMIC_UMAX_X2    : FLAT_Global_Real_Atomics_vi <0x67>;
+defm GLOBAL_ATOMIC_AND_X2     : FLAT_Global_Real_Atomics_vi <0x68>;
+defm GLOBAL_ATOMIC_OR_X2      : FLAT_Global_Real_Atomics_vi <0x69>;
+defm GLOBAL_ATOMIC_XOR_X2     : FLAT_Global_Real_Atomics_vi <0x6a>;
+defm GLOBAL_ATOMIC_INC_X2     : FLAT_Global_Real_Atomics_vi <0x6b>;
+defm GLOBAL_ATOMIC_DEC_X2     : FLAT_Global_Real_Atomics_vi <0x6c>;

test/MC/AMDGPU/flat-global.s

 
 global_load_dwordx3 v[1:3], v[3:4], off
 // GFX9: global_load_dwordx3 v[1:3], v[3:4], off ; encoding: [0x00,0x80,0x58,0xdc,0x03,0x00,0x7f,0x01]
 // VI-ERR: instruction not supported on this GPU
 
 global_load_dwordx4 v[1:4], v[3:4], off
 // GFX9: global_load_dwordx4 v[1:4], v[3:4], off   ; encoding: [0x00,0x80,0x5c,0xdc,0x03,0x00,0x7f,0x01]
 // VI-ERR: instruction not supported on this GPU
+
 // FIXME: VI error should be instruction nto supported
 global_load_dword v1, v[3:4], off offset:0
 // GFX9: global_load_dword v1, v[3:4], off    ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
 // VI-ERR: :41: error: not a valid operand.
 
 global_load_dword v1, v[3:4], off offset:4095
 // GFX9: global_load_dword v1, v[3:4], off offset:4095 ; encoding: [0xff,0x8f,0x50,0xdc,0x03,0x00,0x7f,0x01]
 // VI-ERR: :41: error: not a valid operand.

 
 global_load_dword v1, v[3:4], s2
 // GFX9-ERR: :31: error: invalid operand for instruction
 // VI-ERR: :31: error: invalid operand for instruction
 
 global_load_dword v1, v[3:4], exec_hi
 // GFX9-ERR: :31: error: invalid operand for instruction
 // VI-ERR: :31: error: invalid operand for instruction
+
+global_atomic_cmpswap v[3:4], v[5:6], off
+// GFX9: global_atomic_cmpswap v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x04,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap_x2 v[3:4], v[5:8], off
+// GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off ; encoding: [0x00,0x80,0x84,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_swap v[3:4], v5, off
+// GFX9: global_atomic_swap v[3:4], v5, off   ; encoding: [0x00,0x80,0x00,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_swap_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x80,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_add v[3:4], v5, off
+// GFX9: global_atomic_add v[3:4], v5, off   ; encoding: [0x00,0x80,0x08,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_sub v[3:4], v5, off
+// GFX9: global_atomic_sub v[3:4], v5, off    ; encoding: [0x00,0x80,0x0c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_smin v[3:4], v5, off
+// GFX9: global_atomic_smin v[3:4], v5, off   ; encoding: [0x00,0x80,0x10,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_umin v[3:4], v5, off
+// GFX9: global_atomic_umin v[3:4], v5, off   ; encoding: [0x00,0x80,0x14,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_smax v[3:4], v5, off
+// GFX9: global_atomic_smax v[3:4], v5, off   ; encoding: [0x00,0x80,0x18,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_umax v[3:4], v5, off
+// GFX9: global_atomic_umax v[3:4], v5, off   ; encoding: [0x00,0x80,0x1c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_and v[3:4], v5, off
+// GFX9: global_atomic_and v[3:4], v5, off    ; encoding: [0x00,0x80,0x20,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_or v[3:4], v5, off
+// GFX9: global_atomic_or v[3:4], v5, off     ; encoding: [0x00,0x80,0x24,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_xor v[3:4], v5, off
+// GFX9: global_atomic_xor v[3:4], v5, off    ; encoding: [0x00,0x80,0x28,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_inc v[3:4], v5, off
+// GFX9: global_atomic_inc v[3:4], v5, off    ; encoding: [0x00,0x80,0x2c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_dec v[3:4], v5, off
+// GFX9: global_atomic_dec v[3:4], v5, off    ; encoding: [0x00,0x80,0x30,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_add_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_add_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x88,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_sub_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x8c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_smin_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x90,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_umin_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x94,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_smax_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x98,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_umax_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x9c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_and_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_and_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa0,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_or_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_or_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa4,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_xor_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa8,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_inc_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xac,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: instruction not supported on this GPU
+
+global_atomic_dec_x2 v[3:4], v[5:6], off
+// GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xb0,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_cmpswap v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x04,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :49: error: not a valid operand.
+
+global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16
+// GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16 ; encoding: [0xf0,0x9f,0x84,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :52: error: not a valid operand.
+
+global_atomic_swap v[3:4], v5, off offset:-16
+// GFX9: global_atomic_swap v[3:4], v5, off   offset:-16 ; encoding: [0xf0,0x9f,0x00,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :42: error: not a valid operand
+
+global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x80,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :49: error: not a valid operand
+
+global_atomic_add v[3:4], v5, off offset:-16
+// GFX9: global_atomic_add v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x08,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :41: error: not a valid operand
+
+global_atomic_sub v[3:4], v5, off offset:-16
+// GFX9: global_atomic_sub v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x0c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :41: error: not a valid operand
+
+global_atomic_smin v[3:4], v5, off offset:-16
+// GFX9: global_atomic_smin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x10,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :42: error: not a valid operand
+
+global_atomic_umin v[3:4], v5, off offset:-16
+// GFX9: global_atomic_umin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x14,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :42: error: not a valid operand
+
+global_atomic_smax v[3:4], v5, off offset:-16
+// GFX9: global_atomic_smax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x18,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :42: error: not a valid operand
+
+global_atomic_umax v[3:4], v5, off offset:-16
+// GFX9: global_atomic_umax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x1c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :42: error: not a valid operand
+
+global_atomic_and v[3:4], v5, off offset:-16
+// GFX9: global_atomic_and v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x20,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :41: error: not a valid operand
+
+global_atomic_or v[3:4], v5, off offset:-16
+// GFX9: global_atomic_or v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x24,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :40: error: not a valid operand
+
+global_atomic_xor v[3:4], v5, off offset:-16
+// GFX9: global_atomic_xor v[3:4], v5, off  offset:-16 ; encoding: [0xf0,0x9f,0x28,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :41: error: not a valid operand
+
+global_atomic_inc v[3:4], v5, off offset:-16
+// GFX9: global_atomic_inc v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x2c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :41: error: not a valid operand
+
+global_atomic_dec v[3:4], v5, off offset:-16
+// GFX9: global_atomic_dec v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x30,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :41: error: not a valid operand
+
+global_atomic_add_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_add_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x88,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :48: error: not a valid operand
+
+global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x8c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :48: error: not a valid operand
+
+global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x90,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :49: error: not a valid operand
+
+global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x94,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :49: error: not a valid operand
+
+global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x98,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :49: error: not a valid operand
+
+global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x9c,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :49: error: not a valid operand
+
+global_atomic_and_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_and_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa0,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :48: error: not a valid operand
+
+global_atomic_or_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_or_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa4,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :47: error: not a valid operand
+
+global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa8,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :48: error: not a valid operand
+
+global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xac,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :48: error: not a valid operand
+
+global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16
+// GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xb0,0xdd,0x03,0x05,0x7f,0x00]
+// VI-ERR: :48: error: not a valid operand