Removal of microMIPS64R6

[abeserminji]

Summary

All files and parts of files related to microMips64r6 are removed.
When target is micromips64r6, errors are printed.

This is LLVM part of patch. Clang part of patch can be found here: https://reviews.llvm.org/D35624

Depends on: D37682 and D37683

[sdardis]

Some minor comments.

CodeGen/Mips/tailcall/tailcall.ll

31 ↗

(On Diff #107303)

Spurious blank line.

Target/Mips/MipsSubtarget.cpp

107 ↗

(On Diff #107303)

The error message should be "microMIPS64R6 is not supported".

Target/Mips/MipsTargetMachine.cpp

181 ↗

(On Diff #107303)

mircomips -> microMIPS.

[abeserminji]

Comments resolved.

[abeserminji]

Comments resolved.

[sdardis]

There's also a mention of micromips64r6 in lib/Target/Mips/Relocations.txt, so that file needs to be kept up to date.

Target/Mips/MicroMips64r6InstrInfo.td

481–482 ↗

(On Diff #108077)

This multiclass can be flattened as it is no longer required.

[sdardis]

Flagging this as changes required.

[abeserminji]

Relocation.txt updated.
Multiclass MipsHighestHigherHiLoRelocs flattened.

Added dependencies.

[abeserminji]

Last revision also included some changes on test/MC/Mips/mips64r6/invalid.s, which should not be in this patch.

[abeserminji]

Patch updated to follow latest revision.

[sdardis]

The GPRMM16_64 register class needs to be removed as well. It's used in the MipsMachineFunction.cpp and MipsRegisterInfo.cpp.

lib/Target/Mips/MipsDelaySlotFiller.cpp

601–602 ↗

(On Diff #115401)

"This is the microMIPS32R6 subtarget which does not have instructions which have delay slots."

[sdardis]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

1070–1071

Unused variable.

1110–1111

Unused variable.

[abeserminji]

Comments resolved.

[sdardis]

Can you also remove the instruction mappings for the R6 variants of dbitswap, dclo, dclz, dlsa, lld, lwupc and ldpc ?

lib/Target/Mips/Mips64InstrInfo.td

102

This instruction no longer has a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.

123–129

These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.

144–178

These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.

194–201

These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.

224

This instruction no longer has a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.

302–305

These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.

[abeserminji]

Removed unnecessary annotations.

btw. out of curiosity haven't these StdMMR6Rel's been in contradiction with NotInMicroMips additional predicate?

[sdardis]

For SelectionDAGISel purposes, these instruction mappings were spurious as SelectionDAGISel would pick the corresponding microMIPS instruction due to the various predicates. If however, these instructions were introduced by the likes of MipsSEISelLowering or MipsSEISelDAGToDAG, etc, we'd end up with a mixture of MIPS and microMIPS code. This isn't a problem when producing assembly, as the textual representation is the same, but for object emission we need to produce the correct opcodes. The instruction mapping tables quietly "fixup" the usage of MIPS opcodes in microMIPS code which simplifies injecting instructions by hand in cpp as we don't have to constantly do things like:

BuildMI(MBB, I, DL, TII.get(STI.inMicroMips ? Mips::DADDU_MMR6 : Mips::DADDu), V1).addReg(V0)

throughout the codebase.

[sdardis]

Can you remove the StdMMR6Rel from the R6 instructions dbitswap, dclo, dclz, dlsa, lld, lwupc and ldpc ?

[abeserminji]

Comment resolved.

[sdardis]

Probably my last round of comments on this, also can you add a trivial test case showing that microMIPS64R6 is not supported?

lib/Target/Mips/MicroMipsInstrInfo.td

590–602

Align the format class instantiations / ISA predicates under instruction codegen description instantiations.

650–652

The ISA_MICROMIPS_NOT_32R6 needs to be aligned under the BrkSdbbp16MM.

lib/Target/Mips/MicroMipsSizeReduction.cpp

498

for the subtarget microMIPS32R6.

lib/Target/Mips/MipsTargetMachine.cpp

188–192 ↗

(On Diff #118596)

Take the context from the current Function and use emitError giving the function name + error message.

See include/llvm/IR/LLVMContext.h:300~ for emitError.

test/CodeGen/Mips/llvm-ir/and.ll

42–43

Remove this.

57–58

Remove this.

72–73

Remove this.

test/CodeGen/Mips/llvm-ir/mul.ll

248–249

Remove this.

test/CodeGen/Mips/llvm-ir/not.ll

131–132

Remove this.

144–145

Remove this.

157–158

Remove this.

test/CodeGen/Mips/llvm-ir/or.ll

32

Remove this.

44–45

Remove this.

59–60

Remove this.

test/CodeGen/Mips/llvm-ir/xor.ll

43

Remove this.

55–56

Remove this.

70–71

Remove this.

[abeserminji]

Added test that tests that microMIPS64R6 is not supported anymore.
Comments resolved.

[abeserminji]

lib/Target/Mips/MipsTargetMachine.cpp

188–192 ↗

(On Diff #118596)

I removed this check here, because I was not able to reproduce the error at this place. The check in MipsSubtarget.cpp at 107 always performs first, so this seemed to me like unnecessary thing. Although, correct me if I'm wrong, I might missed some case where this is called before the mentioned check in MipsSubtarget.cpp.

[sdardis]

I missed the AsmParser in my last reviews, can you add checks there, in the initialisation, in parseSetArchDirective and parseDirectiveSet?

lib/Target/Mips/MipsSubtarget.cpp

108

Pass false as the second argument here, so that we don't emit a crash diagnostic.

lib/Target/Mips/MipsTargetMachine.cpp

188–192 ↗

(On Diff #118596)

As far as I can see, this check can be dropped.

test/CodeGen/Mips/micromips-64r6-disabled.ll

1 ↗

(On Diff #119281)

This file should be called micromips64r6-unsupported.ll.

3 ↗

(On Diff #119281)

Test that microMIPS64R6 is not supported.

[abeserminji]

Comments addressed.

[sdardis]

You've missed my comment:

I missed the AsmParser in my last reviews, can you add checks there, in the initialisation, in parseSetArchDirective and parseDirectiveSet?

[abeserminji]

Hi Simon,
Sorry about missing your comment.
I added necessary checks, but I added only for two cases:

1. when cpu=mips64r6 and micromips option is used
2. when cpu=mips64r6 and micromips directive is used

I couldn't find any other cases, so I added checks to the constructor and parseDirectiveSet(). Is there some case that I missed that could call parseSetArchDirective() without triggering current checks?
Also, I added a test that checks these errors.

[sdardis]

.set  micromips
.set  arch=mips64r6
nop

covers the parseSetArchDirective case.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

516

Don't use STI directly here, use getSTI() instead.

7163

Check here if the assembler is in micromips mode.

[abeserminji]

Comments addressed.

[abeserminji]

test/MC/Mips/micromips64r6-unsupported.s

15 ↗

(On Diff #123941)

I made different error messages here on purpose, so that it is clear which part of code is tested.

[sdardis]

LTGM with the inlined nits addressed, along with any other changes that have to be made during rebasing before commit provided they're obvious/minor.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

7124

".set micromips directive is not supported with MIPS64R6"

7160

"MIPS64R6 is not supported with microMIPS"

[abeserminji]

Comments resolved.
Rebase against latest master.

[abeserminji]

Last update doesn't contain deleted files. Fixed that.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
     CpRestoreOffset = -1;
 
     const Triple &TheTriple = sti.getTargetTriple();
     if ((TheTriple.getArch() == Triple::mips) ||
         (TheTriple.getArch() == Triple::mips64))
       IsLittleEndian = false;
     else
       IsLittleEndian = true;
+
+    if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
+      report_fatal_error("microMIPS64R6 is not supported", false);
   }
 
   /// True if all of $fcc0 - $fcc7 exist for the current ISA.
   bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
 
   bool isGP64bit() const {
     return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
   }
bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::DSDivMacro:
   case Mips::UDivMacro:
   case Mips::DUDivMacro:
   case Mips::DIV:
   case Mips::DIVU:
   case Mips::DDIV:
   case Mips::DDIVU:
   case Mips::DIVU_MMR6:
-  case Mips::DDIVU_MM64R6:
   case Mips::DIV_MMR6:
-  case Mips::DDIV_MM64R6:
     if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
         Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
       if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
           Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
         Warning(IDLoc, "dividing zero by zero");
       else
         Warning(IDLoc, "division by zero");
     }

 unsigned
 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
                                               const OperandVector &Operands) {
   switch (Inst.getOpcode()) {
   default:
     return Match_Success;
   case Mips::DATI:
   case Mips::DAHI:
-  case Mips::DATI_MM64R6:
-  case Mips::DAHI_MM64R6:
     if (static_cast<MipsOperand &>(*Operands[1])
             .isValidForTie(static_cast<MipsOperand &>(*Operands[2])))
       return Match_Success;
     return Match_RequiresSameSrcAndDst;
   }
 }
 
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   switch (Inst.getOpcode()) {
   // As described by the MIPSR6 spec, daui must not use the zero operand for
   // its source operand.
   case Mips::DAUI:
-  case Mips::DAUI_MM64R6:
     if (Inst.getOperand(1).getReg() == Mips::ZERO ||
         Inst.getOperand(1).getReg() == Mips::ZERO_64)
       return Match_RequiresNoZeroRegister;
     return Match_Success;
   // As described by the Mips32r2 spec, the registers Rd and Rs for
   // jalr.hb must be different.
   // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
   // and registers Rd and Base for microMIPS lwp instruction
if (Inst.getOperand(0).getReg() == Mips::ZERO ||
         Inst.getOperand(0).getReg() == Mips::ZERO_64)
       return Match_RequiresNoZeroRegister;
     if (Inst.getOperand(1).getReg() == Mips::ZERO ||
         Inst.getOperand(1).getReg() == Mips::ZERO_64)
       return Match_RequiresNoZeroRegister;
     if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
       return Match_RequiresDifferentOperands;
     return Match_Success;
-  case Mips::DINS:
-  case Mips::DINS_MM64R6: {
+  case Mips::DINS: {
     assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
            "Operands must be immediates for dins!");
     const signed Pos = Inst.getOperand(2).getImm();
     const signed Size = Inst.getOperand(3).getImm();
     if ((0 > (Pos + Size)) || ((Pos + Size) > 32))
       return Match_RequiresPosSizeRange0_32;
     return Match_Success;
   }
   case Mips::DINSM:
-  case Mips::DINSM_MM64R6:
-  case Mips::DINSU:
-  case Mips::DINSU_MM64R6: {
+  case Mips::DINSU: {
     assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
            "Operands must be immediates for dinsm/dinsu!");
     const signed Pos = Inst.getOperand(2).getImm();
     const signed Size = Inst.getOperand(3).getImm();
     if ((32 >= (Pos + Size)) || ((Pos + Size) > 64))
       return Match_RequiresPosSizeRange33_64;
     return Match_Success;
   }
-  case Mips::DEXT:
-  case Mips::DEXT_MM64R6: {
+  case Mips::DEXT: {
     assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
            "Operands must be immediates for DEXTM!");
     const signed Pos = Inst.getOperand(2).getImm();
     const signed Size = Inst.getOperand(3).getImm();
     if ((1 > (Pos + Size)) || ((Pos + Size) > 63))
       return Match_RequiresPosSizeUImm6;
     return Match_Success;
   }
   case Mips::DEXTM:
-  case Mips::DEXTU:
-  case Mips::DEXTM_MM64R6:
-  case Mips::DEXTU_MM64R6: {
+  case Mips::DEXTU: {
     assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
            "Operands must be immediates for dextm/dextu!");
     const signed Pos = Inst.getOperand(2).getImm();
     const signed Size = Inst.getOperand(3).getImm();
     if ((32 > (Pos + Size)) || ((Pos + Size) > 64))
       return Match_RequiresPosSizeRange33_64;
     return Match_Success;
   }
StringRef ArchFeatureName =
           .Case("mips64r6", "mips64r6")
           .Case("octeon", "cnmips")
           .Case("r4000", "mips3") // This is an implementation of Mips3.
           .Default("");
 
   if (ArchFeatureName.empty())
     return reportParseError("unsupported architecture");
 
+  if (ArchFeatureName == "mips64r6" && inMicroMipsMode())
+    return reportParseError("mips64r6 does not support microMIPS");
+
   selectArch(ArchFeatureName);
   getTargetStreamer().emitDirectiveSetArch(Arch);
   return false;
 }
 
 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
   MCAsmParser &Parser = getParser();
   Parser.Lex();
bool MipsAsmParser::parseDirectiveSet() {
   } else if (Tok.getString() == "nomips16") {
     return parseSetNoMips16Directive();
   } else if (Tok.getString() == "nomicromips") {
     clearFeatureBits(Mips::FeatureMicroMips, "micromips");
     getTargetStreamer().emitDirectiveSetNoMicroMips();
     Parser.eatToEndOfStatement();
     return false;
   } else if (Tok.getString() == "micromips") {
+    if (hasMips64r6()) {
+      Error(Tok.getLoc(), ".set micromips directive is not supported with MIPS64R6");
+      return false;
+    }
     return parseSetFeature(Mips::FeatureMicroMips);
   } else if (Tok.getString() == "mips0") {
     return parseSetMips0Directive();
   } else if (Tok.getString() == "mips1") {
     return parseSetFeature(Mips::FeatureMips1);
   } else if (Tok.getString() == "mips2") {
     return parseSetFeature(Mips::FeatureMips2);
   } else if (Tok.getString() == "mips3") {
if (Tok.getString() == "noat") {
     return parseSetFeature(Mips::FeatureMips64);
   } else if (Tok.getString() == "mips64r2") {
     return parseSetFeature(Mips::FeatureMips64r2);
   } else if (Tok.getString() == "mips64r3") {
     return parseSetFeature(Mips::FeatureMips64r3);
   } else if (Tok.getString() == "mips64r5") {
     return parseSetFeature(Mips::FeatureMips64r5);
   } else if (Tok.getString() == "mips64r6") {
+    if (inMicroMipsMode()) {
+      Error(Tok.getLoc(), "MIPS64R6 is not supported with microMIPS");
+      return false;
+    }
     return parseSetFeature(Mips::FeatureMips64r6);
   } else if (Tok.getString() == "dsp") {
     return parseSetFeature(Mips::FeatureDSP);
   } else if (Tok.getString() == "dspr2") {
     return parseSetFeature(Mips::FeatureDSPR2);
   } else if (Tok.getString() == "nodsp") {
     return parseSetNoDspDirective();
   } else if (Tok.getString() == "msa") {
     return parseSetMsaDirective();

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 // Override the generated disassembler to produce DEXT all the time. This is
 // for feature / behaviour parity with  binutils.
 template <typename InsnType>
 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
                                const void *Decoder) {
   unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
   unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
   unsigned Size = 0;
   unsigned Pos = 0;
-  bool IsMicroMips = false;
 
   switch (MI.getOpcode()) {
-    case Mips::DEXT_MM64R6:
-      IsMicroMips = true;
-      LLVM_FALLTHROUGH;
     case Mips::DEXT:
       Pos = Lsb;
       Size = Msbd + 1;
       break;
-    case Mips::DEXTM_MM64R6:
-      IsMicroMips = true;
-      LLVM_FALLTHROUGH;
     case Mips::DEXTM:
       Pos = Lsb;
       Size = Msbd + 1 + 32;
       break;
-    case Mips::DEXTU_MM64R6:
-      IsMicroMips = true;
-      LLVM_FALLTHROUGH;
     case Mips::DEXTU:
       Pos = Lsb + 32;
       Size = Msbd + 1;
       break;
     default:
       llvm_unreachable("Unknown DEXT instruction!");
   }
 
-  MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT);
+  MI.setOpcode(Mips::DEXT);
 
-  // Although the format of the instruction is similar, rs and rt are swapped
-  // for microMIPS64R6.
   InsnType Rs = fieldFromInstruction(Insn, 21, 5);
   InsnType Rt = fieldFromInstruction(Insn, 16, 5);
-  if (IsMicroMips)
-    std::swap(Rs, Rt);
 
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
   MI.addOperand(MCOperand::createImm(Pos));
   MI.addOperand(MCOperand::createImm(Size));
 
   return MCDisassembler::Success;
 }
 
 // Override the generated disassembler to produce DINS all the time. This is
 // for feature / behaviour parity with binutils.
 template <typename InsnType>
 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
                                const void *Decoder) {
   unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
   unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
   unsigned Size = 0;
   unsigned Pos = 0;
-  bool IsMicroMips = false;
 
   switch (MI.getOpcode()) {
-    case Mips::DINS_MM64R6:
-      IsMicroMips = true;
-      LLVM_FALLTHROUGH;
     case Mips::DINS:
       Pos = Lsb;
       Size = Msbd + 1 - Pos;
       break;
-    case Mips::DINSM_MM64R6:
-      IsMicroMips = true;
-      LLVM_FALLTHROUGH;
     case Mips::DINSM:
       Pos = Lsb;
       Size = Msbd + 33 - Pos;
       break;
-    case Mips::DINSU_MM64R6:
-      IsMicroMips = true;
-      LLVM_FALLTHROUGH;
     case Mips::DINSU:
       Pos = Lsb + 32;
       // mbsd = pos + size - 33
       // mbsd - pos + 33 = size
       Size = Msbd + 33 - Pos;
       break;
     default:
       llvm_unreachable("Unknown DINS instruction!");
   }
 
-  // Although the format of the instruction is similar, rs and rt are swapped
-  // for microMIPS64R6.
   InsnType Rs = fieldFromInstruction(Insn, 21, 5);
   InsnType Rt = fieldFromInstruction(Insn, 16, 5);
-  if (IsMicroMips)
-    std::swap(Rs, Rt);
 
-  MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS);
+  MI.setOpcode(Mips::DINS);
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
   MI.addOperand(MCOperand::createImm(Pos));
   MI.addOperand(MCOperand::createImm(Size));
 
   return MCDisassembler::Success;
 }
 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   if (IsMicroMips) {
     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
 
     if (hasMips32r6()) {
       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
       // Calling the auto-generated decoder function for microMIPS32R6
-      // (and microMIPS64R6) 16-bit instructions.
+      // 16-bit instructions.
       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
                                  Address, this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 2;
         return Result;
       }
     }
 

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

case Mips::DSRL:
     Inst.setOpcode(Mips::DSRL32);
     return;
   case Mips::DSRA:
     Inst.setOpcode(Mips::DSRA32);
     return;
   case Mips::DROTR:
     Inst.setOpcode(Mips::DROTR32);
     return;
-  case Mips::DSLL_MM64R6:
-    Inst.setOpcode(Mips::DSLL32_MM64R6);
-    return;
-  case Mips::DSRL_MM64R6:
-    Inst.setOpcode(Mips::DSRL32_MM64R6);
-    return;
-  case Mips::DSRA_MM64R6:
-    Inst.setOpcode(Mips::DSRA32_MM64R6);
-    return;
-  case Mips::DROTR_MM64R6:
-    Inst.setOpcode(Mips::DROTR32_MM64R6);
-    return;
   }
 }
 
 // Fix a bad compact branch encoding for beqc/bnec.
 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
   // Encoding may be illegal !(rs < rt), but this situation is
   // easily fixed.
   unsigned RegOp0 = Inst.getOperand(0).getReg();
encodeInstruction(const MCInst &MI, raw_ostream &OS,
   // the check to a function call. Until then, this is more efficient.
   MCInst TmpInst = MI;
   switch (MI.getOpcode()) {
   // If shift amount is >= 32 it the inst needs to be lowered further
   case Mips::DSLL:
   case Mips::DSRL:
   case Mips::DSRA:
   case Mips::DROTR:
-  case Mips::DSLL_MM64R6:
-  case Mips::DSRL_MM64R6:
-  case Mips::DSRA_MM64R6:
-  case Mips::DROTR_MM64R6:
     LowerLargeShift(TmpInst);
     break;
   // Compact branches, enforce encoding restrictions.
   case Mips::BEQC:
   case Mips::BNEC:
   case Mips::BEQC64:
   case Mips::BNEC64:
   case Mips::BOVC:

lib/Target/Mips/MicroMips32r6InstrFormats.td

 //===----------------------------------------------------------------------===//
 
 class MMR6Arch<string opstr> {
   string Arch = "micromipsr6";
   string BaseOpcode = opstr;
   string DecoderNamespace = "MicroMipsR6";
 }
 
-// Class used for microMIPS32r6 and microMIPS64r6 instructions.
+// Class used for microMIPS32r6 instructions.
 class MicroMipsR6Inst16 : PredicateControl {
   string DecoderNamespace = "MicroMipsR6";
   let InsnPredicates = [HasMicroMips32r6];
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Disambiguators

lib/Target/Mips/MicroMipsInstrInfo.td

class UncondBranchMM16<string opstr> :
   let isTerminator = 1;
   let isBarrier = 1;
   let hasDelaySlot = 1;
   let Predicates = [RelocPIC, InMicroMips];
   let Defs = [AT];
 }
 
 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
-    ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
+    ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
-    LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
+    LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
-    SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
+    SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
-    SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
+    SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
 
 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
-                ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
+                ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-               LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
+               LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
                         mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
                         mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
                       LOAD_STORE_FM_MM16<0x1a>;
 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
                         II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;

 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
-               ISA_MICROMIPS_NOT_32R6_64R6;
+               ISA_MICROMIPS_NOT_32R6;
 def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
               IsAsCheapAsAMove;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
                 ISA_MICROMIPS32_NOT_MIPS32R6;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
                 BEQNEZ_FM_MM16<0x23>;
 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
                 BEQNEZ_FM_MM16<0x2b>;
 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
 def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 
 let DecoderNamespace = "MicroMips" in {
   /// Load and Store Instructions - multiple
   def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
                  ISA_MICROMIPS32_NOT_MIPS32R6;
   def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
                  ISA_MICROMIPS32_NOT_MIPS32R6;
   let AdditionalPredicates = [InMicroMips] in {

lib/Target/Mips/MicroMipsSizeReduction.cpp

bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
   }
   return false;
 }
 
 bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
 
   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
 
-  // TODO: Add support for other subtargets:
-  // microMIPS32r6 and microMIPS64r6
+  // TODO: Add support for the subtarget microMIPS32R6.
   if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
       Subtarget->hasMips32r6())
     return false;
 
   MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
 
   bool Modified = false;
   MachineFunction::iterator I = MF.begin(), E = MF.end();

lib/Target/Mips/Mips64InstrInfo.td

 //===----------------------------------------------------------------------===//
 // Instruction definition
 //===----------------------------------------------------------------------===//
 let DecoderNamespace = "Mips64" in {
 /// Arithmetic Instructions (ALU Immediate)
 def DADDi   : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>,
               ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
-                                       II_DADDIU, immSExt16, add>,
+  def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
+                           immSExt16, add>,
                ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
 }
 
 let isCodeGenOnly = 1 in {
 def SLTi64  : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
               SLTI_FM<0xa>;
 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
               SLTI_FM<0xb>;
 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
              ADDI_FM<0xc>;
 def ORi64   : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
               ADDI_FM<0xd>;
 def XORi64  : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
               ADDI_FM<0xe>;
 def LUi64   : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM;
 }
 
 /// Arithmetic Instructions (3-Operand, R-Type)
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DADD   : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>,
-               ADD_FM<0, 0x2c>, ISA_MIPS3;
-  def DADDu  : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
-               ADD_FM<0, 0x2d>, ISA_MIPS3;
-  def DSUBu  : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
+  def DADD   : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
                ISA_MIPS3;
-  def DSUB   : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
+  def DADDu  : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
+               ADD_FM<0, 0x2d>, ISA_MIPS3;
+  def DSUBu  : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
+               ADD_FM<0, 0x2f>, ISA_MIPS3;
+  def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
                ISA_MIPS3;
 }
 
 let isCodeGenOnly = 1 in {
 def SLT64  : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
 def AND64  : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
 def OR64   : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
 def XOR64  : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
 }
 
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
-                                          shl, immZExt6>,
+  def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl,
+                              immZExt6>,
              SRA_FM<0x38, 0>, ISA_MIPS3;
-  def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
-                                          srl, immZExt6>,
+  def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl,
+                              immZExt6>,
              SRA_FM<0x3a, 0>, ISA_MIPS3;
-  def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
-                                          sra, immZExt6>,
+  def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra,
+                              immZExt6>,
              SRA_FM<0x3b, 0>, ISA_MIPS3;
-  def DSLLV  : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
+  def DSLLV  : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
                SRLV_FM<0x14, 0>, ISA_MIPS3;
-  def DSRAV  : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
+  def DSRAV  : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
                SRLV_FM<0x17, 0>, ISA_MIPS3;
-  def DSRLV  : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
+  def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
                SRLV_FM<0x16, 0>, ISA_MIPS3;
-  def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
-                                            II_DSLL32>,
+  def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
                SRA_FM<0x3c, 0>, ISA_MIPS3;
-  def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd,
-                                            II_DSRL32>,
+  def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
                SRA_FM<0x3e, 0>, ISA_MIPS3;
-  def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
-               II_DSRA32>,
+  def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
                SRA_FM<0x3f, 0>, ISA_MIPS3;
 
 // Rotate Instructions
-  def DROTR  : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR,
-                                            rotr, immZExt6>,
+  def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
+                                immZExt6>,
                SRA_FM<0x3a, 1>, ISA_MIPS64R2;
-  def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV,
-                                            rotr>,
+  def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
                SRLV_FM<0x16, 1>, ISA_MIPS64R2;
-  def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd,
-                                             II_DROTR32>,
+  def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
                 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
 }
 
 /// Load and Store Instructions
 ///  aligned
 let isCodeGenOnly = 1 in {
 def LB64  : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
 def LH64  : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
 def LW64  : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
 def SB64  : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
 def SH64  : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
 def SW64  : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
-  def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
+  def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
             LW_FM<0x27>, ISA_MIPS3;
-  def LD  : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
+  def LD  : LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
             LW_FM<0x37>, ISA_MIPS3;
-  def SD  : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
+  def SD  : StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
             LW_FM<0x3f>, ISA_MIPS3;
 }
 
 
 
 /// load/store left/right
 let isCodeGenOnly = 1 in {
 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
 }
 
 def LDL   : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
             ISA_MIPS3_NOT_32R6_64R6;
 def LDR   : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
             ISA_MIPS3_NOT_32R6_64R6;
 def SDL   : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
             ISA_MIPS3_NOT_32R6_64R6;
 def SDR   : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
             ISA_MIPS3_NOT_32R6_64R6;
 
 /// Load-linked, Store-conditional
 let AdditionalPredicates = [NotInMicroMips] in {
-  def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
+  def LLD : LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
             ISA_MIPS3_NOT_32R6_64R6;
 }
 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
 
 let AdditionalPredicates = [NotInMicroMips],
     DecoderNamespace = "Mips32_64_PTR64" in {
 def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64,
            ISA_MIPS2_NOT_32R6_64R6;

 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
             ISA_MIPS32R2;
 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
             ISA_MIPS32R2;
 }
 
 /// Count Leading
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>,
-             CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
-  def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>,
-             CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
+  def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
+             ISA_MIPS64_NOT_64R6;
+  def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>,
+             ISA_MIPS64_NOT_64R6;
 
 /// Double Word Swap Bytes/HalfWords
   def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>,
              ISA_MIPS64R2;
   def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>,
              ISA_MIPS64R2;
 }
 

 
 // hi/lo relocs
 let AdditionalPredicates = [NotInMicroMips] in
 defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, SYM_32;
 
 def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
 def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>;
 
-multiclass MipsHighestHigherHiLoRelocs<Instruction Lui, Instruction Daddiu> {
+// highest/higher/hi/lo relocs
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)),
-                (JAL texternalsym:$dst)>;
+                (JAL texternalsym:$dst)>, SYM_64;
   def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)),
-                (Lui tglobaladdr:$in)>;
+                (LUi64 tglobaladdr:$in)>, SYM_64;
   def : MipsPat<(MipsHighest (i64 tblockaddress:$in)),
-                (Lui tblockaddress:$in)>;
+                (LUi64 tblockaddress:$in)>, SYM_64;
   def : MipsPat<(MipsHighest (i64 tjumptable:$in)),
-                (Lui tjumptable:$in)>;
+                (LUi64 tjumptable:$in)>, SYM_64;
   def : MipsPat<(MipsHighest (i64 tconstpool:$in)),
-                (Lui tconstpool:$in)>;
+                (LUi64 tconstpool:$in)>, SYM_64;
   def : MipsPat<(MipsHighest (i64 tglobaltlsaddr:$in)),
-                (Lui tglobaltlsaddr:$in)>;
+                (LUi64 tglobaltlsaddr:$in)>, SYM_64;
   def : MipsPat<(MipsHighest (i64 texternalsym:$in)),
-                (Lui texternalsym:$in)>;
+                (LUi64 texternalsym:$in)>, SYM_64;
 
   def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
-                (Daddiu ZERO_64, tglobaladdr:$in)>;
+                (DADDiu ZERO_64, tglobaladdr:$in)>, SYM_64;
   def : MipsPat<(MipsHigher (i64 tblockaddress:$in)),
-                (Daddiu ZERO_64, tblockaddress:$in)>;
+                (DADDiu ZERO_64, tblockaddress:$in)>, SYM_64;
   def : MipsPat<(MipsHigher (i64 tjumptable:$in)),
-                (Daddiu ZERO_64, tjumptable:$in)>;
+                (DADDiu ZERO_64, tjumptable:$in)>, SYM_64;
   def : MipsPat<(MipsHigher (i64 tconstpool:$in)),
-                (Daddiu ZERO_64, tconstpool:$in)>;
+                (DADDiu ZERO_64, tconstpool:$in)>, SYM_64;
   def : MipsPat<(MipsHigher (i64 tglobaltlsaddr:$in)),
-                (Daddiu ZERO_64, tglobaltlsaddr:$in)>;
+                (DADDiu ZERO_64, tglobaltlsaddr:$in)>, SYM_64;
   def : MipsPat<(MipsHigher (i64 texternalsym:$in)),
-                (Daddiu ZERO_64, texternalsym:$in)>;
+                (DADDiu ZERO_64, texternalsym:$in)>, SYM_64;
 
   def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
-                (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+                (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))),
-                (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+                (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))),
-                (Daddiu GPR64:$hi, tjumptable:$lo)>;
+                (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))),
-                (Daddiu GPR64:$hi, tconstpool:$lo)>;
+                (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaltlsaddr:$lo))),
-                (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+                (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64;
 
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
-                (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+                (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))),
-                (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+                (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))),
-                (Daddiu GPR64:$hi, tjumptable:$lo)>;
+                (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))),
-                (Daddiu GPR64:$hi, tconstpool:$lo)>;
+                (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaltlsaddr:$lo))),
-                (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+                (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64;
 
   def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
-                (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+                (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))),
-                (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+                (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))),
-                (Daddiu GPR64:$hi, tjumptable:$lo)>;
+                (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))),
-                (Daddiu GPR64:$hi, tconstpool:$lo)>;
+                (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))),
-                (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
-
+                (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64;
 }
 
-// highest/higher/hi/lo relocs
-let AdditionalPredicates = [NotInMicroMips] in
-defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
-
 // gp_rel relocs
 def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)),
               (DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64;
 def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)),
               (DADDiu GPR64:$gp, tconstpool:$in)>, ABI_N64;
 
 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
 def : WrapperPat<tconstpool, DADDiu, GPR64>;

lib/Target/Mips/Mips64r6InstrInfo.td

 
 let AdditionalPredicates = [NotInMicroMips] in {
   let DecoderMethod = "DecodeDAHIDATI" in {
     def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
     def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
   }
   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
   def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
-  def DBITSWAP : R6MMR6Rel, DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
-  def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
-  def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
+  def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
+  def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
+  def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
   def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
   def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
   def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
-  def DLSA_R6 : R6MMR6Rel, DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
+  def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
   def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
   def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
   def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
   def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
-  def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
+  def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
 }
-def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
+def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
 }
 let AdditionalPredicates = [NotInMicroMips],
     DecoderNamespace = "Mips32r6_64r6_PTR64" in {
   def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;

lib/Target/Mips/MipsISelLowering.cpp

case Mips::MODU_MMR6:
     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
   case Mips::PseudoDSDIV:
   case Mips::PseudoDUDIV:
   case Mips::DDIV:
   case Mips::DDIVU:
   case Mips::DMOD:
   case Mips::DMODU:
     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
-  case Mips::DDIV_MM64R6:
-  case Mips::DDIVU_MM64R6:
-  case Mips::DMOD_MM64R6:
-  case Mips::DMODU_MM64R6:
-    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
 
   case Mips::PseudoSELECT_I:
   case Mips::PseudoSELECT_I64:
   case Mips::PseudoSELECT_S:
   case Mips::PseudoSELECT_D32:
   case Mips::PseudoSELECT_D64:
     return emitPseudoSELECT(MI, BB, false, Mips::BNE);
   case Mips::PseudoSELECTFP_F_I:

lib/Target/Mips/MipsInstrInfo.cpp

bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
                                       StringRef &ErrInfo) const {
   // Verify that ins and ext instructions are well formed.
   switch (MI.getOpcode()) {
     case Mips::EXT:
     case Mips::EXT_MM:
     case Mips::INS:
     case Mips::INS_MM:
     case Mips::DINS:
-    case Mips::DINS_MM64R6:
       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
     case Mips::DINSM:
-    case Mips::DINSM_MM64R6:
       // The ISA spec has a subtle difference here in that it says:
       //  2 <= size <= 64 for 'dinsm', so we change the bounds so that it
       // is in line with the rest of instructions.
       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
     case Mips::DINSU:
-    case Mips::DINSU_MM64R6:
       // The ISA spec has a subtle difference here in that it says:
       //  2 <= size <= 64 for 'dinsm', so we change the bounds so that it
       // is in line with the rest of instructions.
       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 1, 32, 32, 64);
     case Mips::DEXT:
-    case Mips::DEXT_MM64R6:
       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
     case Mips::DEXTM:
-    case Mips::DEXTM_MM64R6:
       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
     case Mips::DEXTU:
-    case Mips::DEXTU_MM64R6:
       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
     default:
       return true;
   }
 
   return true;
 }
 

lib/Target/Mips/MipsInstrInfo.td

 def HasMips64r2  :    Predicate<"Subtarget->hasMips64r2()">,
                       AssemblerPredicate<"FeatureMips64r2">;
 def HasMips64r6  :    Predicate<"Subtarget->hasMips64r6()">,
                       AssemblerPredicate<"FeatureMips64r6">;
 def NotMips64r6  :    Predicate<"!Subtarget->hasMips64r6()">,
                       AssemblerPredicate<"!FeatureMips64r6">;
 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
-def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
-                       AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"FeatureMips16">;
 def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"!FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
                       AssemblerPredicate<"FeatureCnMips">;
 def NotCnMips    :    Predicate<"!Subtarget->hasCnMips()">,
                       AssemblerPredicate<"!FeatureCnMips">;

 }
 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
 class ISA_MICROMIPS32R6 {
   list<Predicate> InsnPredicates = [HasMicroMips32r6];
 }
-class ISA_MICROMIPS64R6 {
-  list<Predicate> InsnPredicates = [HasMicroMips64r6];
-}
 class ISA_MICROMIPS32_NOT_MIPS32R6 {
   list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
 }
 
 class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
 class INSN_EVA_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
 }

 }
 
 class ASE_MT {
   list <Predicate> InsnPredicates = [HasMT];
 }
 
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
-class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
-  let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
+class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
+  let InsnPredicates = [InMicroMips, NotMips32r6];
 }
 
 class ASE_NOT_DSP {
   list<Predicate> InsnPredicates = [NotDSP];
 }
 
 class MADD4 {
   list<Predicate> AdditionalPredicates = [HasMadd4];

 include "MicroMipsInstrFormats.td"
 include "MicroMipsInstrInfo.td"
 include "MicroMipsInstrFPU.td"
 
 // Micromips r6
 include "MicroMips32r6InstrFormats.td"
 include "MicroMips32r6InstrInfo.td"
 
-// Micromips64 r6
-include "MicroMips64r6InstrFormats.td"
-include "MicroMips64r6InstrInfo.td"
-
 // Micromips DSP
 include "MicroMipsDSPInstrFormats.td"
 include "MicroMipsDSPInstrInfo.td"

lib/Target/Mips/MipsMachineFunction.cpp

unsigned MipsFunctionInfo::getGlobalBaseReg() {
 
   MipsSubtarget const &STI =
       static_cast<const MipsSubtarget &>(MF.getSubtarget());
 
   const TargetRegisterClass *RC =
       STI.inMips16Mode()
           ? &Mips::CPU16RegsRegClass
           : STI.inMicroMipsMode()
-                ? STI.hasMips64()
-                      ? &Mips::GPRMM16_64RegClass
-                      : &Mips::GPRMM16RegClass
+                ? &Mips::GPRMM16RegClass
                 : static_cast<const MipsTargetMachine &>(MF.getTarget())
                           .getABI()
                           .IsN64()
                       ? &Mips::GPR64RegClass
                       : &Mips::GPR32RegClass;
   return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
 }
 

lib/Target/Mips/MipsRegisterInfo.cpp

MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                      unsigned Kind) const {
   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
   MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
 
   switch (PtrClassKind) {
   case MipsPtrClass::Default:
     return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
   case MipsPtrClass::GPR16MM:
-    return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass
-                              : &Mips::GPRMM16RegClass;
+    return &Mips::GPRMM16RegClass;
   case MipsPtrClass::StackPointer:
     return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
   case MipsPtrClass::GlobalPointer:
     return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
   }
 
   llvm_unreachable("Unknown pointer kind");
 }

lib/Target/Mips/MipsRegisterInfo.td

def GPR64 : RegisterClass<"Mips", [i64], 64, (add
   T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
   // Callee save
   S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
   // Not preserved across procedure calls
   T8_64, T9_64,
   // Reserved
   K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
 
-def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add
-  // Callee save
-  S0_64, S1_64,
-  // Return Values and Arguments
-  V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>;
-
 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
   // Return Values and Arguments
   V0, V1, A0, A1, A2, A3,
   // Callee save
   S0, S1)>;
 
 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
   // Return Values and Arguments

lib/Target/Mips/MipsScheduleP5600.td

def MipsP5600Model : SchedMachineModel {
   int LoadLatency = 4;
   int MispredictPenalty = 8; // TODO: Estimated
 
   let CompleteModel = 1;
 
   list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
                                          HasMips64, HasMips64r2, HasCnMips,
                                          InMicroMips, InMips16Mode,
-                                         HasMicroMips32r6, HasMicroMips64r6,
-                                         HasDSP, HasDSPR2, HasMT];
+                                         HasMicroMips32r6, HasDSP,
+                                         HasDSPR2, HasMT];
 
 }
 
 let SchedModel = MipsP5600Model in {
 
 // ALQ Pipelines
 // =============
 

lib/Target/Mips/MipsSubtarget.h

public:
   // but to use a runtime library for soft float that is written with
   // native mips32 floating point instructions (those runtime routines
   // run in mips32 hard float mode).
   bool inMips16HardFloat() const {
     return inMips16Mode() && InMips16HardFloat;
   }
   bool inMicroMipsMode() const { return InMicroMipsMode; }
   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
-  bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
   bool hasDSP() const { return HasDSP; }
   bool hasDSPR2() const { return HasDSPR2; }
   bool hasDSPR3() const { return HasDSPR3; }
   bool hasMSA() const { return HasMSA; }
   bool disableMadd4() const { return DisableMadd4; }
   bool hasEVA() const { return HasEVA; }
   bool hasMT() const { return HasMT; }
   bool useSmallSection() const { return UseSmallSection; }

lib/Target/Mips/MipsSubtarget.cpp

report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
                        false);
 
   if (!isABI_O32() && !useOddSPReg())
     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
 
   if (IsFPXX && (isABI_N32() || isABI_N64()))
     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
 
+  if (hasMips64r6() && InMicroMipsMode)
+    report_fatal_error("microMIPS64R6 is not supported", false);
+
   if (hasMips32r6()) {
     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
 
     assert(isFP64bit());
     assert(isNaN2008());
     if (hasDSP())
       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
   }

lib/Target/Mips/Relocation.txt

to MIPS32 to compute addresses for the static relocation model.
   }
   defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
 
   // lib/Target/Mips/Mips64InstrInfo.td
   defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, SYM_32;
 
 The instantiation in Mips64InstrInfo.td is used for MIPS64 in ILP32
 mode, as guarded by the predicate "SYM_32" and also for a submode of
-LP64 where symbols are assumed to be 32 bits wide. A similar
-multiclass for MIPS64 in LP64 mode is also defined:
-
-  // lib/Target/Mips/Mips64InstrInfo.td
-  multiclass MipsHighestHigherHiLoRelocs<Instruction Lui,
-                                         Instruction Daddiu> {
-  ...
-    def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)),
-                  (Lui tglobaladdr:$in)>;
-  ...
-    def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
-                  (Daddiu ZERO_64, tglobaladdr:$in)>;
-  ...
-    def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
-                  (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
-  ...
-    def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
-                  (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
-  ...
-    def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
-                  (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
-  }
-
-and it is instantiated twice:
-
-  // lib/Target/Mips/Mips64InstrInfo.td
-  defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
-  // lib/Target/Mips/MicroMips64r6InstrInfo.td
-  defm : MipsHighestHigherHiLoRelocs<LUi64, DADDIU_MM64R6>, SYM_64,
-                                     ISA_MICROMIPS64R6;
-
-These patterns are used during instruction selection to match
-MipsISD::{Highest, Higher, Hi, Lo} to a specific machine instruction
-and operands.
+LP64 where symbols are assumed to be 32 bits wide.
 
 More details on how multiclasses in TableGen work can be found in the
 section "Multiclass definitions and instances" in the document
 "TableGen Language Introduction"
 
 4. Instruction definitions are multiply defined to cover the different
 register classes. In some cases, such as LW/LW64, this also accounts
 for the difference in the results of instruction execution. On MIPS32,

test/CodeGen/Mips/countleading.ll

 ; RUN: llc -march=mipsel -mcpu=mips32   < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s
 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s
 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=ALL,MIPS32-R6,MIPS32-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips4    < %s | FileCheck -check-prefixes=ALL,MIPS4 %s
 ; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s
 
 ; Prefixes:
 ;   ALL      - All
 ;   MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
 ;   MIPS64-GT-R1 - MIPS64r1 and above
 
 define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
 entry:
 ; ALL-LABEL: ctlz_i32:
 
 ; MIPS4-NOT:     clz
 
 ; MIPS32-GT-R1:  clz $2, $4
 
 ; MIPS64-GT-R1:  clz $2, $4
 
-; MICROMIPS64:   clz $2, $4
-
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
   ret i32 %tmp1
 }
 
 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
 
 define i32 @ctlo_i32(i32 signext %X) nounwind readnone {
 entry:
 ; ALL-LABEL: ctlo_i32:
 
 ; MIPS4-NOT:     clo
 
 ; MIPS32-GT-R1:  clo $2, $4
 
 ; MIPS64-GT-R1:  clo $2, $4
 
-; MICROMIPS64:   clo $2, $4
-
   %neg = xor i32 %X, -1
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
   ret i32 %tmp1
 }
 
 define i64 @ctlz_i64(i64 %X) nounwind readnone {
 entry:
 ; ALL-LABEL: ctlz_i64:
 
 ; MIPS4-NOT:     dclz
 
 ; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
 ; MIPS32-R6-DAG:    seleqz $[[R5:[0-9]+]], $[[R2]], $5
 ; MIPS32-R6-DAG:    selnez $[[R6:[0-9]+]], $[[R1]], $5
 ; MIPS32-R6-DAG:    or $2, $[[R6]], $[[R5]]
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclz $2, $4
-; MICROMIPS64:   dclz $2, $4
 
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
   ret i64 %tmp1
 }
 
 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 
 define i64 @ctlo_i64(i64 %X) nounwind readnone {

 ; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]]
 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]]
 ; MIPS32-R6-DAG:    selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
 ; MIPS32-R6-DAG:    seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
 ; MIPS32-R6-DAG:    or $2, $[[R5]], $[[R6]]
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclo $2, $4
-; MICROMIPS64:   dclo $2, $4
 
   %neg = xor i64 %X, -1
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
   ret i64 %tmp1
 }

test/CodeGen/Mips/fcmp.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \
 ; RUN:    FileCheck %s -check-prefixes=ALL,64-C
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
 ; RUN:    FileCheck %s -check-prefixes=ALL,64-CMP
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32R3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MMR6,MM32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MMR6,MM64R6
 
 define i32 @false_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: false_f32:
 ; 32-C:          addiu $2, $zero, 0
 
 ; 32-CMP:        addiu $2, $zero, 0
 
 ; 64-C:          addiu $2, $zero, 0

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.eq.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ule.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ult.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.olt.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ole.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ueq.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.un.s  $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ueq.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ole.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.olt.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ult.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ule.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.eq.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.un.s $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.eq.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp oeq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ule.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ogt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ult.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp oge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.olt.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp olt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ole.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ole double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ueq.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp one double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.un.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp ord double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ueq.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ueq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ole.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.olt.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ult.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ult double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ule.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp ule double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.eq.d  $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp une double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.un.d $f12, $f14
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
   %1 = fcmp uno double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; MM32R6-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
 ; MM32R6-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
 ; MM32R6-DAG:    cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
 ; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
 ; MM32R6-DAG:    bnezc    $[[T5]],
 
-; MM64R6-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
-; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI32_0)
-; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0)
-; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
-; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0)
-; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
-; MM64R6-DAG:    lwc1     $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]])
-; MM64R6-DAG:    cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
-; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
-; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG:    bnezc    $[[T9]],
-
   %add = fadd fast float %at, %angle
   %cmp = fcmp ogt float %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   %sub = fadd fast float %add, -1.000000e+00
   br label %if.end
 

 ; MM32R6-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
 ; MM32R6-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
 ; MM32R6-DAG:    cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
 ; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3]]
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
 ; MM32R6-DAG:    bnezc    $[[T5]],
 
-; MM64R6-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
-; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI33_0)
-; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0)
-; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
-; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0)
-; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
-; MM64R6-DAG:    ldc1     $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]])
-; MM64R6-DAG:    cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
-; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
-; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG:    bnezc    $[[T9]],
-
   %add = fadd fast double %at, %angle
   %cmp = fcmp ogt double %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   %sub = fadd fast double %add, -1.000000e+00
   br label %if.end
 
 if.end:
   %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
   ret double %theta.0
 }
 
 attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }

test/CodeGen/Mips/llvm-ir/add.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM64
 
 
 ; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. 
 ; This sequence is even better as it's a single instruction. See D25485 for the rest of 
 ; the cases where this sequence occurs.
 
 define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
 entry:
; ALL-LABEL: add_i64:
 
   ; GP64:       daddu   $2, $4, $5
 
   ; MM32-DAG:   addu16  $3, $5, $7
   ; MM32-DAG:   addu16  $[[T0:[0-9]+]], $4, $6
   ; MM32:       sltu    $[[T1:[0-9]+]], $3, $5
   ; MM32:       addu16  $2, $[[T0]], $[[T1]]
 
-  ; MM64:       daddu   $2, $4, $5
-
   %r = add i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @add_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: add_i128:
 
; ALL-LABEL: add_i128:
   ; MMR6:        lw        $[[T17:[0-9]+]], 28($sp)
   ; MMR6:        addu16    $[[T18:[0-9]+]], $[[T1]], $[[T17]]
   ; MMR6:        addu16    $[[T19:[0-9]+]], $[[T18]], $[[T15]]
   ; MMR6:        sltu      $[[T20:[0-9]+]], $[[T18]], $[[T1]]
   ; MMR6:        sltu      $[[T21:[0-9]+]], $[[T17]], $[[T18]]
   ; MMR6:        addu16    $2, $[[T16]], $[[T20]]
   ; MMR6:        addu16    $2, $[[T20]], $[[T21]]
 
-  ; MM64:       daddu     $[[T0:[0-9]+]], $4, $6
-  ; MM64:       daddu     $3, $5, $7
-  ; MM64:       sltu      $[[T1:[0-9]+]], $3, $5
-  ; MM64:       dsll      $[[T2:[0-9]+]], $[[T1]], 32
-  ; MM64:       dsrl      $[[T3:[0-9]+]], $[[T2]], 32
-  ; MM64:       daddu     $2, $[[T0]], $[[T3]]
-
   %r = add i128 %a, %b
   ret i128 %r
 }
 
 define signext i1 @add_i1_4(i1 signext %a) {
 ; ALL-LABEL: add_i1_4:
 
   ; ALL:        move      $2, $4
; ALL-LABEL: add_i8_4:
   ; NOT-R2-R6:  sra     $2, $[[T0]], 24
 
   ; R2-R6:      addiu   $[[T0:[0-9]+]], $4, 4
   ; R2-R6:      seb     $2, $[[T0]]
 
   ; MM32:       addiur2 $[[T0:[0-9]+]], $4, 4
   ; MM32:       seb     $2, $[[T0]]
 
-  ; MM64:       addiur2 $[[T0:[0-9]+]], $4, 4
-  ; MM64:       seb     $2, $[[T0]]
-
   %r = add i8 4, %a
   ret i8 %r
 }
 
 define signext i16 @add_i16_4(i16 signext %a) {
 ; ALL-LABEL: add_i16_4:
 
   ; NOT-R2-R6:  sll     $[[T0:[0-9]+]], $4, 16
   ; NOT-R2-R6:  lui     $[[T1:[0-9]+]], 4
   ; NOT-R2-R6:  addu    $[[T0]], $[[T0]], $[[T1]]
   ; NOT-R2-R6:  sra     $2, $[[T0]], 16
 
   ; R2-R6:      addiu   $[[T0:[0-9]+]], $4, 4
   ; R2-R6:      seh     $2, $[[T0]]
 
   ; MM32:       addiur2 $[[T0:[0-9]+]], $4, 4
   ; MM32:       seh     $2, $[[T0]]
 
-  ; MM64:       addiur2 $[[T0:[0-9]+]], $4, 4
-  ; MM64:       seh     $2, $[[T0]]
-
   %r = add i16 4, %a
   ret i16 %r
 }
 
 define signext i32 @add_i32_4(i32 signext %a) {
 ; ALL-LABEL: add_i32_4:
 
   ; GP32:       addiu   $2, $4, 4
 
   ; GP64:       addiu   $2, $4, 4
 
   ; MM32:       addiur2 $2, $4, 4
 
-  ; MM64:       addiur2 $2, $4, 4
-
   %r = add i32 4, %a
   ret i32 %r
 }
 
 define signext i64 @add_i64_4(i64 signext %a) {
 ; ALL-LABEL: add_i64_4:
 
   ; GP32:       addiu   $3, $5, 4
   ; GP32:       sltu    $[[T0:[0-9]+]], $3, $5
   ; GP32:       addu    $2, $4, $[[T0]]
 
   ; MM32:       addiur2 $[[T1:[0-9]+]], $5, 4
   ; MM32:       sltu    $[[T2:[0-9]+]], $[[T1]], $5
   ; MM32:       addu16  $2, $4, $[[T2]]
 
   ; GP64:       daddiu  $2, $4, 4
 
 
-  ; MM64:       daddiu  $2, $4, 4
-
   %r = add i64 4, %a
   ret i64 %r
 }
 
 define signext i128 @add_i128_4(i128 signext %a) {
 ; ALL-LABEL: add_i128_4:
 
   ; PRE4:       move   $[[T0:[0-9]+]], $5
; ALL-LABEL: add_i128_4:
   ; MMR6: seleqz  $[[T7:[0-9]+]], $[[T6]], $[[T3]]
   ; MMR6: or      $[[T8:[0-9]+]], $[[T4]], $[[T7]]
   ; MMR6: addu16  $[[T9:[0-9]+]], $5, $[[T8]]
   ; MMR6: sltu    $[[T10:[0-9]+]], $[[T9]], $5
   ; MMR6: addu16  $[[T11:[0-9]+]], $4, $[[T10]]
   ; MMR6: move    $4, $7
   ; MMR6: move    $5, $[[T1]]
 
-  ; MM64:       daddiu  $[[T0:[0-9]+]], $5, 4
-  ; MM64:       sltu    $[[T1:[0-9]+]], $[[T0]], $5
-  ; MM64:       dsll    $[[T2:[0-9]+]], $[[T1]], 32
-  ; MM64:       dsrl    $[[T3:[0-9]+]], $[[T2]], 32
-  ; MM64:       daddu   $2, $4, $[[T3]]
-
   %r = add i128 4, %a
   ret i128 %r
 }
 
 define signext i1 @add_i1_3(i1 signext %a) {
 ; ALL-LABEL: add_i1_3:
   ; GP32:        addiu  $[[T0:[0-9]+]], $4, 1
   ; GP32:        andi   $[[T0]], $[[T0]], 1
; ALL-LABEL: add_i64_3:
 
   ; GP64:       daddiu  $2, $4, 3
 
   ; MM32:       move    $[[T1:[0-9]+]], $5
   ; MM32:       addius5 $[[T1]], 3
   ; MM32:       sltu    $[[T2:[0-9]+]], $[[T1]], $5
   ; MM32:       addu16  $2, $4, $[[T2]]
 
-  ; MM64:       daddiu  $2, $4, 3
-
   %r = add i64 3, %a
   ret i64 %r
 }
 
 define signext i128 @add_i128_3(i128 signext %a) {
 ; ALL-LABEL: add_i128_3:
 
   ; PRE4:       move   $[[T0:[0-9]+]], $5
; ALL-LABEL: add_i128_3:
   ; MMR6: seleqz  $[[T7:[0-9]+]], $[[T6]], $[[T3]]
   ; MMR6: or      $[[T8:[0-9]+]], $[[T4]], $[[T7]]
   ; MMR6: addu16  $[[T9:[0-9]+]], $5, $[[T8]]
   ; MMR6: sltu    $[[T10:[0-9]+]], $[[T9]], $5
   ; MMR6: addu16  $[[T11:[0-9]+]], $4, $[[T10]]
   ; MMR6: move    $4, $[[T5]]
   ; MMR6: move    $5, $[[T1]]
 
-  ; MM64:       daddiu  $[[T0:[0-9]+]], $5, 3
-  ; MM64:       sltu    $[[T1:[0-9]+]], $[[T0]], $5
-  ; MM64:       dsll    $[[T2:[0-9]+]], $[[T1]], 32
-  ; MM64:       dsrl    $[[T3:[0-9]+]], $[[T2]], 32
-  ; MM64:       daddu   $2, $4, $[[T3]]
-
   %r = add i128 3, %a
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/and.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1:
 
   ; GP32:         and     $2, $4, $5
 
   ; GP64:         and     $1, $4, $5
 
   ; MM32:         and16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         and     $1, $4, $5
-
   %r = and i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: and_i8:
 
   ; GP32:         and     $2, $4, $5
 
   ; GP64:         and     $1, $4, $5
 
   ; MM32:         and16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         and     $1, $4, $5
-
   %r = and i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: and_i16:
 
   ; GP32:         and     $2, $4, $5
 
   ; GP64:         and     $1, $4, $5
 
   ; MM32:         and16   $[[T0:[0-9]+]], $5
   ; MM32          move    $2, $[[T0]]
 
-  ; MM64:         and     $1, $4, $5
-
   %r = and i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
   ; GP32:         and     $2, $4, $5
 
   ; GP64:         and     $[[T0:[0-9]+]], $4, $5
   ; GP64:         sll     $2, $[[T0]], 0
 
   ; MM32:         and16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         and     $[[T0:[0-9]+]], $4, $5
-  ; MM64:         sll     $2, $[[T0]], 0
-
   %r = and i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: and_i64:
 
   ; GP32:         and     $2, $4, $6
   ; GP32:         and     $3, $5, $7
 
   ; GP64:         and     $2, $4, $5
 
   ; MM32:         and16   $[[T0:[0-9]+]], $6
   ; MM32:         and16   $[[T1:[0-9]+]], $7
   ; MM32:         move    $2, $[[T0]]
   ; MM32:         move    $3, $[[T1]]
 
-  ; MM64:         and     $2, $4, $5
-
   %r = and i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128:
 
; ALL-LABEL: and_i128:
   ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
   ; MM32:         and16   $[[T1]], $4
   ; MM32:         and16   $[[T0]], $5
   ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
   ; MM32:         and16   $[[T2]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         and16   $[[T3]], $7
 
-  ; MM64:         and     $2, $4, $6
-  ; MM64:         and     $3, $5, $7
-
   %r = and i128 %a, %b
   ret i128 %r
 }
 
 define signext i1 @and_i1_4(i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1_4:
 
; ALL-LABEL: and_i64_4:
   ; GP32:         andi    $3, $5, 4
   ; GP32:         addiu   $2, $zero, 0
 
   ; GP64:         andi    $2, $4, 4
 
   ; MM32:         andi16  $3, $5, 4
   ; MM32:         li16     $2, 0
 
-  ; MM64:         andi    $2, $4, 4
-
   %r = and i64 4, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128_4(i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128_4:
 
   ; GP32:         andi    $5, $7, 4
   ; GP32:         addiu   $2, $zero, 0
   ; GP32:         addiu   $3, $zero, 0
   ; GP32:         addiu   $4, $zero, 0
 
   ; GP64:         andi    $3, $5, 4
   ; GP64:         daddiu  $2, $zero, 0
 
   ; MM32:         andi16  $5, $7, 4
   ; MM32:         li16    $2, 0
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 4
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 4, %b
   ret i128 %r
 }
 
 define signext i1 @and_i1_31(i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1_31:
 
; ALL-LABEL: and_i64_31:
   ; GP32:         andi    $3, $5, 31
   ; GP32:         addiu   $2, $zero, 0
 
   ; GP64:         andi    $2, $4, 31
 
   ; MM32:         andi16  $3, $5, 31
   ; MM32:         li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 31
-
   %r = and i64 31, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128_31(i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128_31:
 
   ; GP32:         andi    $5, $7, 31
   ; GP32:         addiu   $2, $zero, 0
   ; GP32:         addiu   $3, $zero, 0
   ; GP32:         addiu   $4, $zero, 0
 
   ; GP64:         andi    $3, $5, 31
   ; GP64:         daddiu  $2, $zero, 0
 
   ; MM32:         andi16  $5, $7, 31
   ; MM32:         li16    $2, 0
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 31
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 31, %b
   ret i128 %r
 }
 
 define signext i1 @and_i1_255(i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1_255:
 
; ALL-LABEL: and_i64_255:
   ; GP32:         andi    $3, $5, 255
   ; GP32:         addiu   $2, $zero, 0
 
   ; GP64:         andi    $2, $4, 255
 
   ; MM32:         andi16  $3, $5, 255
   ; MM32:         li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 255
-
   %r = and i64 255, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128_255(i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128_255:
 
   ; GP32:         andi    $5, $7, 255
   ; GP32:         addiu   $2, $zero, 0
   ; GP32:         addiu   $3, $zero, 0
   ; GP32:         addiu   $4, $zero, 0
 
   ; GP64:         andi    $3, $5, 255
   ; GP64:         daddiu  $2, $zero, 0
 
   ; MM32:         andi16  $5, $7, 255
   ; MM32:         li16    $2, 0
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 255
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 255, %b
   ret i128 %r
 }
 
 define signext i1 @and_i1_32768(i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1_32768:
 
; ALL-LABEL: and_i64_32768:
   ; GP32:         andi    $3, $5, 32768
   ; GP32:         addiu   $2, $zero, 0
 
   ; GP64:         andi    $2, $4, 32768
 
   ; MM32:         andi16  $3, $5, 32768
   ; MM32:         li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 32768
-
   %r = and i64 32768, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128_32768(i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128_32768:
 
   ; GP32:         andi    $5, $7, 32768
   ; GP32:         addiu   $2, $zero, 0
   ; GP32:         addiu   $3, $zero, 0
   ; GP32:         addiu   $4, $zero, 0
 
   ; GP64:         andi    $3, $5, 32768
   ; GP64:         daddiu  $2, $zero, 0
 
   ; MM32:         andi16  $5, $7, 32768
   ; MM32:         li16    $2, 0
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 32768
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 32768, %b
   ret i128 %r
 }
 
 define signext i1 @and_i1_65(i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1_65:
 
; ALL-LABEL: and_i64_65:
   ; GP32:         andi    $3, $5, 65
   ; GP32:         addiu   $2, $zero, 0
 
   ; GP64:         andi    $2, $4, 65
 
   ; MM32-DAG:     andi    $3, $5, 65
   ; MM32-DAG:     li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 65
-
   %r = and i64 65, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128_65(i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128_65:
 
   ; GP32:         andi    $5, $7, 65
   ; GP32:         addiu   $2, $zero, 0
   ; GP32:         addiu   $3, $zero, 0
   ; GP32:         addiu   $4, $zero, 0
 
   ; GP64:         andi    $3, $5, 65
   ; GP64:         daddiu  $2, $zero, 0
 
   ; MM32-DAG:     andi    $5, $7, 65
   ; MM32-DAG:     li16    $2, 0
   ; MM32-DAG:     li16    $3, 0
   ; MM32-DAG:     li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 65
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 65, %b
   ret i128 %r
 }
 
 define signext i1 @and_i1_256(i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1_256:
 
; ALL-LABEL: and_i64_256:
   ; GP32:         andi    $3, $5, 256
   ; GP32:         addiu   $2, $zero, 0
 
   ; GP64:         andi    $2, $4, 256
 
   ; MM32-DAG:     andi    $3, $5, 256
   ; MM32-DAG:     li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 256
-
   %r = and i64 256, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128_256(i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128_256:
 
   ; GP32:         andi    $5, $7, 256
   ; GP32:         addiu   $2, $zero, 0
   ; GP32:         addiu   $3, $zero, 0
   ; GP32:         addiu   $4, $zero, 0
 
   ; GP64:         andi    $3, $5, 256
   ; GP64:         daddiu  $2, $zero, 0
 
   ; MM32-DAG:     andi    $5, $7, 256
   ; MM32-DAG:     li16    $2, 0
   ; MM32-DAG:     li16    $3, 0
   ; MM32-DAG:     li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 256
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 256, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/lh_lhu.ll

 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s
 
 @us = global i16 0, align 2
 
 define i32 @lhfunc() {
 entry:
 ; CHECK-LABEL: lhfunc
 ; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}})
   %0 = load i16, i16* @us, align 2

test/CodeGen/Mips/llvm-ir/mul.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,64R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=MM32,MM32R3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=MM32,MM32R6
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
-; RUN:   FileCheck %s -check-prefix=MM64R6
 
 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: mul_i1:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $[[T0:[0-9]+]]
   ; M2:         andi    $[[T0]], $[[T0]], 1
; ALL-LABEL: mul_i1:
   ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
   ; 64R1-R5:    andi    $[[T0]], $[[T0]], 1
   ; 64R1-R5:    negu    $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       andi    $[[T0]], $[[T0]], 1
   ; 64R6:       negu    $2, $[[T0]]
 
-  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
-  ; MM64R6:     andi16  $[[T0]], $[[T0]], 1
-  ; MM64R6:     li16    $[[T1:[0-9]+]], 0
-  ; MM64R6:     subu16  $2, $[[T1]], $[[T0]]
-
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       andi16  $[[T0]], $[[T0]], 1
   ; MM32:       li16    $[[T1:[0-9]+]], 0
   ; MM32:       subu16  $2, $[[T1]], $[[T0]]
 
   %r = mul i1 %a, %b
   ret i1 %r
 }
; ALL-LABEL: mul_i8:
   ; 64R1:       sra     $2, $[[T0]], 24
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seb     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seb     $2, $[[T0]]
 
-  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
-  ; MM64R6:     seb     $2, $[[T0]]
-
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       seb     $2, $[[T0]]
 
   %r = mul i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
; ALL-LABEL: mul_i16:
   ; 64R1:       sra     $2, $[[T0]], 16
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seh     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seh     $2, $[[T0]]
 
-  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
-  ; MM64R6:     seh     $2, $[[T0]]
-
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       seh     $2, $[[T0]]
 
   %r = mul i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: mul_i32:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
   ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
   ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
-  ; MM64R6:     mul     $2, $4, $5
 
   ; MM32:       mul     $2, $4, $5
 
   %r = mul i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
; ALL-LABEL: mul_i64:
 
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
   ; 64R1-R5:    dmult   $4, $5
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
-  ; MM64R6:     dmul    $2, $4, $5
 
   ; MM32R3:     multu   $[[T0:[0-9]+]], $7
   ; MM32R3:     mflo    $[[T1:[0-9]+]]
   ; MM32R3:     mfhi    $[[T2:[0-9]+]]
   ; MM32R3:     mul     $[[T0]], $[[T0]], $6
   ; MM32R3:     addu16  $2, $[[T2]], $[[T0]]
   ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
   ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T3]]
; ALL-LABEL: mul_i128:
   ; GP64-NOT-R6:    daddu   $2, $[[T3:[0-9]+]], $[[T0]]
 
   ; 64R6-DAG:       dmul    $[[T1:[0-9]+]], $5, $6
   ; 64R6:           dmuhu   $[[T2:[0-9]+]], $5, $7
   ; 64R6:           daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 64R6-DAG:       dmul    $[[T0:[0-9]+]], $4, $7
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
   ; 64R6-DAG:       dmul    $3, $5, $7
 
-  ; MM64R6-DAG:     dmul    $[[T1:[0-9]+]], $5, $6
-  ; MM64R6:         dmuhu   $[[T2:[0-9]+]], $5, $7
-  ; MM64R6:         daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; MM64R6-DAG:     dmul    $[[T0:[0-9]+]], $4, $7
-  ; MM64R6:         daddu   $2, $[[T1]], $[[T0]]
-  ; MM64R6-DAG:     dmul    $3, $5, $7
-
   ; MM32:           lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/not.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @not_i1(i1 signext %a) {
 entry:
 ; ALL-LABEL: not_i1:
 
   ; GP32:         not     $2, $4
 
   ; GP64:         not     $2, $4
; ALL-LABEL: not_i64:
   ; GP32:         not     $3, $5
 
   ; GP64:         daddiu  $[[T0:[0-9]+]], $zero, -1
   ; GP64:         xor     $2, $4, $[[T0]]
 
   ; MM32:         not16   $2, $4
   ; MM32:         not16   $3, $5
 
-  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
-  ; MM64:         xor     $2, $4, $[[T0]]
-
   %r = xor i64 %a, -1
   ret i64 %r
 }
 
 define signext i128 @not_i128(i128 signext %a) {
 entry:
 ; ALL-LABEL: not_i128:
 
   ; GP32:         not     $2, $4
   ; GP32:         not     $3, $5
   ; GP32:         not     $4, $6
   ; GP32:         not     $5, $7
 
   ; GP64:         daddiu  $[[T0:[0-9]+]], $zero, -1
   ; GP64:         xor     $2, $4, $[[T0]]
   ; GP64:         xor     $3, $5, $[[T0]]
 
   ; MM32:         not16   $2, $4
   ; MM32:         not16   $3, $5
   ; MM32:         not16   $4, $6
   ; MM32:         not16   $5, $7
 
-  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
-  ; MM64:         xor     $2, $4, $[[T0]]
-  ; MM64:         xor     $3, $5, $[[T0]]
-
   %r = xor i128 %a, -1
   ret i128 %r
 }
 
 define signext i1 @nor_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: nor_i1:
 
   ; GP32:         nor     $2, $5, $4
   ; GP64:         or      $1, $5, $4
   ; MM32:         nor     $2, $5, $4
-  ; MM64:         or      $1, $5, $4
 
   %or = or i1 %b, %a
   %r = xor i1 %or, -1
   ret i1 %r
 }
 
 define signext i8 @nor_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: nor_i8:
 
   ; GP32:         nor     $2, $5, $4
   ; GP64:         or      $1, $5, $4
   ; MM32:         nor     $2, $5, $4
-  ; MM64:         or      $1, $5, $4
 
   %or = or i8 %b, %a
   %r = xor i8 %or, -1
   ret i8 %r
 }
 
 define signext i16 @nor_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: nor_i16:
 
   ; GP32:         nor     $2, $5, $4
   ; GP64:         or      $1, $5, $4
   ; MM32:         nor     $2, $5, $4
-  ; MM64:         or      $1, $5, $4
 
   %or = or i16 %b, %a
   %r = xor i16 %or, -1
   ret i16 %r
 }
 
 define signext i32 @nor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: nor_i32:
 
   ; GP32:         nor     $2, $5, $4
 
   ; GP64:         or      $[[T0:[0-9]+]], $5, $4
   ; GP64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
   ; GP64:         not     $2, $[[T1]]
 
   ; MM32:         nor     $2, $5, $4
 
-  ; MM64:         or      $[[T0:[0-9]+]], $5, $4
-  ; MM64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
-  ; MM64:         not16   $2, $[[T1]]
-
   %or = or i32 %b, %a
   %r = xor i32 %or, -1
   ret i32 %r
 }
 
 
 define signext i64 @nor_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: nor_i64:
 
   ; GP32:         nor     $2, $6, $4
   ; GP32:         nor     $3, $7, $5
 
   ; GP64:         nor     $2, $5, $4
 
   ; MM32:         nor     $2, $6, $4
   ; MM32:         nor     $3, $7, $5
 
-  ; MM64:         nor     $2, $5, $4
-
   %or = or i64 %b, %a
   %r = xor i64 %or, -1
   ret i64 %r
 }
 
 define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: nor_i128:
; ALL-LABEL: nor_i128:
   ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32:         nor     $2, $[[T2]], $4
   ; MM32:         nor     $3, $[[T1]], $5
   ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         nor     $4, $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         nor     $5, $[[T3]], $7
 
-  ; MM64:         nor     $2, $6, $4
-  ; MM64:         nor     $3, $7, $5
-
   %or = or i128 %b, %a
   %r = xor i128 %or, -1
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/or.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1:
 
   ; GP32:         or      $2, $4, $5
 
   ; GP64:         or      $1, $4, $5
 
   ; MM32:         or16    $[[T0:[0-9]+]], $5
   ; MM32          move    $2, $[[T0]]
 
-  ; MM64:         or      $1, $4, $5
-
   %r = or i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @or_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: or_i8:
 
   ; GP32:         or      $2, $4, $5
 
   ; GP64:         or      $1, $4, $5
 
   ; MM32:         or16    $[[T0:[0-9]+]], $5
   ; MM32          move    $2, $[[T0]]
 
-  ; MM64:         or      $1, $4, $5
-
   %r = or i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @or_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: or_i16:
 
   ; GP32:         or      $2, $4, $5
 
   ; GP64:         or      $1, $4, $5
 
   ; MM32:         or16    $[[T0:[0-9]+]], $5
   ; MM32          move    $2, $[[T0]]
 
-  ; MM64:         or      $1, $4, $5
-
   %r = or i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
   ; GP32:         or      $2, $4, $5
 
   ; GP64:         or      $[[T0:[0-9]+]], $4, $5
   ; FIXME: The sll instruction below is redundant.
   ; GP64:         sll     $2, $[[T0]], 0
 
   ; MM32:         or16    $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         or      $[[T0:[0-9]+]], $4, $5
-  ; MM64:         sll     $2, $[[T0]], 0
-
   %r = or i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: or_i64:
 
   ; GP32:         or      $2, $4, $6
   ; GP32:         or      $3, $5, $7
 
   ; GP64:         or      $2, $4, $5
 
   ; MM32:         or16    $[[T0:[0-9]+]], $6
   ; MM32:         or16    $[[T1:[0-9]+]], $7
   ; MM32:         move    $2, $[[T0]]
   ; MM32:         move    $3, $[[T1]]
 
-  ; MM64:         or      $2, $4, $5
-
   %r = or i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128:
 
; ALL-LABEL: or_i128:
   ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32:         or16    $[[T2]], $4
   ; MM32:         or16    $[[T1]], $5
   ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         or16    $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         or16    $[[T3]], $7
 
-  ; MM64:         or      $2, $4, $6
-  ; MM64:         or      $3, $5, $7
-
   %r = or i128 %a, %b
   ret i128 %r
 }
 
 define signext i1 @or_i1_4(i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1_4:
 
; ALL-LABEL: or_i64_4:
   ; GP32:         ori     $3, $5, 4
   ; GP32:         move    $2, $4
 
   ; GP64:         ori     $2, $4, 4
 
   ; MM32:         ori     $3, $5, 4
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 4
-
   %r = or i64 4, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128_4(i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128_4:
 
   ; GP32:         ori     $[[T0:[0-9]+]], $7, 4
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         ori     $3, $5, 4
   ; GP64:         move    $2, $4
 
   ; MM32:         ori     $[[T0:[0-9]+]], $7, 4
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 4
-  ; MM64:         move    $2, $4
-
   %r = or i128 4, %b
   ret i128 %r
 }
 
 define signext i1 @or_i1_31(i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1_31:
 
; ALL-LABEL: or_i64_31:
   ; GP32:         ori     $3, $5, 31
   ; GP32:         move    $2, $4
 
   ; GP64:         ori     $2, $4, 31
 
   ; MM32:         ori     $3, $5, 31
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 31
-
   %r = or i64 31, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128_31(i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128_31:
 
   ; GP32:         ori     $[[T0:[0-9]+]], $7, 31
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         ori     $3, $5, 31
   ; GP64:         move    $2, $4
 
   ; MM32:         ori     $[[T0:[0-9]+]], $7, 31
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 31
-  ; MM64:         move    $2, $4
-
   %r = or i128 31, %b
   ret i128 %r
 }
 
 define signext i1 @or_i1_255(i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1_255:
 
; ALL-LABEL: or_i64_255:
   ; GP32:         ori     $3, $5, 255
   ; GP32:         move    $2, $4
 
   ; GP64:         ori     $2, $4, 255
 
   ; MM32:         ori     $3, $5, 255
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 255
-
   %r = or i64 255, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128_255(i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128_255:
 
   ; GP32:         ori     $[[T0:[0-9]+]], $7, 255
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         ori     $3, $5, 255
   ; GP64:         move    $2, $4
 
   ; MM32:         ori     $[[T0:[0-9]+]], $7, 255
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 255
-  ; MM64:         move    $2, $4
-
   %r = or i128 255, %b
   ret i128 %r
 }
 
 define signext i1 @or_i1_32768(i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1_32768:
 
; ALL-LABEL: or_i64_32768:
   ; GP32:         ori     $3, $5, 32768
   ; GP32:         move    $2, $4
 
   ; GP64:         ori     $2, $4, 32768
 
   ; MM32:         ori     $3, $5, 32768
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 32768
-
   %r = or i64 32768, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128_32768(i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128_32768:
 
   ; GP32:         ori     $[[T0:[0-9]+]], $7, 32768
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         ori     $3, $5, 32768
   ; GP64:         move    $2, $4
 
   ; MM32:         ori     $[[T0:[0-9]+]], $7, 32768
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 32768
-  ; MM64:         move    $2, $4
-
   %r = or i128 32768, %b
   ret i128 %r
 }
 
 define signext i1 @or_i1_65(i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1_65:
 
; ALL-LABEL: or_i64_65:
   ; GP32:         ori     $3, $5, 65
   ; GP32:         move    $2, $4
 
   ; GP64:         ori     $2, $4, 65
 
   ; MM32:         ori     $3, $5, 65
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 65
-
   %r = or i64 65, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128_65(i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128_65:
 
   ; GP32:         ori     $[[T0:[0-9]+]], $7, 65
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         ori     $3, $5, 65
   ; GP64:         move    $2, $4
 
   ; MM32:         ori     $[[T0:[0-9]+]], $7, 65
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 65
-  ; MM64:         move    $2, $4
-
   %r = or i128 65, %b
   ret i128 %r
 }
 
 define signext i1 @or_i1_256(i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1_256:
 
; ALL-LABEL: or_i64_256:
   ; GP32:         ori     $3, $5, 256
   ; GP32:         move    $2, $4
 
   ; GP64:         ori     $2, $4, 256
 
   ; MM32:         ori     $3, $5, 256
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 256
-
   %r = or i64 256, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128_256(i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128_256:
 
   ; GP32:         ori     $[[T0:[0-9]+]], $7, 256
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         ori     $3, $5, 256
   ; GP64:         move    $2, $4
 
   ; MM32:         ori     $[[T0:[0-9]+]], $7, 256
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 256
-  ; MM64:         move    $2, $4
-
   %r = or i128 256, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/sdiv.ll

 ; RUN:    -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,R6,64R6
 
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i1:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $[[T0:[0-9]+]]
; ALL-LABEL: sdiv_i64:
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mflo    $2
 
   ; 64R6:         ddiv    $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
   ; MM32:         lw      $25, %call16(__divdi3)($2)
 
-  ; MM64:         ddiv    $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = sdiv i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
 entry:
   ; ALL-LABEL: sdiv_i128:
 
   ; GP32:         lw      $25, %call16(__divti3)($gp)
 
   ; GP64-NOT-R6:  ld      $25, %call16(__divti3)($gp)
   ; 64R6:         ld      $25, %call16(__divti3)($gp)
 
   ; MM32:         lw      $25, %call16(__divti3)($16)
 
-  ; MM64:         ld      $25, %call16(__divti3)($2)
-
   %r = sdiv i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/srem.ll

 ; RUN:    -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,64R6,R6,R2-R6
 
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: srem_i1:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $[[T0:[0-9]+]]
; ALL-LABEL: srem_i64:
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mfhi    $2
 
   ; 64R6:         dmod    $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
   ; MM32:         lw      $25, %call16(__moddi3)($2)
 
-  ; MM64:         dmod    $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = srem i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: srem_i128:
 
   ; GP32:         lw      $25, %call16(__modti3)($gp)
 
   ; GP64-NOT-R6:  ld      $25, %call16(__modti3)($gp)
   ; 64R6:         ld      $25, %call16(__modti3)($gp)
 
   ; MM32:         lw      $25, %call16(__modti3)($16)
 
-  ; MM64:         ld      $25, %call16(__modti3)($2)
-
   %r = srem i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/sub.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=GP64,MM64
 
 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sub_i1:
 
   ; NOT-MM:         subu    $[[T0:[0-9]+]], $4, $5
   ; NOT-MM:         andi    $[[T0]], $[[T0]], 1
   ; NOT-MM:         negu    $2, $[[T0]]

 ; FIXME: Likewise for the sltu, dext here.
 
 ; GP64-R2:     dsubu     $1, $4, $6
 ; GP64-R2:     sltu      $[[T0:[0-9]+]], $5, $7
 ; GP64-R2:     dext      $[[T1:[0-9]+]], $[[T0]], 0, 32
 ; GP64-R2:     dsubu     $2, $1, $[[T1]]
 ; GP64-R2:     dsubu     $3, $5, $7
 
-; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the
-;        dext instruction which should be used here.
-
-; MM64: dsubu   $[[T0:[0-9]+]], $4, $6
-; MM64: sltu    $[[T1:[0-9]+]], $5, $7
-; MM64: dsll    $[[T2:[0-9]+]], $[[T1]], 32
-; MM64: dsrl    $[[T3:[0-9]+]], $[[T2]], 32
-; MM64: dsubu   $2, $[[T0]], $[[T3]]
-; MM64: dsubu   $3, $5, $7
-
   %r = sub i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/udiv.ll

 ; RUN:    -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,R6,64R6
 
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i1:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
; ALL-LABEL: udiv_i64:
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mflo    $2
 
   ; 64R6:         ddivu   $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
   ; MM32:         lw      $25, %call16(__udivdi3)($2)
 
-  ; MM64:         ddivu   $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = udiv i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: udiv_i128:
 
   ; GP32:         lw      $25, %call16(__udivti3)($gp)
 
   ; GP64-NOT-R6:  ld      $25, %call16(__udivti3)($gp)
   ; 64-R6:        ld      $25, %call16(__udivti3)($gp)
 
   ; MM32:         lw      $25, %call16(__udivti3)($16)
 
-  ; MM64:         ld      $25, %call16(__udivti3)($2)
-
   %r = udiv i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/urem.ll

 ; RUN:    -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,64R6,R6,R2-R6
 
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: urem_i1:
 
   ; NOT-R6:       andi    $[[T0:[0-9]+]], $5, 1
   ; NOT-R6:       andi    $[[T1:[0-9]+]], $4, 1
   ; NOT-R6:       divu    $zero, $[[T1]], $[[T0]]
; ALL-LABEL: urem_i64:
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mfhi    $2
 
   ; 64R6:         dmodu   $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
   ; MM32:         lw      $25, %call16(__umoddi3)($2)
 
-  ; MM64:         dmodu   $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = urem i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
 entry:
   ; ALL-LABEL: urem_i128:
 
   ; GP32:         lw      $25, %call16(__umodti3)($gp)
 
   ; GP64-NOT-R6:  ld      $25, %call16(__umodti3)($gp)
   ; 64R6:         ld      $25, %call16(__umodti3)($gp)
 
   ; MM32:         lw      $25, %call16(__umodti3)($16)
 
-  ; MM64:         ld      $25, %call16(__umodti3)($2)
-
     %r = urem i128 %a, %b
     ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/xor.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: xor_i1:
 
   ; GP32:         xor     $2, $4, $5
 
   ; GP64:         xor     $1, $4, $5
 
   ; MM32:         xor16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         xor     $1, $4, $5
-
   %r = xor i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @xor_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: xor_i8:
 
   ; GP32:         xor     $2, $4, $5
 
   ; GP64:         xor     $1, $4, $5
 
   ; MM32:         xor16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         xor     $1, $4, $5
-
   %r = xor i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @xor_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: xor_i16:
 
   ; GP32:         xor     $2, $4, $5
 
   ; GP64:         xor     $1, $4, $5
 
   ; MM32:         xor16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         xor     $1, $4, $5
-
   %r = xor i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
   ; GP32:         xor     $2, $4, $5
 
   ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
   ; GP64:         sll     $2, $[[T0]], 0
 
   ; MM32:         xor16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; MM64:         sll     $2, $[[T0]], 0
-
   %r = xor i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: xor_i64:
 
   ; GP32:         xor     $2, $4, $6
   ; GP32:         xor     $3, $5, $7
 
   ; GP64:         xor     $2, $4, $5
 
   ; MM32:         xor16   $[[T0:[0-9]+]], $6
   ; MM32:         xor16   $[[T1:[0-9]+]], $7
   ; MM32:         move    $2, $[[T0]]
   ; MM32:         move    $3, $[[T1]]
 
-  ; MM64:         xor     $2, $4, $5
-
   %r = xor i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: xor_i128:
 
; ALL-LABEL: xor_i128:
   ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32:         xor16   $[[T2]], $4
   ; MM32:         xor16   $[[T1]], $5
   ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         xor16   $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         xor16   $[[T3]], $7
 
-  ; MM64:         xor     $2, $4, $6
-  ; MM64:         xor     $3, $5, $7
-
   %r = xor i128 %a, %b
   ret i128 %r
 }
 
 define signext i1 @xor_i1_4(i1 signext %b) {
 entry:
 ; ALL-LABEL: xor_i1_4:
 
; ALL-LABEL: xor_i64_4:
   ; GP32:         xori    $3, $5, 4
   ; GP32:         move    $2, $4
 
   ; GP64:         xori    $2, $4, 4
 
   ; MM32:         xori    $3, $5, 4
   ; MM32:         move    $2, $4
 
-  ; MM64:         xori    $2, $4, 4
-
   %r = xor i64 4, %b
   ret i64 %r
 }
 
 define signext i128 @xor_i128_4(i128 signext %b) {
 entry:
 ; ALL-LABEL: xor_i128_4:
 
   ; GP32:         xori    $[[T0:[0-9]+]], $7, 4
   ; GP32:         move    $2, $4
   ; GP32:         move    $3, $5
   ; GP32:         move    $4, $6
   ; GP32:         move    $5, $[[T0]]
 
   ; GP64:         xori    $3, $5, 4
   ; GP64:         move    $2, $4
 
   ; MM32:         xori    $[[T0:[0-9]+]], $7, 4
   ; MM32:         move    $2, $4
   ; MM32:         move    $3, $5
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         xori    $3, $5, 4
-  ; MM64:         move    $2, $4
-
   %r = xor i128 4, %b
   ret i128 %r
 }

test/CodeGen/Mips/lw16-base-reg.ll

 ; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
 ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
-; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \
-; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
 
 ; The purpose of this test is to check whether the CodeGen selects
 ; LW16 instruction with the base register in a range of $2-$7, $16, $17.
 
 %struct.T = type { i32 }
 
 $_ZN1TaSERKS_ = comdat any
 

test/CodeGen/Mips/micromips-lwc1-swc1.ll

 ; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \
 ; RUN:   -relocation-model=pic < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,MM32
 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
 ; RUN:   -relocation-model=pic < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,MM32
-; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \
-; RUN:   -relocation-model=pic < %s | \
-; RUN:   FileCheck %s -check-prefixes=ALL,MM64
 
 @gf0 = external global float
 
 define float @test_lwc1() {
 entry:
 ; CHECK-LABEL: test_lwc1
 ; MM32:      lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; MM32:      addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
 ; MM32:      addu    $[[R2:[0-9]+]], $[[R1]], $25
 ; MM32:      lw      $[[R3:[0-9]+]], %got(gf0)($[[R2]])
 ; MM32:      lwc1    $f0, 0($[[R3]])
 
-; MM64:      lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1)))
-; MM64:      daddu   $[[R1:[0-9]+]], $[[R0]], $25
-; MM64:      daddiu  $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1)))
-; MM64:      ld      $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
-; MM64:      lwc1    $f0, 0($[[R3]])
-
   %0 = load float, float* @gf0, align 4
   ret float %0
 }
 
 define void @test_swc1(float %a) {
 entry:
 ; CHECK-LABEL: test_swc1
 ; MM32:      lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; MM32:      addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
 ; MM32:      addu    $[[R2:[0-9]+]], $[[R1]], $25
 ; MM32:      lw      $[[R3:[0-9]+]], %got(gf0)($[[R2]])
 ; MM32:      swc1    $f12, 0($[[R3]])
 
-; MM64:      lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1)))
-; MM64:      daddu   $[[R1:[0-9]+]], $[[R0]], $25
-; MM64:      daddiu  $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1)))
-; MM64:      ld      $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
-; MM64:      swc1    $f12, 0($[[R3]])
-
   store float %a, float* @gf0, align 4
   ret void
 }
 

test/CodeGen/Mips/mips64fpldst.ll

 ; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc  < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc  < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 
 @f0 = common global float 0.000000e+00, align 4
 @d0 = common global double 0.000000e+00, align 8
 @f1 = common global float 0.000000e+00, align 4
 @d1 = common global double 0.000000e+00, align 8
 
 define float @funcfl1() nounwind readonly {
 entry:

test/CodeGen/Mips/mips64shift.ll

 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s
 
 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; ALL: dsllv
   %shl = shl i64 %a0, %a1
   ret i64 %shl
 }
 

test/CodeGen/Mips/tailcall/tailcall.ll

 ; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64
 ; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6  \
 ; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
 
 ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
 ; RUN:      -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
 ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
 ; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
-; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
-; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
-; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
-; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
 
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4
 @g2 = common global i32 0, align 4
 @g3 = common global i32 0, align 4
 @g4 = common global i32 0, align 4
 @g5 = common global i32 0, align 4
 @g6 = common global i32 0, align 4

 ; ALL-LABEL: caller8_0:
 ; PIC32: jr $25
 ; PIC32R6: jrc $25
 ; PIC32MM: jrc
 ; STATIC32: j
 ; STATIC32MMR6: bc
 ; PIC64: jr $25
 ; PIC64R6: jrc $25
-; PIC64R6MM: jrc $25
 ; STATIC64: j
 ; PIC16: jalrc
 
   %call = tail call fastcc i32 @caller8_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller8_1() nounwind noinline {

test/MC/Mips/mips64extins.s

 # RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
 # RUN:   | llvm-objdump -disassemble - | FileCheck --check-prefix=OBJ %s
-# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r6 -mattr=+micromips \
-# RUN:         -target-abi=n64 %s -o - | llvm-objdump -disassemble - \
-# RUN:   | FileCheck --check-prefix=OBJ %s
 
 # RUN: llvm-mc -arch=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \
 # RUN:   | FileCheck --check-prefix=ASM %s
-# RUN: llvm-mc -arch=mips64el -mcpu=mips64r6 -mattr=+micromips -target-abi=n64 \
-# RUN:     %s -o - | FileCheck --check-prefix=ASM %s
 
         dext $2, $4, 5, 10   # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
         dextu $2, $4, 34, 6  # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
         dextm $2, $4, 5, 34  # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
         dins $4, $5, 8, 10   # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
         dinsm $4, $5, 30, 6  # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 30, 6
         dinsu $4, $5, 40, 13 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
         # check the aliases