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[AMDGPU][MC] Optimized IsRegIntersect
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Authored by dp on Jul 15 2017, 4:55 AM.

Reviewers

arsenm
artem.tamazov

Commits

Summary

Second part of original D34890 (https://reviews.llvm.org/D34890) split in two as requested by reviewers.

dp created this revision.Jul 15 2017, 4:55 AM

LGTM

This revision is now accepted and ready to land.Jul 17 2017, 7:49 AM

This revision was automatically updated to reflect the committed changes.

Path

Size

lib/

Target/

AMDGPU/

Utils/

18 lines

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	bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {			bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
	const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);			const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
	const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);			const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
	return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) \|\|			return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) \|\|
	Reg == AMDGPU::SCC;			Reg == AMDGPU::SCC;
	}			}

	bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {			bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
				for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
	if (Reg0 == Reg1) {			if (*R == Reg1) return true;
	return true;
	}			}

	unsigned SubReg0 = TRI->getSubReg(Reg0, 1);
	if (SubReg0 == 0) {
	return TRI->getSubRegIndex(Reg1, Reg0) > 0;
	}

	for (unsigned Idx = 2; SubReg0 > 0; ++Idx) {
	if (isRegIntersect(Reg1, SubReg0, TRI)) {
	return true;
	}
	SubReg0 = TRI->getSubReg(Reg0, Idx);
	}

	return false;			return false;
	}			}

	unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {			unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {

	switch(Reg) {			switch(Reg) {
	default: break;			default: break;
	case AMDGPU::FLAT_SCR:			case AMDGPU::FLAT_SCR:
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