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Differential D35237

[ScopInfo] Simplify new access functions under domain context
ClosedPublic

Authored by grosser on Jul 11 2017, 1:55 AM.

Details

Reviewers
Meinersbur
bollu
gareevroman
efriedma
huihuiz
sebpop
simbuerg
Commits
rG4556c9b8feec: [ScopInfo] Simplify new access functions under domain context
rPLO308215: [ScopInfo] Simplify new access functions under domain context
rL308215: [ScopInfo] Simplify new access functions under domain context
Summary

We do not keep domain constraints on access functions when building the
scop. Hence, for consistency reasons, it makes also sense to not include
them when storing a new access function. This change results in simpler
access functions that make output easier to read.

This patch also helps to make DeLICMed memory accesses to be understood by
our matrix multiplication pattern matching pass. Further changes to the
matrix multiplication pattern matching are needed for this to work, so the
corresponding test case will be added in a future commit.

Diff Detail

Event Timeline

grosser created this revision.Jul 11 2017, 1:55 AM
bollu added inline comments.Jul 12 2017, 6:45 AM
lib/Analysis/ScopInfo.cpp
1240

can this be re-written as:

NewAccessRelation = isl_map_gist_domain(NewAccess, getStatement()->getDomain())
grosser added a comment.Jul 14 2017, 1:58 AM

Yes, I can change this.

grosser mentioned this in D33138: [Polly][WIP] Make the pattern matching work with modified memory accesses.Jul 16 2017, 2:51 AM
Closed by commit rL308215: [ScopInfo] Simplify new access functions under domain context (authored by grosser). · Explain WhyJul 17 2017, 1:47 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 105977

lib/Analysis/ScopInfo.cpp

Show First 20 Lines • Show All 1,230 Lines • ▼ Show 20 Lines#ifndef NDEBUG
auto Dims = SAI->getNumberOfDimensions(); auto Dims = SAI->getNumberOfDimensions();
assert(isl_space_dim(NewAccessSpace, isl_dim_set) == Dims && assert(isl_space_dim(NewAccessSpace, isl_dim_set) == Dims &&
"Access dims must match array dims"); "Access dims must match array dims");
isl_space_free(NewAccessSpace); isl_space_free(NewAccessSpace);
isl_id_free(NewArrayId); isl_id_free(NewArrayId);
#endif #endif
isl_map_free(NewAccessRelation); isl_map_free(NewAccessRelation);
NewAccess = isl_map_gist_domain(NewAccess, getStatement()->getDomain());
NewAccessRelation = NewAccess; NewAccessRelation = NewAccess;
bolluUnsubmitted
Not Done
ReplyInline Actions

can this be re-written as:

NewAccessRelation = isl_map_gist_domain(NewAccess, getStatement()->getDomain())
bollu: can this be re-written as: ```lang=cpp NewAccessRelation = isl_map_gist_domain(NewAccess…
} }
bool MemoryAccess::isLatestPartialAccess() const { bool MemoryAccess::isLatestPartialAccess() const {
isl::set StmtDom = give(getStatement()->getDomain()); isl::set StmtDom = give(getStatement()->getDomain());
isl::set AccDom = give(isl_map_domain(getLatestAccessRelation())); isl::set AccDom = give(isl_map_domain(getLatestAccessRelation()));
return isl_set_is_subset(StmtDom.keep(), AccDom.keep()) == isl_bool_false; return isl_set_is_subset(StmtDom.keep(), AccDom.keep()) == isl_bool_false;
} }
▲ Show 20 Lines • Show All 3,876 Lines • Show Last 20 Lines

test/DeLICM/reduction.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Linesreturn:
ret void ret void
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_outer_for ; CHECK-NEXT: Stmt_outer_for
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_outer_for[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_outer_for[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_outer_for[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_outer_for[i0] -> MemRef_A[i0] : i0 <= 1 };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_constant_selfconflict.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesreturn:
ret void ret void
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 8 - 5i0 and i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 >= 0 and -5i0 <= i1 <= 7 - 5i0 and i1 <= 3; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 <= 7 - 5i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_looprotate_gvnpre.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Linesreturn:
ret void ret void
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 and 3i1 <= 22 - 13i0 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }
; PARTIAL: After accesses { ; PARTIAL: After accesses {
; PARTIAL-NEXT: Stmt_reduction_preheader ; PARTIAL-NEXT: Stmt_reduction_preheader
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; PARTIAL-NEXT: Stmt_reduction_for ; PARTIAL-NEXT: Stmt_reduction_for
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: Stmt_body ; PARTIAL-NEXT: Stmt_body
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 and 3i1 <= 22 - 13i0 }; ; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] }; ; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: Stmt_reduction_inc ; PARTIAL-NEXT: Stmt_reduction_inc
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 2 and 3i1 >= -13i0 }; ; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 <= 2 };
; PARTIAL-NEXT: } ; PARTIAL-NEXT: }

test/DeLICM/reduction_looprotate_hoisted.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; load-hoisting %Start is an affine loop. To be fixed in ScopBuilder. ; load-hoisting %Start is an affine loop. To be fixed in ScopBuilder.
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_i__phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_i__phi[] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_i__phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_i__phi[] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and -i0 < i1 <= 3 - Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start >= 4; Stmt_reduction_for[0, 0] -> MemRef_A[0] }; ; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : -i0 < i1 <= 3 - Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start >= 4; Stmt_reduction_for[0, 0] -> MemRef_A[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_reduction_for[i0, 0] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= -4 + Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start <= 4 }; ; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_reduction_for[i0, 0] -> MemRef_A[i0] : i0 <= -4 + Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start <= 4 };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_i[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_i[] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_body[i0, i1] -> MemRef_mul[] }; ; CHECK-NEXT: [Start] -> { Stmt_body[i0, i1] -> MemRef_mul[] };
; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_body[i0, 0] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= -4 + Start; Stmt_body[1, 0] -> MemRef_A[1] : Start <= 4 }; ; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_body[i0, 0] -> MemRef_A[i0] : i0 <= -4 + Start; Stmt_body[1, 0] -> MemRef_A[1] : Start <= 4 };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : Start <= 3 and 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_body[1, 0] -> MemRef_A[1]; Stmt_body[0, 0] -> MemRef_A[0] : Start >= 4 }; ; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_body[1, 0] -> MemRef_A[1]; Stmt_body[0, 0] -> MemRef_A[0] : Start >= 4 };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_i__phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_i__phi[] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_mul[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_mul[] };
; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : Start <= 3 and 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_reduction_inc[1, 0] -> MemRef_A[1]; Stmt_reduction_inc[0, 0] -> MemRef_A[0] : Start >= 4 }; ; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_reduction_inc[1, 0] -> MemRef_A[1]; Stmt_reduction_inc[0, 0] -> MemRef_A[0] : Start >= 4 };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 < i1 <= 3 - Start; Stmt_reduction_inc[i0, 0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 < i1 <= 3 - Start; Stmt_reduction_inc[i0, 0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_i[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_i[] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_mul[] }; ; CHECK-NEXT: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_mul[] };
; CHECK-NEXT: new: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_looprotate_licm.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_looprotate_load.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_StartPtr[0] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_StartPtr[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_looprotate_readonly.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_Start[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_Start[] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_looprotate_synthesizable.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linesreturn:
ret void ret void
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_mul[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_mul[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_mul[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_mul[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_mul[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_mul[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_looprotate_undef.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
return: return:
ret void ret void
} }
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_conv[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_conv[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_conv[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_conv[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_conv[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_conv[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/DeLICM/reduction_overapproximate.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Linesreturn:
ret void ret void
} }
; APPROX: After accesses { ; APPROX: After accesses {
; APPROX-NEXT: Stmt_reduction_checkloop ; APPROX-NEXT: Stmt_reduction_checkloop
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_checkloop[i0] -> MemRef_val__phi[] }; ; APPROX-NEXT: { Stmt_reduction_checkloop[i0] -> MemRef_val__phi[] };
; APPROX-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 3 }; ; APPROX-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_preheader ; APPROX-NEXT: Stmt_reduction_preheader
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; APPROX-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; APPROX-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] : 2 <= i0 <= 3 }; ; APPROX-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_for ; APPROX-NEXT: Stmt_reduction_for
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; APPROX-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; APPROX-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_body ; APPROX-NEXT: Stmt_body
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; APPROX-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 10 - 3i0 and i1 <= 1 and i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; APPROX-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_inc ; APPROX-NEXT: Stmt_reduction_inc
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[2] : i0 <= 3 and 0 <= i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[2] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_val__phi[] }; ; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_val__phi[] };
; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 }; ; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_exit ; APPROX-NEXT: Stmt_reduction_exit
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_exit[i0] -> MemRef_val__phi[] }; ; APPROX-NEXT: { Stmt_reduction_exit[i0] -> MemRef_val__phi[] };
; APPROX-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 3 }; ; APPROX-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; APPROX-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] }; ; APPROX-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: } ; APPROX-NEXT: }
; EXACT: No modification has been made ; EXACT: No modification has been made
; PARTIAL: After accesses { ; PARTIAL: After accesses {
; PARTIAL-NEXT: Stmt_reduction_checkloop ; PARTIAL-NEXT: Stmt_reduction_checkloop
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_checkloop[i0] -> MemRef_val__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_checkloop[i0] -> MemRef_val__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 1 }; ; PARTIAL-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] : i0 <= 1 };
; PARTIAL-NEXT: Stmt_reduction_preheader ; PARTIAL-NEXT: Stmt_reduction_preheader
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] : 2 <= i0 <= 3 }; ; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_reduction_for ; PARTIAL-NEXT: Stmt_reduction_for
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 }; ; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 }; ; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_body ; PARTIAL-NEXT: Stmt_body
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 10 - 3i0 and i1 <= 1 and i1 <= -2 + i0 }; ; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 }; ; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_reduction_inc ; PARTIAL-NEXT: Stmt_reduction_inc
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 }; ; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_inc[3, 0] -> MemRef_A[2] }; ; PARTIAL-NEXT: new: { Stmt_reduction_inc[3, 0] -> MemRef_A[2] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_val__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_val__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, -2 + i0] -> MemRef_A[-1 + i0] : 2 <= i0 <= 3 }; ; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, -2 + i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_reduction_exit ; PARTIAL-NEXT: Stmt_reduction_exit
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_exit[i0] -> MemRef_val__phi[] }; ; PARTIAL-NEXT: { Stmt_reduction_exit[i0] -> MemRef_val__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 3 }; ; PARTIAL-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; PARTIAL-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] }; ; PARTIAL-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: } ; PARTIAL-NEXT: }

test/DeLICM/reduction_preheader.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; [27] Stmt_reduction_inc[1, 3] ; [27] Stmt_reduction_inc[1, 3]
; [28] Stmt_reduction_for[1, 4] ; [28] Stmt_reduction_for[1, 4]
; [29] Stmt_reduction_exit[1] ; [29] Stmt_reduction_exit[1]
; CHECK: After accesses { ; CHECK: After accesses {
; CHECK-NEXT: Stmt_reduction_preheader ; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 8 - 5i0 and i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 >= 0 and -5i0 <= i1 <= 7 - 5i0 and i1 <= 3; Stmt_reduction_inc[1, 3] -> MemRef_A[1] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 <= 7 - 5i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 3 }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: } ; CHECK-NEXT: }

test/Isl/CodeGen/MemAccess/map_scalar_access.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; CHECK-NEXT: new: { Stmt_outer_for[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_outer_for[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for ; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: Domain := ; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_reduction_for[0, i1] : 0 <= i1 <= 4 }; ; CHECK-NEXT: { Stmt_reduction_for[0, i1] : 0 <= i1 <= 4 };
; CHECK-NEXT: Schedule := ; CHECK-NEXT: Schedule :=
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> [0, 1, i1, 0] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> [0, 1, i1, 0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: Stmt_body ; CHECK-NEXT: Stmt_body
; CHECK-NEXT: Domain := ; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_body[0, i1] : 0 <= i1 <= 3 }; ; CHECK-NEXT: { Stmt_body[0, i1] : 0 <= i1 <= 3 };
; CHECK-NEXT: Schedule := ; CHECK-NEXT: Schedule :=
; CHECK-NEXT: { Stmt_body[i0, i1] -> [0, 1, i1, 1] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> [0, 1, i1, 1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: Stmt_reduction_inc ; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: Domain := ; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_reduction_inc[0, i1] : 0 <= i1 <= 3 }; ; CHECK-NEXT: { Stmt_reduction_inc[0, i1] : 0 <= i1 <= 3 };
; CHECK-NEXT: Schedule := ; CHECK-NEXT: Schedule :=
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> [0, 1, i1, 2] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> [0, 1, i1, 2] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] }; ; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: Stmt_reduction_exit ; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: Domain := ; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_reduction_exit[0] }; ; CHECK-NEXT: { Stmt_reduction_exit[0] };
; CHECK-NEXT: Schedule := ; CHECK-NEXT: Schedule :=
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> [0, 2, 0, 0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> [0, 2, 0, 0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[0] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[0] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] }; ; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] }; ; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[0] };
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK: New access function '{ Stmt_outer_for[i0] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK: New access function '{ Stmt_outer_for[i0] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK-NEXT: New access function '{ Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK-NEXT: New access function '{ Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_body[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK-NEXT: New access function '{ Stmt_body[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_body[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK-NEXT: New access function '{ Stmt_body[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK-NEXT: New access function '{ Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file ; CHECK-NEXT: New access function '{ Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
Show All 36 Lines

test/ScheduleOptimizer/mat_mul_pattern_data_layout.ll

Show All 16 Lines
; for (k = 0; k < _PB_NK; ++k) ; for (k = 0; k < _PB_NK; ++k)
; C[i][j] += alpha * A[i][k] * B[k][j]; ; C[i][j] += alpha * A[i][k] * B[k][j];
; } ; }
; ;
; CHECK: double Packed_B[ { [] -> [(256)] } ][ { [] -> [(256)] } ][ { [] -> [(8)] } ]; ; CHECK: double Packed_B[ { [] -> [(256)] } ][ { [] -> [(256)] } ][ { [] -> [(8)] } ];
; CHECK-NEXT: double Packed_A[ { [] -> [(24)] } ][ { [] -> [(256)] } ][ { [] -> [(4)] } ]; // Element size 8 ; CHECK-NEXT: double Packed_A[ { [] -> [(24)] } ][ { [] -> [(256)] } ][ { [] -> [(4)] } ]; // Element size 8
; ;
; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg6[i0, i2] }; ; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg6[i0, i2] };
; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 4*floor((-i0 + o2)/4) = -i0 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 3 and -3 + i0 - 4o0 <= 96*floor((i0)/96) <= i0 - 4o0 }; ; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 96*floor((-i0 + 4o0 + o2)/96) = -i0 + 4o0 + o2 and 0 <= o1 <= 255 and o2 >= 0 and -4o0 <= o2 <= 95 - 4o0 and o2 <= 3 };
; ;
; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg7[i2, i1] }; ; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg7[i2, i1] };
; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_B[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 8*floor((-i1 + o2)/8) = -i1 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 7 and -7 + i1 - 8o0 <= 2048*floor((i1)/2048) <= i1 - 8o0 }; ; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_B[o0, o1, i1 - 8o0] : 256*floor((-i2 + o1)/256) = -i2 + o1 and -7 + i1 <= 8o0 <= i1 and 0 <= o1 <= 255 };
; ;
; CHECK: CopyStmt_0 ; CHECK: CopyStmt_0
; CHECK-NEXT: Domain := ; CHECK-NEXT: Domain :=
; CHECK-NEXT: { CopyStmt_0[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 }; ; CHECK-NEXT: { CopyStmt_0[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 };
; CHECK-NEXT: Schedule := ; CHECK-NEXT: Schedule :=
; CHECK-NEXT: ; ; CHECK-NEXT: ;
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null; ; CHECK-NEXT: null;
; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> Packed_B[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 8*floor((-i1 + o2)/8) = -i1 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 7 and -7 + i1 - 8o0 <= 2048*floor((i1)/2048) <= i1 - 8o0 }; ; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> Packed_B[o0, o1, i1 - 8o0] : 256*floor((-i2 + o1)/256) = -i2 + o1 and -7 + i1 <= 8o0 <= i1 and 0 <= o1 <= 255 };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null; ; CHECK-NEXT: null;
; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> MemRef_arg7[i2, i1] }; ; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> MemRef_arg7[i2, i1] };
; CHECK-NEXT: CopyStmt_1 ; CHECK-NEXT: CopyStmt_1
; CHECK-NEXT: Domain := ; CHECK-NEXT: Domain :=
; CHECK-NEXT: { CopyStmt_1[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 }; ; CHECK-NEXT: { CopyStmt_1[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 };
; CHECK-NEXT: Schedule := ; CHECK-NEXT: Schedule :=
; CHECK-NEXT: ; ; CHECK-NEXT: ;
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null; ; CHECK-NEXT: null;
; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 4*floor((-i0 + o2)/4) = -i0 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 3 and -3 + i0 - 4o0 <= 96*floor((i0)/96) <= i0 - 4o0 }; ; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 96*floor((-i0 + 4o0 + o2)/96) = -i0 + 4o0 + o2 and 0 <= o1 <= 255 and o2 >= 0 and -4o0 <= o2 <= 95 - 4o0 and o2 <= 3 };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null; ; CHECK-NEXT: null;
; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> MemRef_arg6[i0, i2] }; ; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> MemRef_arg6[i0, i2] };
; ;
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown" target triple = "x86_64-unknown-unknown"
define internal void @kernel_gemm(i32 %arg, i32 %arg1, i32 %arg2, double %arg3, double %arg4, [1056 x double]* %arg5, [1024 x double]* %arg6, [1056 x double]* %arg7) #0 { define internal void @kernel_gemm(i32 %arg, i32 %arg1, i32 %arg2, double %arg3, double %arg4, [1056 x double]* %arg5, [1024 x double]* %arg6, [1056 x double]* %arg7) #0 {
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