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Differential D35214

[compiler-rt][X86] Match the detection of cpu's for __cpu_model to the latest version of gcc
ClosedPublic

Authored by craig.topper on Jul 10 2017, 11:03 AM.

Details

Reviewers
echristo
asbirlea
RKSimon
erichkeane
zvi
Commits
rGe6b07073ca3c: [compiler-rt][X86] Match the detection of cpu's for __cpu_model to the latest…
rCRT307878: [compiler-rt][X86] Match the detection of cpu's for __cpu_model to the latest…
rL307878: [compiler-rt][X86] Match the detection of cpu's for __cpu_model to the latest…
Summary

We were missing many feature flags that newer gcc supports and we had our own set of feature flags that gcc didnt' support that were overlapping. Clang's implementation assumes gcc's features list so a mismatch here is problematic.

I've also matched the cpu type/subtype lists with gcc and removed all the cpus that gcc doesn't support. I've also removed the fallback autodetection logic that was taken from Host.cpp. It was the main reason we had extra feature flags relative to gcc. I don't think gcc does this in libgcc.

Unfortunately, libgcc seems to have ignored their own source code comment and has added new cpu types/subtypes in the middle of their enums at various times so I can't guarantee any compatibility with older libgcc here. But maybe once we have a matching implementation we can treat that as a reason to file bugs against libgcc if they do it again going forward.

Once this support is in place we can consider implementing __builtin_cpu_is in clang. This could also be needed for function dispatching that Erich Keane is working on.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Jul 10 2017, 11:03 AM
Herald added a subscriber: dberris. · View Herald TranscriptJul 10 2017, 11:03 AM
craig.topper updated this revision to Diff 105886.Jul 10 2017, 11:06 AM

Add back INTEL_CORE2 to the switch. Guess I got carried away with deleting.

asbirlea edited edge metadata.Jul 10 2017, 11:30 AM

Does it make sense to update this together with Host.cpp?

craig.topper added a comment.Jul 10 2017, 11:47 AM

I can't remove the older processors from Host.cpp. Host.cpp also contains a newer processor called Goldmont that's not in libgcc yet. I think these files have slightly different goals.

echristo edited edge metadata.Jul 10 2017, 1:12 PM
In D35214#804024, @craig.topper wrote:

I can't remove the older processors from Host.cpp. Host.cpp also contains a newer processor called Goldmont that's not in libgcc yet. I think these files have slightly different goals.

Gah.

They're not supposed to fwiw.

I'll trust you here, but can you make sure that the code in Host.cpp is as up to date with all of this as you can make it? If nothing else Host.cpp should be a strict superset of this.

-eric

Diffusion mentioned this in rL307757: [X86] Sync ProcessorTypes and ProcessorSubtypes enums used by getHostCPUName….Jul 11 2017, 11:50 PM
craig.topper updated this revision to Diff 106143.Jul 11 2017, 11:55 PM

I've synced what I can of this into Host.cpp now. Host.cpp now has two feature variables now because just in matching libgcc we used 31 bits. The fall back CPU detection for Intel family 6 required 3 more bits. So I gave Host.cpp a second variable. Now getAvailableFeatures in Host.cpp returns both feature variables through outparams. I've changed getAvailableFeatures here to return its single feature variable as an outparam as well to keep them somewhat consistent.

craig.topper updated this revision to Diff 106144.Jul 11 2017, 11:58 PM

Found a mistake in my previous patch around getAvailableFeatures where I forgot to still update the Features variable that gets passed to the AMD and Intel CPU detection

asbirlea accepted this revision.Jul 12 2017, 9:29 AM

LGTM.
Thank you for the updates in Host.cpp too; the comments there are great for pointing future changes to libgcc/compiler-rt.

This revision is now accepted and ready to land.Jul 12 2017, 9:29 AM
Closed by commit rL307878: [compiler-rt][X86] Match the detection of cpu's for __cpu_model to the latest… (authored by ctopper). · Explain WhyJul 12 2017, 7:57 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
compiler-rt/
trunk/
lib/
builtins/
416 lines

Diff 106370

compiler-rt/trunk/lib/builtins/cpu_model.c

Show All 38 Lines
enum ProcessorVendors { enum ProcessorVendors {
VENDOR_INTEL = 1, VENDOR_INTEL = 1,
VENDOR_AMD, VENDOR_AMD,
VENDOR_OTHER, VENDOR_OTHER,
VENDOR_MAX VENDOR_MAX
}; };
enum ProcessorTypes { enum ProcessorTypes {
INTEL_ATOM = 1, INTEL_BONNELL = 1,
INTEL_CORE2, INTEL_CORE2,
INTEL_COREI7, INTEL_COREI7,
AMDFAM10H, AMDFAM10H,
AMDFAM15H, AMDFAM15H,
INTEL_i386, INTEL_SILVERMONT,
INTEL_i486, INTEL_KNL,
INTEL_PENTIUM, AMD_BTVER1,
INTEL_PENTIUM_PRO, AMD_BTVER2,
INTEL_PENTIUM_II,
INTEL_PENTIUM_III,
INTEL_PENTIUM_IV,
INTEL_PENTIUM_M,
INTEL_CORE_DUO,
INTEL_XEONPHI,
INTEL_X86_64,
INTEL_NOCONA,
INTEL_PRESCOTT,
AMD_i486,
AMDPENTIUM,
AMDATHLON,
AMDFAM14H,
AMDFAM16H,
AMDFAM17H, AMDFAM17H,
CPU_TYPE_MAX CPU_TYPE_MAX
}; };
enum ProcessorSubtypes { enum ProcessorSubtypes {
INTEL_COREI7_NEHALEM = 1, INTEL_COREI7_NEHALEM = 1,
INTEL_COREI7_WESTMERE, INTEL_COREI7_WESTMERE,
INTEL_COREI7_SANDYBRIDGE, INTEL_COREI7_SANDYBRIDGE,
AMDFAM10H_BARCELONA, AMDFAM10H_BARCELONA,
AMDFAM10H_SHANGHAI, AMDFAM10H_SHANGHAI,
AMDFAM10H_ISTANBUL, AMDFAM10H_ISTANBUL,
AMDFAM15H_BDVER1, AMDFAM15H_BDVER1,
AMDFAM15H_BDVER2, AMDFAM15H_BDVER2,
INTEL_PENTIUM_MMX, AMDFAM15H_BDVER3,
INTEL_CORE2_65, AMDFAM15H_BDVER4,
INTEL_CORE2_45, AMDFAM17H_ZNVER1,
INTEL_COREI7_IVYBRIDGE, INTEL_COREI7_IVYBRIDGE,
INTEL_COREI7_HASWELL, INTEL_COREI7_HASWELL,
INTEL_COREI7_BROADWELL, INTEL_COREI7_BROADWELL,
INTEL_COREI7_SKYLAKE, INTEL_COREI7_SKYLAKE,
INTEL_COREI7_SKYLAKE_AVX512, INTEL_COREI7_SKYLAKE_AVX512,
INTEL_ATOM_BONNELL,
INTEL_ATOM_SILVERMONT,
INTEL_KNIGHTS_LANDING,
AMDPENTIUM_K6,
AMDPENTIUM_K62,
AMDPENTIUM_K63,
AMDPENTIUM_GEODE,
AMDATHLON_TBIRD,
AMDATHLON_MP,
AMDATHLON_XP,
AMDATHLON_K8SSE3,
AMDATHLON_OPTERON,
AMDATHLON_FX,
AMDATHLON_64,
AMD_BTVER1,
AMD_BTVER2,
AMDFAM15H_BDVER3,
AMDFAM15H_BDVER4,
AMDFAM17H_ZNVER1,
CPU_SUBTYPE_MAX CPU_SUBTYPE_MAX
}; };
enum ProcessorFeatures { enum ProcessorFeatures {
FEATURE_CMOV = 0, FEATURE_CMOV = 0,
FEATURE_MMX, FEATURE_MMX,
FEATURE_POPCNT, FEATURE_POPCNT,
FEATURE_SSE, FEATURE_SSE,
FEATURE_SSE2, FEATURE_SSE2,
FEATURE_SSE3, FEATURE_SSE3,
FEATURE_SSSE3, FEATURE_SSSE3,
FEATURE_SSE4_1, FEATURE_SSE4_1,
FEATURE_SSE4_2, FEATURE_SSE4_2,
FEATURE_AVX, FEATURE_AVX,
FEATURE_AVX2, FEATURE_AVX2,
FEATURE_AVX512, FEATURE_SSE4_A,
FEATURE_AVX512SAVE, FEATURE_FMA4,
FEATURE_MOVBE, FEATURE_XOP,
FEATURE_ADX, FEATURE_FMA,
FEATURE_EM64T FEATURE_AVX512F,
FEATURE_BMI,
FEATURE_BMI2,
FEATURE_AES,
FEATURE_PCLMUL,
FEATURE_AVX512VL,
FEATURE_AVX512BW,
FEATURE_AVX512DQ,
FEATURE_AVX512CD,
FEATURE_AVX512ER,
FEATURE_AVX512PF,
FEATURE_AVX512VBMI,
FEATURE_AVX512IFMA,
FEATURE_AVX5124VNNIW,
FEATURE_AVX5124FMAPS,
FEATURE_AVX512VPOPCNTDQ
}; };
// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
// support. Consequently, for i386, the presence of CPUID is checked first // support. Consequently, for i386, the presence of CPUID is checked first
// via the corresponding eflags bit. // via the corresponding eflags bit.
static bool isCpuIdSupported() { static bool isCpuIdSupported() {
#if defined(__GNUC__) || defined(__clang__) #if defined(__GNUC__) || defined(__clang__)
▲ Show 20 Lines • Show All 155 Lines • ▼ Show 20 Lines
static void static void
getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
unsigned Brand_id, unsigned Features, unsigned Brand_id, unsigned Features,
unsigned *Type, unsigned *Subtype) { unsigned *Type, unsigned *Subtype) {
if (Brand_id != 0) if (Brand_id != 0)
return; return;
switch (Family) { switch (Family) {
case 3:
*Type = INTEL_i386;
break;
case 4:
switch (Model) {
case 0: // Intel486 DX processors
case 1: // Intel486 DX processors
case 2: // Intel486 SX processors
case 3: // Intel487 processors, IntelDX2 OverDrive processors,
// IntelDX2 processors
case 4: // Intel486 SL processor
case 5: // IntelSX2 processors
case 7: // Write-Back Enhanced IntelDX2 processors
case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
default:
*Type = INTEL_i486;
break;
}
break;
case 5:
switch (Model) {
case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
// Pentium processors (60, 66)
case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
// 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
// 150, 166, 200)
case 3: // Pentium OverDrive processors for Intel486 processor-based
// systems
*Type = INTEL_PENTIUM;
break;
case 4: // Pentium OverDrive processor with MMX technology for Pentium
// processor (75, 90, 100, 120, 133), Pentium processor with
// MMX technology (166, 200)
*Type = INTEL_PENTIUM;
*Subtype = INTEL_PENTIUM_MMX;
break;
default:
*Type = INTEL_PENTIUM;
break;
}
break;
case 6: case 6:
switch (Model) { switch (Model) {
case 0x01: // Pentium Pro processor
*Type = INTEL_PENTIUM_PRO;
break;
case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
// model 03
case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
// model 05, and Intel Celeron processor, model 05
case 0x06: // Celeron processor, model 06
*Type = INTEL_PENTIUM_II;
break;
case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
// processor, model 07
case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
// model 08, and Celeron processor, model 08
case 0x0a: // Pentium III Xeon processor, model 0Ah
case 0x0b: // Pentium III processor, model 0Bh
*Type = INTEL_PENTIUM_III;
break;
case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
// 0Dh. All processors are manufactured using the 90 nm process.
case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
// Integrated Processor with Intel QuickAssist Technology
*Type = INTEL_PENTIUM_M;
break;
case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
// 0Eh. All processors are manufactured using the 65 nm process.
*Type = INTEL_CORE_DUO;
break; // yonah
case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
// processor, Intel Core 2 Quad processor, Intel Core 2 Quad // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
// mobile processor, Intel Core 2 Extreme processor, Intel // mobile processor, Intel Core 2 Extreme processor, Intel
// Pentium Dual-Core processor, Intel Xeon processor, model // Pentium Dual-Core processor, Intel Xeon processor, model
// 0Fh. All processors are manufactured using the 65 nm process. // 0Fh. All processors are manufactured using the 65 nm process.
case 0x16: // Intel Celeron processor model 16h. All processors are case 0x16: // Intel Celeron processor model 16h. All processors are
// manufactured using the 65 nm process // manufactured using the 65 nm process
*Type = INTEL_CORE2; // "core2"
*Subtype = INTEL_CORE2_65;
break;
case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
// 17h. All processors are manufactured using the 45 nm process. // 17h. All processors are manufactured using the 45 nm process.
// //
// 45nm: Penryn , Wolfdale, Yorkfield (XE) // 45nm: Penryn , Wolfdale, Yorkfield (XE)
case 0x1d: // Intel Xeon processor MP. All processors are manufactured using case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
// the 45 nm process. // the 45 nm process.
*Type = INTEL_CORE2; // "penryn" *Type = INTEL_CORE2; // "penryn"
*Subtype = INTEL_CORE2_45;
break; break;
case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
// processors are manufactured using the 45 nm process. // processors are manufactured using the 45 nm process.
case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
// As found in a Summer 2010 model iMac. // As found in a Summer 2010 model iMac.
case 0x1f: case 0x1f:
case 0x2e: // Nehalem EX case 0x2e: // Nehalem EX
*Type = INTEL_COREI7; // "nehalem" *Type = INTEL_COREI7; // "nehalem"
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines case 0x55:
*Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
break; break;
case 0x1c: // Most 45 nm Intel Atom processors case 0x1c: // Most 45 nm Intel Atom processors
case 0x26: // 45 nm Atom Lincroft case 0x26: // 45 nm Atom Lincroft
case 0x27: // 32 nm Atom Medfield case 0x27: // 32 nm Atom Medfield
case 0x35: // 32 nm Atom Midview case 0x35: // 32 nm Atom Midview
case 0x36: // 32 nm Atom Midview case 0x36: // 32 nm Atom Midview
*Type = INTEL_ATOM; *Type = INTEL_BONNELL;
*Subtype = INTEL_ATOM_BONNELL;
break; // "bonnell" break; // "bonnell"
// Atom Silvermont codes from the Intel software optimization guide. // Atom Silvermont codes from the Intel software optimization guide.
case 0x37: case 0x37:
case 0x4a: case 0x4a:
case 0x4d: case 0x4d:
case 0x5a: case 0x5a:
case 0x5d: case 0x5d:
case 0x4c: // really airmont case 0x4c: // really airmont
*Type = INTEL_ATOM; *Type = INTEL_SILVERMONT;
*Subtype = INTEL_ATOM_SILVERMONT;
break; // "silvermont" break; // "silvermont"
case 0x57: case 0x57:
*Type = INTEL_XEONPHI; // knl *Type = INTEL_KNL; // knl
*Subtype = INTEL_KNIGHTS_LANDING;
break;
default: // Unknown family 6 CPU, try to guess.
if (Features & (1 << FEATURE_AVX512)) {
*Type = INTEL_XEONPHI; // knl
*Subtype = INTEL_KNIGHTS_LANDING;
break;
}
if (Features & (1 << FEATURE_ADX)) {
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_BROADWELL;
break;
}
if (Features & (1 << FEATURE_AVX2)) {
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_HASWELL;
break;
}
if (Features & (1 << FEATURE_AVX)) {
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_SANDYBRIDGE;
break;
}
if (Features & (1 << FEATURE_SSE4_2)) {
if (Features & (1 << FEATURE_MOVBE)) {
*Type = INTEL_ATOM;
*Subtype = INTEL_ATOM_SILVERMONT;
} else {
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_NEHALEM;
}
break;
}
if (Features & (1 << FEATURE_SSE4_1)) {
*Type = INTEL_CORE2; // "penryn"
*Subtype = INTEL_CORE2_45;
break;
}
if (Features & (1 << FEATURE_SSSE3)) {
if (Features & (1 << FEATURE_MOVBE)) {
*Type = INTEL_ATOM;
*Subtype = INTEL_ATOM_BONNELL; // "bonnell"
} else {
*Type = INTEL_CORE2; // "core2"
*Subtype = INTEL_CORE2_65;
}
break;
}
if (Features & (1 << FEATURE_EM64T)) {
*Type = INTEL_X86_64;
break; // x86-64
}
if (Features & (1 << FEATURE_SSE2)) {
*Type = INTEL_PENTIUM_M;
break;
}
if (Features & (1 << FEATURE_SSE)) {
*Type = INTEL_PENTIUM_III;
break;
}
if (Features & (1 << FEATURE_MMX)) {
*Type = INTEL_PENTIUM_II;
break;
}
*Type = INTEL_PENTIUM_PRO;
break;
}
break;
case 15: {
switch (Model) {
case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
// model 00h and manufactured using the 0.18 micron process.
case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
// processor MP, and Intel Celeron processor. All processors are
// model 01h and manufactured using the 0.18 micron process.
case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
// processor, and Mobile Intel Celeron processor. All processors
// are model 02h and manufactured using the 0.13 micron process.
*Type =
((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
break;
case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
// processor. All processors are model 03h and manufactured using
// the 90 nm process.
case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
// Pentium D processor, Intel Xeon processor, Intel Xeon
// processor MP, Intel Celeron D processor. All processors are
// model 04h and manufactured using the 90 nm process.
case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
// Extreme Edition, Intel Xeon processor, Intel Xeon processor
// MP, Intel Celeron D processor. All processors are model 06h
// and manufactured using the 65 nm process.
*Type =
((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT);
break; break;
default: default: // Unknown family 6 CPU.
*Type =
((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
break; break;
}
break; break;
} }
default: default:
break; /*"generic"*/ break; // Unknown.
} }
} }
static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
unsigned Features, unsigned *Type, unsigned Features, unsigned *Type,
unsigned *Subtype) { unsigned *Subtype) {
// FIXME: this poorly matches the generated SubtargetFeatureKV table. There // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
// appears to be no way to generate the wide variety of AMD-specific targets // appears to be no way to generate the wide variety of AMD-specific targets
// from the information returned from CPUID. // from the information returned from CPUID.
switch (Family) { switch (Family) {
case 4:
*Type = AMD_i486;
break;
case 5:
*Type = AMDPENTIUM;
switch (Model) {
case 6:
case 7:
*Subtype = AMDPENTIUM_K6;
break; // "k6"
case 8:
*Subtype = AMDPENTIUM_K62;
break; // "k6-2"
case 9:
case 13:
*Subtype = AMDPENTIUM_K63;
break; // "k6-3"
case 10:
*Subtype = AMDPENTIUM_GEODE;
break; // "geode"
}
break;
case 6:
*Type = AMDATHLON;
switch (Model) {
case 4:
*Subtype = AMDATHLON_TBIRD;
break; // "athlon-tbird"
case 6:
case 7:
case 8:
*Subtype = AMDATHLON_MP;
break; // "athlon-mp"
case 10:
*Subtype = AMDATHLON_XP;
break; // "athlon-xp"
}
break;
case 15:
*Type = AMDATHLON;
if (Features & (1 << FEATURE_SSE3)) {
*Subtype = AMDATHLON_K8SSE3;
break; // "k8-sse3"
}
switch (Model) {
case 1:
*Subtype = AMDATHLON_OPTERON;
break; // "opteron"
case 5:
*Subtype = AMDATHLON_FX;
break; // "athlon-fx"; also opteron
default:
*Subtype = AMDATHLON_64;
break; // "athlon64"
}
break;
case 16: case 16:
*Type = AMDFAM10H; // "amdfam10" *Type = AMDFAM10H; // "amdfam10"
switch (Model) { switch (Model) {
case 2: case 2:
*Subtype = AMDFAM10H_BARCELONA; *Subtype = AMDFAM10H_BARCELONA;
break; break;
case 4: case 4:
*Subtype = AMDFAM10H_SHANGHAI; *Subtype = AMDFAM10H_SHANGHAI;
break; break;
case 8: case 8:
*Subtype = AMDFAM10H_ISTANBUL; *Subtype = AMDFAM10H_ISTANBUL;
break; break;
} }
break; break;
case 20: case 20:
*Type = AMDFAM14H; *Type = AMD_BTVER1;
*Subtype = AMD_BTVER1;
break; // "btver1"; break; // "btver1";
case 21: case 21:
*Type = AMDFAM15H; *Type = AMDFAM15H;
if (Model >= 0x60 && Model <= 0x7f) { if (Model >= 0x60 && Model <= 0x7f) {
*Subtype = AMDFAM15H_BDVER4; *Subtype = AMDFAM15H_BDVER4;
break; // "bdver4"; 50h-6Fh: Excavator break; // "bdver4"; 60h-7Fh: Excavator
} }
if (Model >= 0x30 && Model <= 0x3f) { if (Model >= 0x30 && Model <= 0x3f) {
*Subtype = AMDFAM15H_BDVER3; *Subtype = AMDFAM15H_BDVER3;
break; // "bdver3"; 30h-3Fh: Steamroller break; // "bdver3"; 30h-3Fh: Steamroller
} }
if (Model >= 0x10 && Model <= 0x1f) { if (Model >= 0x10 && Model <= 0x1f) {
*Subtype = AMDFAM15H_BDVER2; *Subtype = AMDFAM15H_BDVER2;
break; // "bdver2"; 10h-1Fh: Piledriver break; // "bdver2"; 10h-1Fh: Piledriver
Show All 10 Lines case 23:
*Type = AMDFAM17H; *Type = AMDFAM17H;
*Subtype = AMDFAM17H_ZNVER1; *Subtype = AMDFAM17H_ZNVER1;
break; break;
default: default:
break; // "generic" break; // "generic"
} }
} }
static unsigned getAvailableFeatures(unsigned ECX, unsigned EDX, static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
unsigned MaxLeaf) { unsigned *FeaturesOut) {
unsigned Features = 0; unsigned Features = 0;
unsigned EAX, EBX; unsigned EAX, EBX;
Features |= (((EDX >> 23) & 1) << FEATURE_MMX);
Features |= (((EDX >> 25) & 1) << FEATURE_SSE); if ((EDX >> 15) & 1)
Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); Features |= 1 << FEATURE_CMOV;
Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); if ((EDX >> 23) & 1)
Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); Features |= 1 << FEATURE_MMX;
Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); if ((EDX >> 25) & 1)
Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); Features |= 1 << FEATURE_SSE;
Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); if ((EDX >> 26) & 1)
Features |= 1 << FEATURE_SSE2;
if ((ECX >> 0) & 1)
Features |= 1 << FEATURE_SSE3;
if ((ECX >> 1) & 1)
Features |= 1 << FEATURE_PCLMUL;
if ((ECX >> 9) & 1)
Features |= 1 << FEATURE_SSSE3;
if ((ECX >> 12) & 1)
Features |= 1 << FEATURE_FMA;
if ((ECX >> 19) & 1)
Features |= 1 << FEATURE_SSE4_1;
if ((ECX >> 20) & 1)
Features |= 1 << FEATURE_SSE4_2;
if ((ECX >> 23) & 1)
Features |= 1 << FEATURE_POPCNT;
if ((ECX >> 25) & 1)
Features |= 1 << FEATURE_AES;
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context // indicates that the AVX registers will be saved and restored on context
// switch, then we have full AVX support. // switch, then we have full AVX support.
const unsigned AVXBits = (1 << 27) | (1 << 28); const unsigned AVXBits = (1 << 27) | (1 << 28);
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
((EAX & 0x6) == 0x6); ((EAX & 0x6) == 0x6);
bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
if (HasAVX)
Features |= 1 << FEATURE_AVX;
bool HasLeaf7 = bool HasLeaf7 =
MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); if (HasLeaf7 && ((EBX >> 3) & 1))
bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); Features |= 1 << FEATURE_BMI;
Features |= (HasAVX << FEATURE_AVX); if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
Features |= (HasAVX2 << FEATURE_AVX2); Features |= 1 << FEATURE_AVX2;
Features |= (HasAVX512 << FEATURE_AVX512); if (HasLeaf7 && ((EBX >> 9) & 1))
Features |= (HasAVX512Save << FEATURE_AVX512SAVE); Features |= 1 << FEATURE_BMI2;
Features |= (HasADX << FEATURE_ADX); if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512F;
if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512DQ;
if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512IFMA;
if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512PF;
if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512ER;
if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512CD;
if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512BW;
if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512VL;
if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512VBMI;
if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX512VPOPCNTDQ;
if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX5124VNNIW;
if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
Features |= 1 << FEATURE_AVX5124FMAPS;
unsigned MaxExtLevel; unsigned MaxExtLevel;
getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
!getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
if (HasExtLeaf1) if (HasExtLeaf1 && ((ECX >> 6) & 1))
Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); Features |= 1 << FEATURE_SSE4_A;
if (HasExtLeaf1 && ((ECX >> 11) & 1))
Features |= 1 << FEATURE_XOP;
if (HasExtLeaf1 && ((ECX >> 16) & 1))
Features |= 1 << FEATURE_FMA4;
return Features; *FeaturesOut = Features;
} }
#if defined(HAVE_INIT_PRIORITY) #if defined(HAVE_INIT_PRIORITY)
#define CONSTRUCTOR_ATTRIBUTE __attribute__((__constructor__ 101)) #define CONSTRUCTOR_ATTRIBUTE __attribute__((__constructor__ 101))
#elif __has_attribute(__constructor__) #elif __has_attribute(__constructor__)
#define CONSTRUCTOR_ATTRIBUTE __attribute__((__constructor__)) #define CONSTRUCTOR_ATTRIBUTE __attribute__((__constructor__))
#else #else
// FIXME: For MSVC, we should make a function pointer global in .CRT$X?? so that // FIXME: For MSVC, we should make a function pointer global in .CRT$X?? so that
Show All 36 Lines if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) {
__cpu_model.__cpu_vendor = VENDOR_OTHER; __cpu_model.__cpu_vendor = VENDOR_OTHER;
return -1; return -1;
} }
getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
detectX86FamilyModel(EAX, &Family, &Model); detectX86FamilyModel(EAX, &Family, &Model);
Brand_id = EBX & 0xff; Brand_id = EBX & 0xff;
/* Find available features. */ /* Find available features. */
Features = getAvailableFeatures(ECX, EDX, MaxLeaf); getAvailableFeatures(ECX, EDX, MaxLeaf, &Features);
__cpu_model.__cpu_features[0] = Features; __cpu_model.__cpu_features[0] = Features;
if (Vendor == SIG_INTEL) { if (Vendor == SIG_INTEL) {
/* Get CPU type. */ /* Get CPU type. */
getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
&(__cpu_model.__cpu_type), &(__cpu_model.__cpu_type),
&(__cpu_model.__cpu_subtype)); &(__cpu_model.__cpu_subtype));
__cpu_model.__cpu_vendor = VENDOR_INTEL; __cpu_model.__cpu_vendor = VENDOR_INTEL;
Show All 17 Lines