Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT

[fpichet]

Summary

Do not assume little endian architecture in DAGCombiner::visitTRUNCATE and DAGCombiner::visitEXTRACT_VECTOR_ELT.
PR33682

[sdardis]

You should upload patches with more context i.e. git diff -U9999.

I'm seeing the reported issue with MIPS, here's a testcase, you may need to file the rough edges off.

It can go in test/CodeGen/Mips/pr33682.ll

; RUN: llc -march=mips -mcpu=mips32  < %s | FileCheck --check-prefixes=ALL,BE
; RUN: llc -march=mipsel -mcpu=mips32  < %s | FileCheck --check-prefixes=ALL,LE
  
; Verify visitTRUNCATE respects endianness when transforming truncates to extract vector element.

; ALL-LABEL: a:
; BE: lw $2, 4($4)
; LE: lw $2, 0($4) 
  
define i32 @a(<2 x i32> * %a) {
entry:
  %0 = load <2 x i32>, <2 x i32> * %a
  %1 = bitcast <2 x i32> %0 to i64
  %2 = trunc i64 %1 to i32
  ret i32 %2
}

[fpichet]

Added test case

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8377

I'm not sure this is generally correct - for example what about the (i16 trunc (i64 (bitcast v4i16:x))) case? Shouldn't the extracted big-endian index then be 3?

[fpichet]

Update patch taking into account vector size > 2
Also reuse existing isLE variable.

[RKSimon]

Cheers, does anyone have any further comments?

[sdardis]

2 quick things, summary could do with an update (as now there is a test case), but that can be done on commit.

The other is that the case you've highlighted @RKSimon should probably be added to the test case.

Thanks.

[RKSimon]

Waiting on the additional bug mentioned in PR33682

[fpichet]

This comment was removed by fpichet.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8377

I agree, I'll update the patch.

[fpichet]

Update patch with fix for endianness bug in visitEXTRACT_VECTOR_ELT.

[fpichet]

is it ok to commit now?

[RKSimon]

@sdardis any comments?

[sdardis]

LGTM. @RKSimon No more comments from me.

[RKSimon]

LGTM as well

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

   // Fold truncate of a bitcast of a vector to an extract of the low vector
   // element.
   //
-  // e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, 0
+  // e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, idx
   if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
     SDValue VecSrc = N0.getOperand(0);
     EVT SrcVT = VecSrc.getValueType();

       SDLoc SL(N);
 
       EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
+      unsigned Idx = DAG.getDataLayout().isBigEndian() ? 1 : 0;
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT,
-                         VecSrc, DAG.getConstant(0, SL, IdxVT));
+                         VecSrc, DAG.getConstant(Idx, SL, IdxVT));
     }
   }