Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT

[fpichet]

Summary

Do not assume little endian architecture in DAGCombiner::visitTRUNCATE and DAGCombiner::visitEXTRACT_VECTOR_ELT.
PR33682

[sdardis]

You should upload patches with more context i.e. git diff -U9999.

I'm seeing the reported issue with MIPS, here's a testcase, you may need to file the rough edges off.

It can go in test/CodeGen/Mips/pr33682.ll

; RUN: llc -march=mips -mcpu=mips32  < %s | FileCheck --check-prefixes=ALL,BE
; RUN: llc -march=mipsel -mcpu=mips32  < %s | FileCheck --check-prefixes=ALL,LE
  
; Verify visitTRUNCATE respects endianness when transforming truncates to extract vector element.

; ALL-LABEL: a:
; BE: lw $2, 4($4)
; LE: lw $2, 0($4) 
  
define i32 @a(<2 x i32> * %a) {
entry:
  %0 = load <2 x i32>, <2 x i32> * %a
  %1 = bitcast <2 x i32> %0 to i64
  %2 = trunc i64 %1 to i32
  ret i32 %2
}

[fpichet]

Added test case

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8377 ↗

(On Diff #105367)

I'm not sure this is generally correct - for example what about the (i16 trunc (i64 (bitcast v4i16:x))) case? Shouldn't the extracted big-endian index then be 3?

[fpichet]

Update patch taking into account vector size > 2
Also reuse existing isLE variable.

[RKSimon]

Cheers, does anyone have any further comments?

[sdardis]

2 quick things, summary could do with an update (as now there is a test case), but that can be done on commit.

The other is that the case you've highlighted @RKSimon should probably be added to the test case.

Thanks.

[RKSimon]

Waiting on the additional bug mentioned in PR33682

[fpichet]

This comment was removed by fpichet.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8377 ↗

(On Diff #105367)

I agree, I'll update the patch.

[fpichet]

Update patch with fix for endianness bug in visitEXTRACT_VECTOR_ELT.

[fpichet]

is it ok to commit now?

[RKSimon]

@sdardis any comments?

[sdardis]

LGTM. @RKSimon No more comments from me.

[RKSimon]

LGTM as well

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (NumDefs == 1) {
       }
       return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
     }
   }
 
   // Fold truncate of a bitcast of a vector to an extract of the low vector
   // element.
   //
-  // e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, 0
+  // e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, idx
   if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
     SDValue VecSrc = N0.getOperand(0);
     EVT SrcVT = VecSrc.getValueType();
     if (SrcVT.isVector() && SrcVT.getScalarType() == VT &&
         (!LegalOperations ||
          TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, SrcVT))) {
       SDLoc SL(N);
 
       EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
+      unsigned Idx = isLE ? 0 : SrcVT.getVectorNumElements() - 1;
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT,
-                         VecSrc, DAG.getConstant(0, SL, IdxVT));
+                         VecSrc, DAG.getConstant(Idx, SL, IdxVT));
     }
   }
 
   // Simplify the operands using demanded-bits information.
   if (!VT.isVector() &&
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
if (ConstEltNo &&
     // Sometimes build_vector's scalar input types do not match result type.
     if (NVT == InEltVT)
       return Elt;
 
     // TODO: It may be useful to truncate if free if the build_vector implicitly
     // converts.
   }
 
-  // extract_vector_elt (v2i32 (bitcast i64:x)), 0 -> i32 (trunc i64:x)
+  // extract_vector_elt (v2i32 (bitcast i64:x)), EltTrunc -> i32 (trunc i64:x)
+  bool isLE = DAG.getDataLayout().isLittleEndian();
+  unsigned EltTrunc = isLE ? 0 : VT.getVectorNumElements() - 1;
   if (ConstEltNo && InVec.getOpcode() == ISD::BITCAST && InVec.hasOneUse() &&
-      ConstEltNo->isNullValue() && VT.isInteger()) {
+      ConstEltNo->getZExtValue() == EltTrunc && VT.isInteger()) {
     SDValue BCSrc = InVec.getOperand(0);
     if (BCSrc.getValueType().isScalarInteger())
       return DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, BCSrc);
   }
 
   // extract_vector_elt (insert_vector_elt vec, val, idx), idx) -> val
   //
   // This only really matters if the index is non-constant since other combines

llvm/trunk/test/CodeGen/Mips/pr33682.ll

+; RUN: llc -march=mips -mcpu=mips32  < %s | FileCheck %s --check-prefixes=ALL,BE
+; RUN: llc -march=mipsel -mcpu=mips32  < %s | FileCheck %s --check-prefixes=ALL,LE
+
+; Verify visitTRUNCATE respects endianness when transforming trunc to insert_vector_elt.
+
+; ALL-LABEL: a:
+; BE: lw $2, 4($4)
+; LE: lw $2, 0($4)
+
+define i32 @a(<2 x i32> * %a) {
+entry:
+%0 = load <2 x i32>, <2 x i32> * %a
+%1 = bitcast <2 x i32> %0 to i64
+%2 = trunc i64 %1 to i32
+ret i32 %2
+}
+
+; ALL-LABEL: b:
+; BE: lw $2, 12($4)
+; LE: lw $2, 0($4)
+
+define i32 @b(<4 x i32> * %a) {
+entry:
+%0 = load <4 x i32>, <4 x i32> * %a
+%1 = bitcast <4 x i32> %0 to i128
+%2 = trunc i128 %1 to i32
+ret i32 %2
+}
+
+
+; Verify visitEXTRACT_VECTOR_ELT respects endianness when transforming extract_vector_elt to a trunc.
+
+; ALL-LABEL: c:
+; BE: lw $2, 0($4)
+; LE: lw $2, 0($4)
+
+define i32 @c(i64 * %a) {
+entry:
+%0 = load i64, i64 * %a
+%1 = bitcast i64 %0 to <2 x i32>
+%2 = extractelement <2 x i32> %1, i32 0
+ret i32 %2
+}
+
+; ALL-LABEL: d:
+; BE: lw $2, 4($4)
+; LE: lw $2, 4($4)
+
+define i32 @d(i64 * %a) {
+entry:
+%0 = load i64, i64 * %a
+%1 = bitcast i64 %0 to <2 x i32>
+%2 = extractelement <2 x i32> %1, i32 1
+ret i32 %2
+}