[AMDGPU] Fix regressions on mesa/clover with libclc due to address space

[yaxunl]

Summary

Currently AMDGPUTargetInfo does not initialize AddrSpaceMap in constructor, which causes regressions in mesa/clover with libclc.

This patch fixes that.

[yaxunl]

Fix typo.

[awatry]

FWIW, this looks ok to me.

Just as importantly, this fixes the address space mapping regressions for both r600 (BARTS) and GCN/AMDGPU (PITCAIRN) for me.

lib/Basic/Targets.cpp

 };
 
 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
 
 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
   return llvm::makeArrayRef(GCCRegNames);
 }
 
-static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = {
+static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = {
     4, // Default
     1, // opencl_global
     3, // opencl_local
     2, // opencl_constant
     4, // opencl_generic
     1, // cuda_device
     2, // cuda_constant
     3  // cuda_shared
 };
-static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = {
+static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = {
     0, // Default
     1, // opencl_global
     3, // opencl_local
     2, // opencl_constant
     0, // opencl_generic
     1, // cuda_device
     2, // cuda_constant
     3  // cuda_shared
 };
-static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = {
+static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = {
     0, // Default
     1, // opencl_global
     3, // opencl_local
     2, // opencl_constant
     4, // opencl_generic
     1, // cuda_device
     2, // cuda_constant
     3  // cuda_shared
 };
-static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = {
+static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = {
     5, // Default
     1, // opencl_global
     3, // opencl_local
     2, // opencl_constant
     0, // opencl_generic
     1, // cuda_device
     2, // cuda_constant
     3  // cuda_shared

     }
     auto IsGenericZero = isGenericZero(Triple);
     resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
                     (IsGenericZero ? DataLayoutStringSIGenericIsZero :
                         DataLayoutStringSIPrivateIsZero)
                     : DataLayoutStringR600);
     assert(DataLayout->getAllocaAddrSpace() == AS.Private);
 
+    setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D ||
+                       Triple.getEnvironment() == llvm::Triple::OpenCL ||
+                       Triple.getEnvironmentName() == "amdgizcl" ||
+                       !isAMDGCN(Triple));
     UseAddrSpaceMapMangling = true;
   }
 
-  void adjust(LangOptions &Opts) override {
-    TargetInfo::adjust(Opts);
+  void setAddressSpaceMap(bool DefaultIsGeneric) {
     if (isGenericZero(getTriple())) {
-      AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap
-                                 : &AMDGPUNonOpenCLGenericIsZeroMap;
+      AddrSpaceMap = DefaultIsGeneric ? &AMDGPUGenIsZeroDefIsPrivMap
+                                      : &AMDGPUGenIsZeroDefIsGenMap;
     } else {
-      AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap
-                                 : &AMDGPUNonOpenCLPrivateIsZeroMap;
+      AddrSpaceMap = DefaultIsGeneric ? &AMDGPUPrivIsZeroDefIsPrivMap
+                                      : &AMDGPUPrivIsZeroDefIsGenMap;
     }
   }
 
+  void adjust(LangOptions &Opts) override {
+    TargetInfo::adjust(Opts);
+    setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple()));
+  }
+
   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
     if (GPU <= GK_CAYMAN)
       return 32;
 
     if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
       return 32;
     }
     return 64;

test/CodeGenOpenCL/address-spaces.cl

 // RUN: %clang_cc1 %s -O0 -ffake-address-space-map -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,SPIR
 // RUN: %clang_cc1 %s -O0 -DCL20 -cl-std=CL2.0 -ffake-address-space-map -emit-llvm -o - | FileCheck %s --check-prefixes=CL20,CL20SPIR
 // RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa-opencl -emit-llvm -o - | FileCheck --check-prefixes=CHECK,SPIR %s
 // RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa-opencl -DCL20 -cl-std=CL2.0 -emit-llvm -o - | FileCheck %s --check-prefixes=CL20,CL20SPIR
 // RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa-amdgizcl -emit-llvm -o - | FileCheck %s -check-prefixes=CHECK,GIZ
 // RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa-amdgizcl -DCL20 -cl-std=CL2.0 -emit-llvm -o - | FileCheck %s --check-prefixes=CL20,CL20GIZ
+// RUN: %clang_cc1 %s -O0 -triple amdgcn-mesa-mesa3d -emit-llvm -o - | FileCheck --check-prefixes=CHECK,SPIR %s
+// RUN: %clang_cc1 %s -O0 -triple r600-- -emit-llvm -o - | FileCheck --check-prefixes=CHECK,SPIR %s
 
 // SPIR: i32* %arg
 // GIZ: i32 addrspace(5)* %arg
 void f__p(__private int *arg) {}
 
 // CHECK: i32 addrspace(1)* %arg
 void f__g(__global int *arg) {}