[AMDGPU] Add FP_CLASS to the add/setcc combine

[rampitec]

Summary

This is one of the nodes which also compile as v_cmp_*.

[arsenm]

LGTM. Should this also handle i1 and/or/xor?

[rampitec]

In D34485#787380, @arsenm wrote:

LGTM. Should this also handle i1 and/or/xor?

I'm not sure yet, I have to check the resulting code. Probably it should.

[rampitec]

In D34485#787393, @rampitec wrote:

In D34485#787380, @arsenm wrote:

LGTM. Should this also handle i1 and/or/xor?

I'm not sure yet, I have to check the resulting code. Probably it should.

Looks like it is beneficial for anything producing i1 and which is an instruction. I.e. not for arguments, constants etc.

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::performAddCombine(SDNode *N,
 
   Opc = RHS.getOpcode();
   switch (Opc) {
   default: break;
   case ISD::ZERO_EXTEND:
   case ISD::SIGN_EXTEND:
   case ISD::ANY_EXTEND: {
     auto Cond = RHS.getOperand(0);
-    if (Cond.getOpcode() != ISD::SETCC) break;
+    if (Cond.getOpcode() != ISD::SETCC &&
+        Cond.getOpcode() != AMDGPUISD::FP_CLASS)
+      break;
     SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1);
     SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond };
     Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
     return DAG.getNode(Opc, SL, VTList, Args);
   }
   case ISD::ADDCARRY: {
     // add x, (addcarry y, 0, cc) => addcarry x, y, cc
     auto C = dyn_cast<ConstantSDNode>(RHS.getOperand(1));

llvm/trunk/test/CodeGen/AMDGPU/combine-cond-add-sub.ll

bb:
   %cmp = icmp ugt i32 %x, %y
   %ext = sext i1 %cmp to i32
   %sub = sub i32 %v, %a
   %adde = add i32 %sub, %ext
   store i32 %adde, i32 addrspace(1)* %gep, align 4
   ret void
 }
 
+; GCN-LABEL: {{^}}zext_flclass:
+; GCN: v_cmp_class_f32_e{{32|64}} [[CC:[^,]+]],
+; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, 0, v{{[0-9]+}}, [[CC]]
+; GCN-NOT: v_cndmask
+
+define amdgpu_kernel void @zext_flclass(i32 addrspace(1)* nocapture %arg, float %x) {
+bb:
+  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
+  %v = load i32, i32 addrspace(1)* %gep, align 4
+  %cmp = tail call zeroext i1 @llvm.amdgcn.class.f32(float %x, i32 608)
+  %ext = zext i1 %cmp to i32
+  %add = add i32 %v, %ext
+  store i32 %add, i32 addrspace(1)* %gep, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}sext_flclass:
+; GCN: v_cmp_class_f32_e{{32|64}} [[CC:[^,]+]],
+; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, 0, [[CC]]
+; GCN-NOT: v_cndmask
+
+define amdgpu_kernel void @sext_flclass(i32 addrspace(1)* nocapture %arg, float %x) {
+bb:
+  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
+  %v = load i32, i32 addrspace(1)* %gep, align 4
+  %cmp = tail call zeroext i1 @llvm.amdgcn.class.f32(float %x, i32 608)
+  %ext = sext i1 %cmp to i32
+  %add = add i32 %v, %ext
+  store i32 %add, i32 addrspace(1)* %gep, align 4
+  ret void
+}
+
+declare i1 @llvm.amdgcn.class.f32(float, i32) #0
+
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 declare i32 @llvm.amdgcn.workitem.id.y() #0
 
 attributes #0 = { nounwind readnone speculatable }