This is an archive of the discontinued LLVM Phabricator instance.

Differential D33940

[Power9] Added support for the modsw, moduw, modsd, modud hardware instructions that are new to P9.
ClosedPublic

Authored by stefanp on Jun 6 2017, 6:59 AM.

Details

Reviewers
echristo
hfinkel
nemanjai
kbarton
syzaara
sfertile
inouehrs
lei
jtony
Commits
rG30a49d1a3d5b: [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.
rL305210: [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.
Summary

Note that if we need the result of both the divide and the modulo then we compute the modulo based on the result of the divide and not using the new hardware instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

stefanp created this revision.Jun 6 2017, 6:59 AM
stefanp updated this revision to Diff 101755.Jun 7 2017, 9:16 AM

I did not set the
let Predicates = [IsISA3_0] in {
correctly.
Fixed in this update.

jtony added inline comments.Jun 8 2017, 11:08 AM
lib/Target/PowerPC/PPCISelLowering.cpp
207 ↗(On Diff #101755)

SREM/UREM are actually not instructions, they are SDNode or operations, I think.

test/CodeGen/PowerPC/ppc64-P9-mod.ll
1 ↗(On Diff #101755)

Do we need to test Big-endian also?

nemanjai accepted this revision.Jun 8 2017, 10:07 PM

Aside from a few minor inline nits, LGTM. Please address the inline comments on the commit.

lib/Target/PowerPC/PPCISelLowering.cpp
207 ↗(On Diff #101755)

Sure. Technically. But I think the comment is fine.

8405 ↗(On Diff #101755)

Well, this isn't completely accurate. Probably more accurate to say something like
// Check for a DIV with the same operands as this REM.

8406 ↗(On Diff #101755)

The temporary isn't really needed here. The loop can just be
for (auto UI : Op.getOperand(1)->uses())

test/CodeGen/PowerPC/ppc64-P9-mod.ll
1 ↗(On Diff #101755)

Yes, I agree. The codegen (and therefore CHECK directives) don't need to change, but please add a RUN line with triple -mtriple=powerpc64-unknown-linux-gnu.

20 ↗(On Diff #101755)

For the actual MOD instructions you're checking for where the operands are parameters, please add the input registers to the CHECK directives since they're mandated by the ABI. They should look something like
; CHECK: modsw {{[0-9]+}}, 3, 4

I don't think we care to do that for the checks of existing code though (i.e. the dif/mul/sub).

This revision is now accepted and ready to land.Jun 8 2017, 10:07 PM
inouehrs added inline comments.Jun 8 2017, 10:18 PM
lib/Target/PowerPC/PPCISelLowering.cpp
208 ↗(On Diff #101755)

nit: harware -> hardware

test/CodeGen/PowerPC/ppc64-P9-mod.ll
1 ↗(On Diff #101755)

Also, it is better to add -verify-machineinstrs

stefanp updated this revision to Diff 102196.Jun 12 2017, 9:52 AM
stefanp marked 8 inline comments as done.

Fixed various comments from reviewers.

Closed by commit rL305210: [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions. (authored by jtony). · Explain WhyJun 12 2017, 10:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
PowerPC/
1 line
37 lines
10 lines
8 lines
test/
CodeGen/
PowerPC/
263 lines
MC/
Disassembler/
PowerPC/
12 lines
12 lines
PowerPC/
13 lines

Diff 102205

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

Show First 20 Lines • Show All 912 Lines • ▼ Show 20 Lines private:
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 198 Lines • ▼ Show 20 LinesPPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// We do not currently implement these libm ops for PowerPC. // We do not currently implement these libm ops for PowerPC.
setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
setOperationAction(ISD::FREM, MVT::ppcf128, Expand); setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
// PowerPC has no SREM/UREM instructions // PowerPC has no SREM/UREM instructions unless we are on P9
// On P9 we may use a hardware instruction to compute the remainder.
// The instructions are not legalized directly because in the cases where the
// result of both the remainder and the division is required it is more
// efficient to compute the remainder from the result of the division rather
// than use the remainder instruction.
if (Subtarget.isISA3_0()) {
setOperationAction(ISD::SREM, MVT::i32, Custom);
setOperationAction(ISD::UREM, MVT::i32, Custom);
setOperationAction(ISD::SREM, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
} else {
setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand); setOperationAction(ISD::UREM, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i64, Expand); setOperationAction(ISD::SREM, MVT::i64, Expand);
setOperationAction(ISD::UREM, MVT::i64, Expand); setOperationAction(ISD::UREM, MVT::i64, Expand);
}
// Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Expand); setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
setOperationAction(ISD::SDIVREM, MVT::i32, Expand); setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
▲ Show 20 Lines • Show All 8,169 Lines • ▼ Show 20 Lines return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
0); 0);
} }
default: default:
break; break;
} }
return SDValue(); return SDValue();
} }
SDValue PPCTargetLowering::LowerREM(SDValue Op, SelectionDAG &DAG) const {
// Check for a DIV with the same operands as this REM.
for (auto UI : Op.getOperand(1)->uses()) {
if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
(Op.getOpcode() == ISD::UREM && UI->getOpcode() == ISD::UDIV))
if (UI->getOperand(0) == Op.getOperand(0) &&
UI->getOperand(1) == Op.getOperand(1))
return SDValue();
}
return Op;
}
SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc dl(Op); SDLoc dl(Op);
// For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
// instructions), but for smaller types, we need to first extend up to v2i32 // instructions), but for smaller types, we need to first extend up to v2i32
// before doing going farther. // before doing going farther.
if (Op.getValueType() == MVT::v2i64) { if (Op.getValueType() == MVT::v2i64) {
EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
▲ Show 20 Lines • Show All 452 Lines • ▼ Show 20 LinesSDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::INTRINSIC_W_CHAIN: return SDValue(); case ISD::INTRINSIC_W_CHAIN: return SDValue();
// Frame & Return address. // Frame & Return address.
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::INTRINSIC_VOID: case ISD::INTRINSIC_VOID:
return LowerINTRINSIC_VOID(Op, DAG); return LowerINTRINSIC_VOID(Op, DAG);
case ISD::SREM:
case ISD::UREM:
return LowerREM(Op, DAG);
} }
} }
void PPCTargetLowering::ReplaceNodeResults(SDNode *N, void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc dl(N); SDLoc dl(N);
switch (N->getOpcode()) { switch (N->getOpcode()) {
▲ Show 20 Lines • Show All 4,358 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td

Show First 20 Lines • Show All 677 Lines • ▼ Show 20 Linesdefm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
[(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64;
defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divdu", "$rT, $rA, $rB", IIC_IntDivD, "divdu", "$rT, $rA, $rB", IIC_IntDivD,
[(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64;
def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divde $rT, $rA, $rB", IIC_IntDivD, "divde $rT, $rA, $rB", IIC_IntDivD,
[(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
isPPC64, Requires<[HasExtDiv]>; isPPC64, Requires<[HasExtDiv]>;
let Predicates = [IsISA3_0] in {
def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"modsd $rT, $rA, $rB", IIC_IntDivW,
[(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"modud $rT, $rA, $rB", IIC_IntDivW,
[(set i64:$rT, (urem i64:$rA, i64:$rB))]>;
}
let Defs = [CR0] in let Defs = [CR0] in
def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divde. $rT, $rA, $rB", IIC_IntDivD, "divde. $rT, $rA, $rB", IIC_IntDivD,
[]>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
isPPC64, Requires<[HasExtDiv]>; isPPC64, Requires<[HasExtDiv]>;
def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divdeu $rT, $rA, $rB", IIC_IntDivD, "divdeu $rT, $rA, $rB", IIC_IntDivD,
[(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
▲ Show 20 Lines • Show All 641 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Show First 20 Lines • Show All 2,538 Lines • ▼ Show 20 Lines def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
[(set f64:$rT, (PPCmffs))]>, [(set f64:$rT, (PPCmffs))]>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
let Defs = [CR1] in let Defs = [CR1] in
def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins), def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
"mffs. $rT", IIC_IntMFFS, []>, isDOT; "mffs. $rT", IIC_IntMFFS, []>, isDOT;
} }
let Predicates = [IsISA3_0] in {
def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
"modsw $rT, $rA, $rB", IIC_IntDivW,
[(set i32:$rT, (srem i32:$rA, i32:$rB))]>;
def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
"moduw $rT, $rA, $rB", IIC_IntDivW,
[(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
}
let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
// XO-Form instructions. Arithmetic instructions that can set overflow bit // XO-Form instructions. Arithmetic instructions that can set overflow bit
let isCommutable = 1 in let isCommutable = 1 in
defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
"add", "$rT, $rA, $rB", IIC_IntSimple, "add", "$rT, $rA, $rB", IIC_IntSimple,
[(set i32:$rT, (add i32:$rA, i32:$rB))]>; [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
▲ Show 20 Lines • Show All 1,885 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/ppc64-P9-mod.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not mod[us][wd]
@mod_resultsw = common local_unnamed_addr global i32 0, align 4
@mod_resultud = common local_unnamed_addr global i64 0, align 8
@div_resultsw = common local_unnamed_addr global i32 0, align 4
@mod_resultuw = common local_unnamed_addr global i32 0, align 4
@div_resultuw = common local_unnamed_addr global i32 0, align 4
@div_resultsd = common local_unnamed_addr global i64 0, align 8
@mod_resultsd = common local_unnamed_addr global i64 0, align 8
@div_resultud = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind
define void @modulo_sw(i32 signext %a, i32 signext %b) local_unnamed_addr {
entry:
%rem = srem i32 %a, %b
store i32 %rem, i32* @mod_resultsw, align 4
ret void
; CHECK-LABEL: modulo_sw
; CHECK: modsw {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_sw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @modulo_uw(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr {
entry:
%rem = urem i32 %a, %b
ret i32 %rem
; CHECK-LABEL: modulo_uw
; CHECK: moduw {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_uw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @modulo_sd(i64 %a, i64 %b) local_unnamed_addr {
entry:
%rem = srem i64 %a, %b
ret i64 %rem
; CHECK-LABEL: modulo_sd
; CHECK: modsd {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_sd
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_ud(i64 %a, i64 %b) local_unnamed_addr {
entry:
%rem = urem i64 %a, %b
store i64 %rem, i64* @mod_resultud, align 8
ret void
; CHECK-LABEL: modulo_ud
; CHECK: modud {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_ud
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_div_sw(i32 signext %a, i32 signext %b) local_unnamed_addr {
entry:
%rem = srem i32 %a, %b
store i32 %rem, i32* @mod_resultsw, align 4
%div = sdiv i32 %a, %b
store i32 %div, i32* @div_resultsw, align 4
ret void
; CHECK-LABEL: modulo_div_sw
; CHECK-NOT: modsw
; CHECK: div
; CHECK-NOT: modsw
; CHECK: mull
; CHECK-NOT: modsw
; CHECK: sub
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_div_sw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_div_abc_sw(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr {
entry:
%rem = srem i32 %a, %c
store i32 %rem, i32* @mod_resultsw, align 4
%div = sdiv i32 %b, %c
store i32 %div, i32* @div_resultsw, align 4
ret void
; CHECK-LABEL: modulo_div_abc_sw
; CHECK: modsw {{[0-9]+}}, 3, 5
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_div_abc_sw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_div_uw(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr {
entry:
%rem = urem i32 %a, %b
store i32 %rem, i32* @mod_resultuw, align 4
%div = udiv i32 %a, %b
store i32 %div, i32* @div_resultuw, align 4
ret void
; CHECK-LABEL: modulo_div_uw
; CHECK-NOT: modsw
; CHECK: div
; CHECK-NOT: modsw
; CHECK: mull
; CHECK-NOT: modsw
; CHECK: sub
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_div_uw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_div_swuw(i32 signext %a, i32 signext %b) local_unnamed_addr {
entry:
%rem = srem i32 %a, %b
store i32 %rem, i32* @mod_resultsw, align 4
%div = udiv i32 %a, %b
store i32 %div, i32* @div_resultsw, align 4
ret void
; CHECK-LABEL: modulo_div_swuw
; CHECK: modsw {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_div_swuw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_div_udsd(i64 %a, i64 %b) local_unnamed_addr {
entry:
%rem = urem i64 %a, %b
store i64 %rem, i64* @mod_resultud, align 8
%div = sdiv i64 %a, %b
store i64 %div, i64* @div_resultsd, align 8
ret void
; CHECK-LABEL: modulo_div_udsd
; CHECK: modud {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_div_udsd
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
define void @modulo_const32_sw(i32 signext %a) local_unnamed_addr {
entry:
%rem = srem i32 %a, 32
store i32 %rem, i32* @mod_resultsw, align 4
ret void
; CHECK-LABEL: modulo_const32_sw
; CHECK-NOT: modsw
; CHECK: srawi
; CHECK-NOT: modsw
; CHECK: addze
; CHECK-NOT: modsw
; CHECK: slwi
; CHECK-NOT: modsw
; CHECK: subf
; CHECK-NOT: modsw
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_const32_sw
; CHECK-PWR8: srawi
; CHECK-PWR8: addze
; CHECK-PWR8: slwi
; CHECK-PWR8: subf
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @modulo_const3_sw(i32 signext %a) local_unnamed_addr {
entry:
%rem = srem i32 %a, 3
ret i32 %rem
; CHECK-LABEL: modulo_const3_sw
; CHECK-NOT: modsw
; CHECK: mull
; CHECK-NOT: modsw
; CHECK: sub
; CHECK-NOT: modsw
; CHECK: blr
; CHECK-PWR8-LABEL: modulo_const3_sw
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @const2_modulo_sw(i32 signext %a) local_unnamed_addr {
entry:
%rem = srem i32 2, %a
ret i32 %rem
; CHECK-LABEL: const2_modulo_sw
; CHECK: modsw {{[0-9]+}}, {{[0-9]+}}, 3
; CHECK: blr
; CHECK-PWR8-LABEL: const2_modulo_sw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}
; Function Attrs: norecurse nounwind
; FIXME On power 9 this test will still produce modsw because the divide is in
; a different block than the remainder. Due to the nature of the SDAG we cannot
; see the div in the other block.
define void @blocks_modulo_div_sw(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr {
entry:
%div = sdiv i32 %a, %b
store i32 %div, i32* @div_resultsw, align 4
%cmp = icmp sgt i32 %c, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%rem = srem i32 %a, %b
store i32 %rem, i32* @mod_resultsw, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
; CHECK-LABEL: blocks_modulo_div_sw
; CHECK: div
; CHECK: modsw {{[0-9]+}}, 3, 4
; CHECK: blr
; CHECK-PWR8-LABEL: blocks_modulo_div_sw
; CHECK-PWR8: div
; CHECK-PWR8: mull
; CHECK-PWR8: sub
; CHECK-PWR8: blr
}

llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

Show First 20 Lines • Show All 346 Lines • ▼ Show 20 Lines
0x7c 0x43 0x23 0x57 0x7c 0x43 0x23 0x57
# CHECK: divweu 2, 3, 4 # CHECK: divweu 2, 3, 4
0x7c 0x43 0x23 0x16 0x7c 0x43 0x23 0x16
# CHECK: divweu. 2, 3, 4 # CHECK: divweu. 2, 3, 4
0x7c 0x43 0x23 0x17 0x7c 0x43 0x23 0x17
# CHECK: modsw 2, 3, 4
0x7c 0x43 0x26 0x16
# CHECK: moduw 2, 3, 4
0x7c 0x43 0x22 0x16
# CHECK: modsd 2, 3, 4
0x7c 0x43 0x26 0x12
# CHECK: modud 2, 3, 4
0x7c 0x43 0x22 0x12
# CHECK: mulld 2, 3, 4 # CHECK: mulld 2, 3, 4
0x7c 0x43 0x21 0xd2 0x7c 0x43 0x21 0xd2
# CHECK: mulld. 2, 3, 4 # CHECK: mulld. 2, 3, 4
0x7c 0x43 0x21 0xd3 0x7c 0x43 0x21 0xd3
# CHECK: mulhd 2, 3, 4 # CHECK: mulhd 2, 3, 4
0x7c 0x43 0x20 0x92 0x7c 0x43 0x20 0x92
▲ Show 20 Lines • Show All 348 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

Show First 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
0x57 0x23 0x43 0x7c 0x57 0x23 0x43 0x7c
# CHECK: divweu 2, 3, 4 # CHECK: divweu 2, 3, 4
0x16 0x23 0x43 0x7c 0x16 0x23 0x43 0x7c
# CHECK: divweu. 2, 3, 4 # CHECK: divweu. 2, 3, 4
0x17 0x23 0x43 0x7c 0x17 0x23 0x43 0x7c
# CHECK: modsw 2, 3, 4
0x16 0x26 0x43 0x7c
# CHECK: moduw 2, 3, 4
0x16 0x22 0x43 0x7c
# CHECK: modsd 2, 3, 4
0x12 0x26 0x43 0x7c
# CHECK: modud 2, 3, 4
0x12 0x22 0x43 0x7c
# CHECK: mulld 2, 3, 4 # CHECK: mulld 2, 3, 4
0xd2 0x21 0x43 0x7c 0xd2 0x21 0x43 0x7c
# CHECK: mulld. 2, 3, 4 # CHECK: mulld. 2, 3, 4
0xd3 0x21 0x43 0x7c 0xd3 0x21 0x43 0x7c
# CHECK: mulhd 2, 3, 4 # CHECK: mulhd 2, 3, 4
0x92 0x20 0x43 0x7c 0x92 0x20 0x43 0x7c
▲ Show 20 Lines • Show All 305 Lines • Show Last 20 Lines

llvm/trunk/test/MC/PowerPC/ppc64-encoding.s

Show First 20 Lines • Show All 487 Lines • ▼ Show 20 Lines
# CHECK-LE: divweu 2, 3, 4 # encoding: [0x16,0x23,0x43,0x7c] # CHECK-LE: divweu 2, 3, 4 # encoding: [0x16,0x23,0x43,0x7c]
divweu 2, 3, 4 divweu 2, 3, 4
# CHECK-BE: divweu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x17] # CHECK-BE: divweu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x17]
# CHECK-LE: divweu. 2, 3, 4 # encoding: [0x17,0x23,0x43,0x7c] # CHECK-LE: divweu. 2, 3, 4 # encoding: [0x17,0x23,0x43,0x7c]
divweu. 2, 3, 4 divweu. 2, 3, 4
# FIXME: divweuo 2, 3, 4 # FIXME: divweuo 2, 3, 4
# FIXME: divweuo. 2, 3, 4 # FIXME: divweuo. 2, 3, 4
# CHECK-BE: modsw 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x16]
# CHECK-LE: modsw 2, 3, 4 # encoding: [0x16,0x26,0x43,0x7c]
modsw 2, 3, 4
# CHECK-BE: moduw 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x16]
# CHECK-LE: moduw 2, 3, 4 # encoding: [0x16,0x22,0x43,0x7c]
moduw 2, 3, 4
# CHECK-BE: modsd 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x12]
# CHECK-LE: modsd 2, 3, 4 # encoding: [0x12,0x26,0x43,0x7c]
modsd 2, 3, 4
# CHECK-BE: modud 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x12]
# CHECK-LE: modud 2, 3, 4 # encoding: [0x12,0x22,0x43,0x7c]
modud 2, 3, 4
# CHECK-BE: mulld 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd2] # CHECK-BE: mulld 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd2]
# CHECK-LE: mulld 2, 3, 4 # encoding: [0xd2,0x21,0x43,0x7c] # CHECK-LE: mulld 2, 3, 4 # encoding: [0xd2,0x21,0x43,0x7c]
mulld 2, 3, 4 mulld 2, 3, 4
# CHECK-BE: mulld. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd3] # CHECK-BE: mulld. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd3]
# CHECK-LE: mulld. 2, 3, 4 # encoding: [0xd3,0x21,0x43,0x7c] # CHECK-LE: mulld. 2, 3, 4 # encoding: [0xd3,0x21,0x43,0x7c]
mulld. 2, 3, 4 mulld. 2, 3, 4
# FIXME: mulldo 2, 3, 4 # FIXME: mulldo 2, 3, 4
# FIXME: mulldo. 2, 3, 4 # FIXME: mulldo. 2, 3, 4
▲ Show 20 Lines • Show All 443 Lines • Show Last 20 Lines