AMDGPU: Remove deprecated and unused elf definitions

[kzhuravl]

Ping.

[t-tye]

LGTM

llvm/trunk/include/llvm/Support/ELF.h

enum : unsigned {
 
   // Address size to be inferred from section entry size.
   SHF_MIPS_ADDR = 0x40000000,
 
   // Section data is string data by default.
   SHF_MIPS_STRING = 0x80000000,
 
   // Make code section unreadable when in execute-only mode
-  SHF_ARM_PURECODE = 0x20000000,
-
-  SHF_AMDGPU_HSA_GLOBAL = 0x00100000,
-  SHF_AMDGPU_HSA_READONLY = 0x00200000,
-  SHF_AMDGPU_HSA_CODE = 0x00400000,
-  SHF_AMDGPU_HSA_AGENT = 0x00800000
+  SHF_ARM_PURECODE = 0x20000000
 };
 
 // Section Group Flags
 enum : unsigned {
   GRP_COMDAT = 0x1,
   GRP_MASKOS = 0x0ff00000,
   GRP_MASKPROC = 0xf0000000
 };
enum {
   STT_TLS = 6,        // Thread local data object
   STT_GNU_IFUNC = 10, // GNU indirect function
   STT_LOOS = 10,      // Lowest operating system-specific symbol type
   STT_HIOS = 12,      // Highest operating system-specific symbol type
   STT_LOPROC = 13,    // Lowest processor-specific symbol type
   STT_HIPROC = 15,    // Highest processor-specific symbol type
 
   // AMDGPU symbol types
-  STT_AMDGPU_HSA_KERNEL = 10,
-  STT_AMDGPU_HSA_INDIRECT_FUNCTION = 11,
-  STT_AMDGPU_HSA_METADATA = 12
+  STT_AMDGPU_HSA_KERNEL = 10
 };
 
 enum {
   STV_DEFAULT = 0,  // Visibility is specified by binding type
   STV_INTERNAL = 1, // Defined by processor supplements
   STV_HIDDEN = 2,   // Not visible to other components
   STV_PROTECTED = 3 // Visible in other components but not preemptable
 };
enum {
   PT_ARM_UNWIND = 0x70000001,
 
   // MIPS program header types.
   PT_MIPS_REGINFO = 0x70000000,  // Register usage information.
   PT_MIPS_RTPROC = 0x70000001,   // Runtime procedure table.
   PT_MIPS_OPTIONS = 0x70000002,  // Options segment.
   PT_MIPS_ABIFLAGS = 0x70000003, // Abiflags segment.
 
-  // AMDGPU program header types.
-  PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM = 0x60000000,
-  PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT = 0x60000001,
-  PT_AMDGPU_HSA_LOAD_READONLY_AGENT = 0x60000002,
-  PT_AMDGPU_HSA_LOAD_CODE_AGENT = 0x60000003,
-
   // WebAssembly program header types.
   PT_WEBASSEMBLY_FUNCTIONS = PT_LOPROC + 0, // Function definitions.
 };
 
 // Segment flag bits.
 enum : unsigned {
   PF_X = 1,                // Execute
   PF_W = 2,                // Write

llvm/trunk/lib/ObjectYAML/ELFYAML.cpp

#define BCase(X) IO.bitSetCase(Value, #X, ELF::X)
   BCase(SHF_LINK_ORDER);
   BCase(SHF_OS_NONCONFORMING);
   BCase(SHF_GROUP);
   BCase(SHF_TLS);
   switch (Object->Header.Machine) {
   case ELF::EM_ARM:
     BCase(SHF_ARM_PURECODE);
     break;
-  case ELF::EM_AMDGPU:
-    BCase(SHF_AMDGPU_HSA_GLOBAL);
-    BCase(SHF_AMDGPU_HSA_READONLY);
-    BCase(SHF_AMDGPU_HSA_CODE);
-    BCase(SHF_AMDGPU_HSA_AGENT);
-    break;
   case ELF::EM_HEXAGON:
     BCase(SHF_HEX_GPREL);
     break;
   case ELF::EM_MIPS:
     BCase(SHF_MIPS_NODUPES);
     BCase(SHF_MIPS_NAMES);
     BCase(SHF_MIPS_LOCAL);
     BCase(SHF_MIPS_NOSTRIP);

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 private:
   bool ParseAsAbsoluteExpression(uint32_t &Ret);
   bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
   bool ParseDirectiveHSACodeObjectVersion();
   bool ParseDirectiveHSACodeObjectISA();
   bool ParseDirectiveCodeObjectMetadata();
   bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
   bool ParseDirectiveAMDKernelCodeT();
-  bool ParseSectionDirectiveHSAText();
   bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
   bool ParseDirectiveAMDGPUHsaKernel();
-  bool ParseDirectiveAMDGPUHsaModuleGlobal();
-  bool ParseDirectiveAMDGPUHsaProgramGlobal();
-  bool ParseSectionDirectiveHSADataGlobalAgent();
-  bool ParseSectionDirectiveHSADataGlobalProgram();
-  bool ParseSectionDirectiveHSARodataReadonlyAgent();
   bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
                              RegisterKind RegKind, unsigned Reg1,
                              unsigned RegNum);
   bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
                            unsigned& RegNum, unsigned& RegWidth,
                            unsigned *DwordRegIndex);
   void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
                     bool IsAtomic, bool IsAtomicReturn);
if (ParseAMDKernelCodeTValue(ID, Header))
       return true;
   }
 
   getTargetStreamer().EmitAMDKernelCodeT(Header);
 
   return false;
 }
 
-bool AMDGPUAsmParser::ParseSectionDirectiveHSAText() {
-  getParser().getStreamer().SwitchSection(
-      AMDGPU::getHSATextSection(getContext()));
-  return false;
-}
-
 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
   if (getLexer().isNot(AsmToken::Identifier))
     return TokError("expected symbol name");
 
   StringRef KernelName = Parser.getTok().getString();
 
   getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
                                            ELF::STT_AMDGPU_HSA_KERNEL);
   Lex();
   KernelScope.initialize(getContext());
   return false;
 }
 
-bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaModuleGlobal() {
-  if (getLexer().isNot(AsmToken::Identifier))
-    return TokError("expected symbol name");
-
-  StringRef GlobalName = Parser.getTok().getIdentifier();
-
-  getTargetStreamer().EmitAMDGPUHsaModuleScopeGlobal(GlobalName);
-  Lex();
-  return false;
-}
-
-bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaProgramGlobal() {
-  if (getLexer().isNot(AsmToken::Identifier))
-    return TokError("expected symbol name");
-
-  StringRef GlobalName = Parser.getTok().getIdentifier();
-
-  getTargetStreamer().EmitAMDGPUHsaProgramScopeGlobal(GlobalName);
-  Lex();
-  return false;
-}
-
-bool AMDGPUAsmParser::ParseSectionDirectiveHSADataGlobalAgent() {
-  getParser().getStreamer().SwitchSection(
-      AMDGPU::getHSADataGlobalAgentSection(getContext()));
-  return false;
-}
-
-bool AMDGPUAsmParser::ParseSectionDirectiveHSADataGlobalProgram() {
-  getParser().getStreamer().SwitchSection(
-      AMDGPU::getHSADataGlobalProgramSection(getContext()));
-  return false;
-}
-
-bool AMDGPUAsmParser::ParseSectionDirectiveHSARodataReadonlyAgent() {
-  getParser().getStreamer().SwitchSection(
-      AMDGPU::getHSARodataReadonlyAgentSection(getContext()));
-  return false;
-}
-
 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
   StringRef IDVal = DirectiveID.getString();
 
   if (IDVal == ".hsa_code_object_version")
     return ParseDirectiveHSACodeObjectVersion();
 
   if (IDVal == ".hsa_code_object_isa")
     return ParseDirectiveHSACodeObjectISA();
 
   if (IDVal == AMDGPU::CodeObject::MetadataAssemblerDirectiveBegin)
     return ParseDirectiveCodeObjectMetadata();
 
   if (IDVal == ".amd_kernel_code_t")
     return ParseDirectiveAMDKernelCodeT();
 
-  if (IDVal == ".hsatext")
-    return ParseSectionDirectiveHSAText();
-
   if (IDVal == ".amdgpu_hsa_kernel")
     return ParseDirectiveAMDGPUHsaKernel();
 
-  if (IDVal == ".amdgpu_hsa_module_global")
-    return ParseDirectiveAMDGPUHsaModuleGlobal();
-
-  if (IDVal == ".amdgpu_hsa_program_global")
-    return ParseDirectiveAMDGPUHsaProgramGlobal();
-
-  if (IDVal == ".hsadata_global_agent")
-    return ParseSectionDirectiveHSADataGlobalAgent();
-
-  if (IDVal == ".hsadata_global_program")
-    return ParseSectionDirectiveHSADataGlobalProgram();
-
-  if (IDVal == ".hsarodata_readonly_agent")
-    return ParseSectionDirectiveHSARodataReadonlyAgent();
-
   return true;
 }
 
 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
                                            unsigned RegNo) const {
   if (isCI())
     return true;
 

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                              uint32_t Stepping,
                                              StringRef VendorName,
                                              StringRef ArchName) = 0;
 
   virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) = 0;
 
   virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) = 0;
 
-  virtual void EmitAMDGPUHsaModuleScopeGlobal(StringRef GlobalName) = 0;
-
-  virtual void EmitAMDGPUHsaProgramScopeGlobal(StringRef GlobalName) = 0;
-
   virtual void EmitStartOfCodeObjectMetadata(const Module &Mod);
 
   virtual void EmitKernelCodeObjectMetadata(
       const Function &Func, const amd_kernel_code_t &KernelCode);
 
   virtual void EmitEndOfCodeObjectMetadata();
 
   /// \returns True on success, false on failure.
public:
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
-  void EmitAMDGPUHsaModuleScopeGlobal(StringRef GlobalName) override;
-
-  void EmitAMDGPUHsaProgramScopeGlobal(StringRef GlobalName) override;
-
   /// \returns True on success, false on failure.
   bool EmitCodeObjectMetadata(StringRef YamlString) override;
 };
 
 class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
   MCStreamer &Streamer;
 
   void EmitAMDGPUNote(const MCExpr *DescSize,
public:
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
-  void EmitAMDGPUHsaModuleScopeGlobal(StringRef GlobalName) override;
-
-  void EmitAMDGPUHsaProgramScopeGlobal(StringRef GlobalName) override;
-
   /// \returns True on success, false on failure.
   bool EmitCodeObjectMetadata(StringRef YamlString) override;
 };
 
 }
 #endif

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
   switch (Type) {
     default: llvm_unreachable("Invalid AMDGPU symbol type");
     case ELF::STT_AMDGPU_HSA_KERNEL:
       OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
       break;
   }
 }
 
-void AMDGPUTargetAsmStreamer::EmitAMDGPUHsaModuleScopeGlobal(
-    StringRef GlobalName) {
-  OS << "\t.amdgpu_hsa_module_global " << GlobalName << '\n';
-}
-
-void AMDGPUTargetAsmStreamer::EmitAMDGPUHsaProgramScopeGlobal(
-    StringRef GlobalName) {
-  OS << "\t.amdgpu_hsa_program_global " << GlobalName << '\n';
-}
-
 bool AMDGPUTargetAsmStreamer::EmitCodeObjectMetadata(StringRef YamlString) {
   auto VerifiedYamlString = CodeObjectMetadataStreamer.toYamlString(YamlString);
   if (!VerifiedYamlString)
     return false;
 
   OS << '\t' << AMDGPU::CodeObject::MetadataAssemblerDirectiveBegin << '\n';
   OS << VerifiedYamlString.get();
   OS << '\t' << AMDGPU::CodeObject::MetadataAssemblerDirectiveEnd << '\n';

 
 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
                                                    unsigned Type) {
   MCSymbolELF *Symbol = cast<MCSymbolELF>(
       getStreamer().getContext().getOrCreateSymbol(SymbolName));
   Symbol->setType(ELF::STT_AMDGPU_HSA_KERNEL);
 }
 
-void AMDGPUTargetELFStreamer::EmitAMDGPUHsaModuleScopeGlobal(
-    StringRef GlobalName) {
-
-  MCSymbolELF *Symbol = cast<MCSymbolELF>(
-      getStreamer().getContext().getOrCreateSymbol(GlobalName));
-  Symbol->setType(ELF::STT_OBJECT);
-  Symbol->setBinding(ELF::STB_LOCAL);
-}
-
-void AMDGPUTargetELFStreamer::EmitAMDGPUHsaProgramScopeGlobal(
-    StringRef GlobalName) {
-
-  MCSymbolELF *Symbol = cast<MCSymbolELF>(
-      getStreamer().getContext().getOrCreateSymbol(GlobalName));
-  Symbol->setType(ELF::STT_OBJECT);
-  Symbol->setBinding(ELF::STB_GLOBAL);
-}
-
 bool AMDGPUTargetELFStreamer::EmitCodeObjectMetadata(StringRef YamlString) {
   auto VerifiedYamlString = CodeObjectMetadataStreamer.toYamlString(YamlString);
   if (!VerifiedYamlString)
     return false;
 
   // Create two labels to mark the beginning and end of the desc field
   // and a MCExpr to calculate the size of the desc field.
   auto &Context = getContext();

llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 
 } // end namespace IsaInfo
 
 LLVM_READONLY
 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
 
 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
                                const FeatureBitset &Features);
-MCSection *getHSATextSection(MCContext &Ctx);
-
-MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
-
-MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
-
-MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
 
 bool isGroupSegment(const GlobalValue *GV, AMDGPUAS AS);
 bool isGlobalSegment(const GlobalValue *GV, AMDGPUAS AS);
 bool isReadOnlySegment(const GlobalValue *GV, AMDGPUAS AS);
 
 /// \returns True if constants should be emitted to .text section for given
 /// target triple \p TT, false otherwise.
 bool shouldEmitConstantsToTextSection(const Triple &TT);

llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
 
   // These alignment values are specified in powers of two, so alignment =
   // 2^n.  The minimum alignment is 2^4 = 16.
   Header.kernarg_segment_alignment = 4;
   Header.group_segment_alignment = 4;
   Header.private_segment_alignment = 4;
 }
 
-MCSection *getHSATextSection(MCContext &Ctx) {
-  return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
-                           ELF::SHF_ALLOC | ELF::SHF_WRITE |
-                           ELF::SHF_EXECINSTR |
-                           ELF::SHF_AMDGPU_HSA_AGENT |
-                           ELF::SHF_AMDGPU_HSA_CODE);
-}
-
-MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
-  return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
-                           ELF::SHF_ALLOC | ELF::SHF_WRITE |
-                           ELF::SHF_AMDGPU_HSA_GLOBAL |
-                           ELF::SHF_AMDGPU_HSA_AGENT);
-}
-
-MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
-  return  Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
-                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
-                            ELF::SHF_AMDGPU_HSA_GLOBAL);
-}
-
-MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx) {
-  return Ctx.getELFSection(".hsarodata_readonly_agent", ELF::SHT_PROGBITS,
-                           ELF::SHF_ALLOC | ELF::SHF_AMDGPU_HSA_READONLY |
-                           ELF::SHF_AMDGPU_HSA_AGENT);
-}
-
 bool isGroupSegment(const GlobalValue *GV, AMDGPUAS AS) {
   return GV->getType()->getAddressSpace() == AS.LOCAL_ADDRESS;
 }
 
 bool isGlobalSegment(const GlobalValue *GV, AMDGPUAS AS) {
   return GV->getType()->getAddressSpace() == AS.GLOBAL_ADDRESS;
 }
 

llvm/trunk/test/Object/AMDGPU/elf-definitions.yaml

 # RUN: yaml2obj %s > %t.o
 # RUN: llvm-readobj -s -file-headers %t.o | FileCheck %s
 
 # CHECK: Format: ELF64-amdgpu-hsacobj
 # CHECK: Arch: amdgcn
-# CHECK:  Machine: EM_AMDGPU (0xE0)
-# CHECK: Sections [
-# CHECK: Section {
-# CHECK: Name: .shf_amdgpu
-# CHECK: Flags [ (0xF00000)
-# CHECK: SHF_AMDGPU_HSA_AGENT (0x800000)
-# CHECK: SHF_AMDGPU_HSA_CODE (0x400000)
-# CHECK: SHF_AMDGPU_HSA_GLOBAL (0x100000)
-# CHECK: SHF_AMDGPU_HSA_READONLY (0x200000)
+# CHECK: ElfHeader {
+# CHECK:   Ident {
+# CHECK:     OS/ABI: AMDGPU_HSA (0x40)
+# CHECK:     ABIVersion: 0
+# CHECK:   }
+# CHECK:   Machine: EM_AMDGPU (0xE0)
 # CHECK: }
 
 --- !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   Type:    ET_REL
   Machine: EM_AMDGPU
   OSABI:   ELFOSABI_AMDGPU_HSA
-
-Sections:
-  - Name:  .shf_amdgpu
-    Type:  SHT_PROGBITS
-    Flags: [ SHF_AMDGPU_HSA_GLOBAL, SHF_AMDGPU_HSA_READONLY,
-             SHF_AMDGPU_HSA_CODE, SHF_AMDGPU_HSA_AGENT]
 ...

llvm/trunk/test/tools/llvm-readobj/amdgpu-elf-definitions.test

+RUN: llvm-readobj -file-headers -program-headers -sections -symbols %p/Inputs/trivial.obj.elf-amdhsa-gfx803 | FileCheck %s
+
+CHECK: Format: ELF64-amdgpu-hsacobj
+CHECK: Arch: amdgcn
+CHECK: ElfHeader {
+CHECK:   Ident {
+CHECK:     OS/ABI: AMDGPU_HSA (0x40)
+CHECK:     ABIVersion: 0
+CHECK:   }
+CHECK:   Machine: EM_AMDGPU (0xE0)
+CHECK: }

llvm/trunk/test/tools/llvm-readobj/amdgpu-elf-defs.test

-RUN: llvm-readobj  -program-headers -sections -symbols -file-headers \
-RUN: %p/Inputs/trivial.elf-amdhsa-kaveri | FileCheck %s
-
-CHECK: ElfHeader {
-CHECK:  Ident {
-CHECK: Class: 64-bit (0x2)
-CHECK: DataEncoding: LittleEndian (0x1)
-CHECK: Machine: EM_AMDGPU (0xE0)
-
-
-CHECK: Section {
-CHECK: Name: .text
-CHECK: Type: SHT_PROGBITS (0x1)
-CHECK: Flags [ (0xC00007
-CHECK: SHF_ALLOC (0x2)
-CHECK: SHF_AMDGPU_HSA_AGENT (0x800000)
-CHECK: SHF_AMDGPU_HSA_CODE (0x400000)
-CHECK: SHF_EXECINSTR (0x4)
-CHECK: SHF_WRITE (0x1)
-
-CHECK: Symbol {
-CHECK: Name: hello_world
-CHECK: Value: 0x0
-CHECK: Binding: Local (0x0)
-CHECK: Type: AMDGPU_HSA_KERNEL (0xA)
-
-CHECK: ProgramHeader {
-CHECK: Type: PT_AMDGPU_HSA_LOAD_CODE_AGENT (0x60000003)

llvm/trunk/test/tools/llvm-readobj/elf-sec-flags.test

 # Check that llvm-readobj shows arch specific ELF section flags.
 
-# RUN: yaml2obj -docnum 1 %s > %t-amdgpu.o
-# RUN: llvm-readobj -s %t-amdgpu.o | FileCheck -check-prefix=AMD %s
-
-# AMD:      Flags [ (0x300000)
-# AMD-NEXT:   SHF_AMDGPU_HSA_GLOBAL (0x100000)
-# AMD-NEXT:   SHF_AMDGPU_HSA_READONLY (0x200000)
-# AMD-NEXT: ]
-
-# amdgpu.o
---- !ELF
-FileHeader:
-  Class:    ELFCLASS64
-  Data:     ELFDATA2LSB
-  OSABI:    ELFOSABI_GNU
-  Type:     ET_REL
-  Machine:  EM_AMDGPU
-  Flags:    []
-Sections:
-  - Name:   .amdgpu
-    Type:   SHT_PROGBITS
-    Flags:  [SHF_AMDGPU_HSA_GLOBAL, SHF_AMDGPU_HSA_READONLY]
-    Size:   4
-
-# RUN: yaml2obj -docnum 2 %s > %t-hex.o
+# RUN: yaml2obj -docnum 1 %s > %t-hex.o
 # RUN: llvm-readobj -s %t-hex.o | FileCheck -check-prefix=HEX %s
 
 # HEX:      Flags [ (0x10000000)
 # HEX-NEXT:   SHF_HEX_GPREL (0x10000000)
 # HEX-NEXT: ]
 
 # hex.o
 --- !ELF
 FileHeader:
   Class:    ELFCLASS32
   Data:     ELFDATA2LSB
   Type:     ET_REL
   Machine:  EM_HEXAGON
   Flags:    []
 Sections:
   - Name:   .hex
     Type:   SHT_PROGBITS
     Flags:  [SHF_HEX_GPREL]
     Size:   4
 
-# RUN: yaml2obj -docnum 3 %s > %t-mips.o
+# RUN: yaml2obj -docnum 2 %s > %t-mips.o
 # RUN: llvm-readobj -s %t-mips.o | FileCheck -check-prefix=MIPS %s
 
 # MIPS:      Flags [ (0x38000000)
 # MIPS-NEXT:   SHF_MIPS_GPREL (0x10000000)
 # MIPS-NEXT:   SHF_MIPS_MERGE (0x20000000)
 # MIPS-NEXT:   SHF_MIPS_NOSTRIP (0x8000000)
 # MIPS-NEXT: ]
 
 # mips.o
 --- !ELF
 FileHeader:
   Class:    ELFCLASS32
   Data:     ELFDATA2LSB
   Type:     ET_REL
   Machine:  EM_MIPS
   Flags:    []
 Sections:
   - Name:   .mips
     Type:   SHT_PROGBITS
     Flags:  [SHF_MIPS_GPREL, SHF_MIPS_MERGE, SHF_MIPS_NOSTRIP]
     Size:   4
 
-# RUN: yaml2obj -docnum 4 %s > %t-x86_64.o
+# RUN: yaml2obj -docnum 3 %s > %t-x86_64.o
 # RUN: llvm-readobj -s %t-x86_64.o | FileCheck -check-prefix=X86_64 %s
 
 # X86_64:      Flags [ (0x10000000)
 # X86_64-NEXT:   SHF_X86_64_LARGE (0x10000000)
 # X86_64-NEXT: ]
 
 # x86_64.o
 --- !ELF

llvm/trunk/tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfSymbolTypes[] = {
     {"Function",  "FUNC",    ELF::STT_FUNC},
     {"Section",   "SECTION", ELF::STT_SECTION},
     {"File",      "FILE",    ELF::STT_FILE},
     {"Common",    "COMMON",  ELF::STT_COMMON},
     {"TLS",       "TLS",     ELF::STT_TLS},
     {"GNU_IFunc", "IFUNC",   ELF::STT_GNU_IFUNC}};
 
 static const EnumEntry<unsigned> AMDGPUSymbolTypes[] = {
-  { "AMDGPU_HSA_KERNEL",            ELF::STT_AMDGPU_HSA_KERNEL },
-  { "AMDGPU_HSA_INDIRECT_FUNCTION", ELF::STT_AMDGPU_HSA_INDIRECT_FUNCTION },
-  { "AMDGPU_HSA_METADATA",          ELF::STT_AMDGPU_HSA_METADATA }
+  { "AMDGPU_HSA_KERNEL",            ELF::STT_AMDGPU_HSA_KERNEL }
 };
 
 static const char *getGroupType(uint32_t Flag) {
   if (Flag & ELF::GRP_COMDAT)
     return "COMDAT";
   else
     return "(unknown)";
 }
static const EnumEntry<unsigned> ElfSectionFlags[] = {
   ENUM_ENT_1(SHF_COMPRESSED),
 };
 
 static const EnumEntry<unsigned> ElfXCoreSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_CP_SECTION),
   LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_DP_SECTION)
 };
 
-static const EnumEntry<unsigned> ElfAMDGPUSectionFlags[] = {
-  LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_GLOBAL),
-  LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_READONLY),
-  LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_CODE),
-  LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_AGENT)
-};
-
 static const EnumEntry<unsigned> ElfARMSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_ARM_PURECODE)
 };
 
 static const EnumEntry<unsigned> ElfHexagonSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_HEX_GPREL)
 };
 
static std::string getGNUFlags(uint64_t Flags) {
   }
   return Str;
 }
 
 static const char *getElfSegmentType(unsigned Arch, unsigned Type) {
   // Check potentially overlapped processor-specific
   // program header type.
   switch (Arch) {
-  case ELF::EM_AMDGPU:
-    switch (Type) {
-    LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM);
-    LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT);
-    LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_READONLY_AGENT);
-    LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_CODE_AGENT);
-    }
   case ELF::EM_ARM:
     switch (Type) {
     LLVM_READOBJ_ENUM_CASE(ELF, PT_ARM_EXIDX);
     }
   case ELF::EM_MIPS:
   case ELF::EM_MIPS_RS3_LE:
     switch (Type) {
     LLVM_READOBJ_ENUM_CASE(ELF, PT_MIPS_REGINFO);
switch (Type) {
     LLVM_READOBJ_PHDR_ENUM(ELF, PT_TLS)
     LLVM_READOBJ_PHDR_ENUM(ELF, PT_GNU_EH_FRAME)
     LLVM_READOBJ_PHDR_ENUM(ELF, PT_SUNW_UNWIND)
     LLVM_READOBJ_PHDR_ENUM(ELF, PT_GNU_STACK)
     LLVM_READOBJ_PHDR_ENUM(ELF, PT_GNU_RELRO)
   default:
     // All machine specific PT_* types
     switch (Arch) {
-    case ELF::EM_AMDGPU:
-      switch (Type) {
-        LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM);
-        LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT);
-        LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_READONLY_AGENT);
-        LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_CODE_AGENT);
-      }
-      return "";
     case ELF::EM_ARM:
       if (Type == ELF::PT_ARM_EXIDX)
         return "EXIDX";
       return "";
     case ELF::EM_MIPS:
     case ELF::EM_MIPS_RS3_LE:
       switch (Type) {
       case PT_MIPS_REGINFO:
for (const Elf_Shdr &Sec : unwrapOrError(Obj->sections())) {
     W.printNumber("Name", Name, Sec.sh_name);
     W.printHex(
         "Type",
         object::getELFSectionTypeName(Obj->getHeader()->e_machine, Sec.sh_type),
         Sec.sh_type);
     std::vector<EnumEntry<unsigned>> SectionFlags(std::begin(ElfSectionFlags),
                                                   std::end(ElfSectionFlags));
     switch (Obj->getHeader()->e_machine) {
-    case EM_AMDGPU:
-      SectionFlags.insert(SectionFlags.end(), std::begin(ElfAMDGPUSectionFlags),
-                          std::end(ElfAMDGPUSectionFlags));
-      break;
     case EM_ARM:
       SectionFlags.insert(SectionFlags.end(), std::begin(ElfARMSectionFlags),
                           std::end(ElfARMSectionFlags));
       break;
     case EM_HEXAGON:
       SectionFlags.insert(SectionFlags.end(),
                           std::begin(ElfHexagonSectionFlags),
                           std::end(ElfHexagonSectionFlags));