[mips] Add runtime options to enable/disable generation of madd.fmt, msub.fmt

[smaksimovic]

Summary

Added options to clang are -mmadd4 and -mno-madd4, used to enable or disable generation
of madd.fmt and similar instructions respectively, as per GCC.

[sdardis]

This also requires that __mips_no_madd4 is defined when the -mnomadd4 option is in use.

[smaksimovic]

Changed feature name from madd4 to nomadd4 to reflect the change from the dependency.
Added macro definition when +nomadd4 is present.

[sdardis]

The new define also requires a test in test/Preprocessor/init.c - test that by default the new define isn't present, and in some case, when supplied with the -mno-madd4 that it is present.

LGTM with that change.

[smaksimovic]

Provided define checks, one when the target feature is present, other when the feature isn't provided at all (default).

include/clang/Driver/Options.td

def mno_check_zero_division : Flag<["-"], "mno-check-zero-division">,
                               Group<m_Group>;
 def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, Group<m_Group>;
 def mdsp : Flag<["-"], "mdsp">, Group<m_Group>;
 def mno_dsp : Flag<["-"], "mno-dsp">, Group<m_Group>;
 def mdspr2 : Flag<["-"], "mdspr2">, Group<m_Group>;
 def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group<m_Group>;
 def msingle_float : Flag<["-"], "msingle-float">, Group<m_Group>;
 def mdouble_float : Flag<["-"], "mdouble-float">, Group<m_Group>;
+def mmadd4 : Flag<["-"], "mmadd4">, Group<m_Group>,
+  HelpText<"Enable the generation of 4-operand madd.s, madd.d and related instructions.">;
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group<m_Group>,
+  HelpText<"Disable the generation of 4-operand madd.s, madd.d and related instructions.">;
 def mmsa : Flag<["-"], "mmsa">, Group<m_Group>,
   HelpText<"Enable MSA ASE (MIPS only)">;
 def mno_msa : Flag<["-"], "mno-msa">, Group<m_Group>,
   HelpText<"Disable MSA ASE (MIPS only)">;
 def mfp64 : Flag<["-"], "mfp64">, Group<m_Group>,
   HelpText<"Use 64-bit floating point registers (MIPS only)">;
 def mfp32 : Flag<["-"], "mfp32">, Group<m_Group>,
   HelpText<"Use 32-bit floating point registers (MIPS only)">;

lib/Basic/Targets.cpp

class MipsTargetInfo : public TargetInfo {
   bool CanUseBSDABICalls;
   enum MipsFloatABI {
     HardFloat, SoftFloat
   } FloatABI;
   enum DspRevEnum {
     NoDSP, DSP1, DSP2
   } DspRev;
   bool HasMSA;
+  bool DisableMadd4;
 
 protected:
   bool HasFP64;
   std::string ABI;
 
 public:
   MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
         IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
         CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-        HasMSA(false), HasFP64(false) {
+        HasMSA(false), DisableMadd4(false), HasFP64(false) {
     TheCXXABI.set(TargetCXXABI::GenericMIPS);
 
     setABI((getTriple().getArch() == llvm::Triple::mips ||
             getTriple().getArch() == llvm::Triple::mipsel)
                ? "o32"
                : "n64");
 
     CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
case DSP2:
       Builder.defineMacro("__mips_dspr2", Twine(1));
       Builder.defineMacro("__mips_dsp", Twine(1));
       break;
     }
 
     if (HasMSA)
       Builder.defineMacro("__mips_msa", Twine(1));
 
+    if (DisableMadd4)
+      Builder.defineMacro("__mips_no_madd4", Twine(1));
+
     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
 
     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
 
     // These shouldn't be defined for MIPS-I but there's no need to check
for (const auto &Feature : Features) {
       else if (Feature == "+micromips")
         IsMicromips = true;
       else if (Feature == "+dsp")
         DspRev = std::max(DspRev, DSP1);
       else if (Feature == "+dspr2")
         DspRev = std::max(DspRev, DSP2);
       else if (Feature == "+msa")
         HasMSA = true;
+      else if (Feature == "+nomadd4")
+        DisableMadd4 = true;
       else if (Feature == "+fp64")
         HasFP64 = true;
       else if (Feature == "-fp64")
         HasFP64 = false;
       else if (Feature == "+nan2008")
         IsNan2008 = true;
       else if (Feature == "-nan2008")
         IsNan2008 = false;

lib/Driver/ToolChains/Arch/Mips.cpp

if (Arg *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
     Features.push_back("+nooddspreg");
   } else if (mips::isFP64ADefault(Triple, CPUName)) {
     Features.push_back("+fp64");
     Features.push_back("+nooddspreg");
   }
 
   AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
                    options::OPT_modd_spreg, "nooddspreg");
+
+  if(Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
+    if(A->getOption().matches(options::OPT_mmadd4))
+      Features.push_back("-nomadd4");
+    else
+      Features.push_back("+nomadd4");
+  }
 }
 
 mips::NanEncoding mips::getSupportedNanEncoding(StringRef &CPU) {
   // Strictly speaking, mips32r2 and mips64r2 are NanLegacy-only since Nan2008
   // was first introduced in Release 3. However, other compilers have
   // traditionally allowed it for Release 2 so we should do the same.
   return (NanEncoding)llvm::StringSwitch<int>(CPU)
       .Case("mips1", NanLegacy)

test/CodeGen/mips-madd4.c

+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4    %s -o -| FileCheck %s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck %s -check-prefix=NOMADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4    -fno-honor-nans %s -o -| FileCheck %s -check-prefix=MADD4-NONAN
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=NOMADD4-NONAN
+ 
+float madd_s (float f, float g, float h)
+{
+  return (f * g) + h;
+}
+// MADD4:   madd.s
+// NOMADD4: mul.s
+// NOMADD4: add.s
+
+float msub_s (float f, float g, float h)
+{
+  return (f * g) - h;
+}
+// MADD4:   msub.s
+// NOMADD4: mul.s
+// NOMADD4: sub.s
+
+double madd_d (double f, double g, double h)
+{
+  return (f * g) + h;
+}
+// MADD4:   madd.d
+// NOMADD4: mul.d
+// NOMADD4: add.d
+
+double msub_d (double f, double g, double h)
+{
+  return (f * g) - h;
+}
+// MADD4:   msub.d
+// NOMADD4: mul.d
+// NOMADD4: sub.d
+
+
+float nmadd_s (float f, float g, float h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) + h);
+}
+// MADD4-NONAN:   nmadd.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: add.s
+// NOMADD4-NONAN: sub.s
+
+float nmsub_s (float f, float g, float h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) - h);
+}
+// MADD4-NONAN:   nmsub.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: sub.s
+// NOMADD4-NONAN: sub.s
+
+double nmadd_d (double f, double g, double h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) + h);
+}
+// MADD4-NONAN:   nmadd.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: add.d
+// NOMADD4-NONAN: sub.d
+
+double nmsub_d (double f, double g, double h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) - h);
+}
+// MADD4-NONAN:   nmsub.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: sub.d
+// NOMADD4-NONAN: sub.d
+