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Differential D33400

[mips] Add madd4 subtarget feature
ClosedPublic

Authored by smaksimovic on May 22 2017, 3:18 AM.

Details

Reviewers
sdardis
zoran.jovanovic
Commits
rG64fb7a8ebd9c: [mips] Add madd4 subtarget feature
rL304801: [mips] Add madd4 subtarget feature
Summary

Addition of a feature and a predicate used to control generation of madd.fmt and similar instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

smaksimovic created this revision.May 22 2017, 3:18 AM
Herald added a subscriber: arichardson. · View Herald TranscriptMay 22 2017, 3:18 AM
sdardis requested changes to this revision.May 22 2017, 5:35 AM
sdardis added a child revision: D33401: [mips] Add runtime options to enable/disable generation of madd.fmt, msub.fmt.

Rather than enabling the usage of 4 operand multiply accumulate instructions, we want to presume they're available by default if the ISA supports them. So rather than "HasMadd4", the logic we want is "DisableMadd4" which by default is false.

This revision now requires changes to proceed.May 22 2017, 5:35 AM
smaksimovic updated this revision to Diff 99906.May 23 2017, 7:00 AM
smaksimovic edited edge metadata.

Changed the feature name to disable_madd4 and set it to false by default.
As a result, removed the -mattr=... options from the test file.

sdardis requested changes to this revision.May 30 2017, 5:14 AM

This requires a test. Can you bring back test/CodeGen/Mips/fmad1.ll and add some additional RUN lines where madd/msub/etc is disabled, and check that madd/msub/etc aren't generated?

lib/Target/Mips/Mips.td
188 ↗(On Diff #99906)

This should be "nomadd4" rather than "disable_madd4".

189 ↗(On Diff #99906)

"Disable 4-operand madd.fmt and related instructions".

This revision now requires changes to proceed.May 30 2017, 5:14 AM
smaksimovic updated this revision to Diff 100702.May 30 2017, 6:55 AM
smaksimovic edited edge metadata.

Addressed review comments.

smaksimovic marked 2 inline comments as done.May 30 2017, 6:56 AM
sdardis accepted this revision.May 30 2017, 8:48 AM

LGTM with a nit addressed.

test/CodeGen/Mips/fmadd1.ll
8–30 ↗(On Diff #100702)

Rather than reusing prefixes in a slightly unexpected way, rename the ones that don't have madd.fmt instructions to some like '$ORIGNALLABEL-NOMADD".

This revision is now accepted and ready to land.May 30 2017, 8:48 AM
smaksimovic updated this revision to Diff 101006.Jun 1 2017, 4:33 AM

Renamed prefixes.
Additionally, noticed that some of the MC tests were failing due to llvm-mc incorrectly interpreting the newly added feature. Changed AssemblerPredicate<"FeatureMadd4"> to AssemblerPredicate<"!FeatureMadd4"> to fix the issue.

Closed by commit rL304801: [mips] Add madd4 subtarget feature (authored by petarj). · Explain WhyJun 6 2017, 8:33 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
3 lines
18 lines
6 lines
5 lines
2 lines
test/
CodeGen/
Mips/
535 lines

Diff 101572

llvm/trunk/lib/Target/Mips/Mips.td

Show First 20 Lines • Show All 179 Lines • ▼ Show 20 Linesdef FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
"true", "Octeon cnMIPS Support", "true", "Octeon cnMIPS Support",
[FeatureMips64r2]>; [FeatureMips64r2]>;
def FeatureUseTCCInDIV : SubtargetFeature< def FeatureUseTCCInDIV : SubtargetFeature<
"use-tcc-in-div", "use-tcc-in-div",
"UseTCCInDIV", "false", "UseTCCInDIV", "false",
"Force the assembler to use trapping">; "Force the assembler to use trapping">;
def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
"Disable 4-operand madd.fmt and related instructions">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips processors supported. // Mips processors supported.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
"MipsSubtarget::CPU::P5600", "MipsSubtarget::CPU::P5600",
"The P5600 Processor", [FeatureMips32r5]>; "The P5600 Processor", [FeatureMips32r5]>;
Show All 38 Lines

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 551 Lines • ▼ Show 20 Lines
def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
ADDS_FM<0x02, 16>; ADDS_FM<0x02, 16>;
defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
ADDS_FM<0x01, 16>; ADDS_FM<0x01, 16>;
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
let AdditionalPredicates = [NoNaNsFPMath] in { let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
} }
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
let AdditionalPredicates = [NoNaNsFPMath] in { let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
} }
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
} }
let AdditionalPredicates = [NoNaNsFPMath], let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
DecoderNamespace = "Mips64" in { DecoderNamespace = "Mips64" in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 259 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
def IsLE : Predicate<"Subtarget->isLittle()">; def IsLE : Predicate<"Subtarget->isLittle()">;
def IsBE : Predicate<"!Subtarget->isLittle()">; def IsBE : Predicate<"!Subtarget->isLittle()">;
def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
def HasEVA : Predicate<"Subtarget->hasEVA()">, def HasEVA : Predicate<"Subtarget->hasEVA()">,
AssemblerPredicate<"FeatureEVA,FeatureMips32r2">; AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
def HasMSA : Predicate<"Subtarget->hasMSA()">, def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">; AssemblerPredicate<"FeatureMSA">;
def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
AssemblerPredicate<"!FeatureMadd4">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips GPR size adjectives. // Mips GPR size adjectives.
// They are mutually exclusive. // They are mutually exclusive.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl { class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6]; let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
} }
class ASE_NOT_DSP { class ASE_NOT_DSP {
list<Predicate> InsnPredicates = [NotDSP]; list<Predicate> InsnPredicates = [NotDSP];
} }
class MADD4 {
list<Predicate> AdditionalPredicates = [HasMadd4];
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl { class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
let EncodingPredicates = [HasStdEnc]; let EncodingPredicates = [HasStdEnc];
} }
class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
InstAlias<Asm, Result, Emit>, PredicateControl; InstAlias<Asm, Result, Emit>, PredicateControl;
▲ Show 20 Lines • Show All 2,531 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Linesclass MipsSubtarget : public MipsGenSubtargetInfo {
// UseTCCInDIV -- Enables the use of trapping in the assembler. // UseTCCInDIV -- Enables the use of trapping in the assembler.
bool UseTCCInDIV; bool UseTCCInDIV;
// Sym32 -- On Mips64 symbols are 32 bits. // Sym32 -- On Mips64 symbols are 32 bits.
bool HasSym32; bool HasSym32;
// HasEVA -- supports EVA ASE. // HasEVA -- supports EVA ASE.
bool HasEVA; bool HasEVA;
// nomadd4 - disables generation of 4-operand madd.s, madd.d and
// related instructions.
bool DisableMadd4;
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
// We can override the determination of whether we are in mips16 mode // We can override the determination of whether we are in mips16 mode
// as from the command line // as from the command line
enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
const MipsTargetMachine &TM; const MipsTargetMachine &TM;
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Linespublic:
} }
bool inMicroMipsMode() const { return InMicroMipsMode; } bool inMicroMipsMode() const { return InMicroMipsMode; }
bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); } bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
bool hasDSP() const { return HasDSP; } bool hasDSP() const { return HasDSP; }
bool hasDSPR2() const { return HasDSPR2; } bool hasDSPR2() const { return HasDSPR2; }
bool hasDSPR3() const { return HasDSPR3; } bool hasDSPR3() const { return HasDSPR3; }
bool hasMSA() const { return HasMSA; } bool hasMSA() const { return HasMSA; }
bool disableMadd4() const { return DisableMadd4; }
bool hasEVA() const { return HasEVA; } bool hasEVA() const { return HasEVA; }
bool useSmallSection() const { return UseSmallSection; } bool useSmallSection() const { return UseSmallSection; }
bool hasStandardEncoding() const { return !inMips16Mode(); } bool hasStandardEncoding() const { return !inMips16Mode(); }
bool useSoftFloat() const { return IsSoftFloat; } bool useSoftFloat() const { return IsSoftFloat; }
bool enableLongBranchPass() const { bool enableLongBranchPass() const {
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(), HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(),
InstrInfo( InstrInfo(
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
FrameLowering(MipsFrameLowering::create(*this)), FrameLowering(MipsFrameLowering::create(*this)),
TLInfo(MipsTargetLowering::create(TM, *this)) { TLInfo(MipsTargetLowering::create(TM, *this)) {
if (MipsArchVersion == MipsDefault) if (MipsArchVersion == MipsDefault)
MipsArchVersion = Mips32; MipsArchVersion = Mips32;
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/fmadd1.ll

; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
; correctly. ; correctly.
; The spec for nmadd.[ds], and nmsub.[ds] does not state that they obey the ; The spec for nmadd.[ds], and nmsub.[ds] does not state that they obey the
; the Has2008 and ABS2008 configuration bits which govern the conformance to ; the Has2008 and ABS2008 configuration bits which govern the conformance to
; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only ; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
; available when -enable-no-nans-fp-math is given. ; available when -enable-no-nans-fp-math is given.
; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32,32-NONAN ; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6,32R6-NONAN ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NONAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6,64R6-NONAN ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32,32-NAN ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6,32R6-NAN ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6,64R6-NAN ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
; when +nomadd attribute is specified.
; Output for mips32 and mips64r6 reused since aforementioned instructions are
; not generated in those cases.
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
define float @FOO0float(float %a, float %b, float %c) nounwind readnone { define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO0float: ; ALL-LABEL: FOO0float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.s $f0, $[[T1]], $[[T2]] ; 32-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
; 32R2: mtc1 $6, $[[T0:f[0-9]+]] ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2: add.s $f0, $[[T1]], $[[T2]] ; 32R2: add.s $f0, $[[T1]], $[[T2]]
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]] ; 32R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T0]], $[[T1]] ; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.s $f0, $[[T0]], $[[T1]] ; 64R2: add.s $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14 ; 64R6-NOMADD-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]] ; 64R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
%mul = fmul float %a, %b %mul = fmul float %a, %b
%add = fadd float %mul, %c %add = fadd float %mul, %c
%add1 = fadd float %add, 0.000000e+00 %add1 = fadd float %add, 0.000000e+00
ret float %add1 ret float %add1
} }
define float @FOO1float(float %a, float %b, float %c) nounwind readnone { define float @FOO1float(float %a, float %b, float %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO1float: ; ALL-LABEL: FOO1float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.s $f0, $[[T1]], $[[T2]] ; 32-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
; 32R2: mtc1 $6, $[[T0:f[0-9]+]] ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2: add.s $f0, $[[T1]], $[[T2]] ; 32R2: add.s $f0, $[[T1]], $[[T2]]
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]] ; 32R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T0]], $[[T1]] ; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.s $f0, $[[T0]], $[[T1]] ; 64R2: add.s $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14 ; 64R6-NOMADD-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]] ; 64R6-NOMADD-DAG: add.s $f0, $[[T1]], $[[T2]]
%mul = fmul float %a, %b %mul = fmul float %a, %b
%sub = fsub float %mul, %c %sub = fsub float %mul, %c
%add = fadd float %sub, 0.000000e+00 %add = fadd float %sub, 0.000000e+00
ret float %add ret float %add
} }
define float @FOO2float(float %a, float %b, float %c) nounwind readnone { define float @FOO2float(float %a, float %b, float %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO2float: ; ALL-LABEL: FOO2float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.s $f0, $[[T2]], $[[T1]] ; 32-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]] ; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14 ; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]] ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]] ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]] ; 32R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13 ; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]] ; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]] ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14 ; 64R6-NOMADD-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]] ; 64R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
%mul = fmul float %a, %b %mul = fmul float %a, %b
%add = fadd float %mul, %c %add = fadd float %mul, %c
%sub = fsub float 0.000000e+00, %add %sub = fsub float 0.000000e+00, %add
ret float %sub ret float %sub
} }
define float @FOO3float(float %a, float %b, float %c) nounwind readnone { define float @FOO3float(float %a, float %b, float %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO3float: ; ALL-LABEL: FOO3float:
; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.s $f0, $[[T2]], $[[T1]] ; 32-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]] ; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14 ; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]] ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]] ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]] ; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13 ; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]] ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14 ; 64R6-NOMADD-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]] ; 64R6-NOMADD-DAG: sub.s $f0, $[[T2]], $[[T1]]
%mul = fmul float %a, %b %mul = fmul float %a, %b
%sub = fsub float %mul, %c %sub = fsub float %mul, %c
%sub1 = fsub float 0.000000e+00, %sub %sub1 = fsub float 0.000000e+00, %sub
ret float %sub1 ret float %sub1
} }
define double @FOO10double(double %a, double %b, double %c) nounwind readnone { define double @FOO10double(double %a, double %b, double %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO10double: ; ALL-LABEL: FOO10double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.d $f0, $[[T1]], $[[T2]] ; 32-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2: mthc1 $zero, $[[T2]] ; 32R2: mthc1 $zero, $[[T2]]
; 32R2: add.d $f0, $[[T1]], $[[T2]] ; 32R2: add.d $f0, $[[T1]], $[[T2]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]] ; 32R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T0]], $[[T1]] ; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.d $f0, $[[T0]], $[[T1]] ; 64R2: add.d $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14 ; 64R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]] ; 64R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
%mul = fmul double %a, %b %mul = fmul double %a, %b
%add = fadd double %mul, %c %add = fadd double %mul, %c
%add1 = fadd double %add, 0.000000e+00 %add1 = fadd double %add, 0.000000e+00
ret double %add1 ret double %add1
} }
define double @FOO11double(double %a, double %b, double %c) nounwind readnone { define double @FOO11double(double %a, double %b, double %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO11double: ; ALL-LABEL: FOO11double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: add.d $f0, $[[T1]], $[[T2]] ; 32-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2: mthc1 $zero, $[[T2]] ; 32R2: mthc1 $zero, $[[T2]]
; 32R2: add.d $f0, $[[T1]], $[[T2]] ; 32R2: add.d $f0, $[[T1]], $[[T2]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]] ; 32R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T0]], $[[T1]] ; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2: add.d $f0, $[[T0]], $[[T1]] ; 64R2: add.d $f0, $[[T0]], $[[T1]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14 ; 64R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]] ; 64R6-NOMADD-DAG: add.d $f0, $[[T1]], $[[T2]]
%mul = fmul double %a, %b %mul = fmul double %a, %b
%sub = fsub double %mul, %c %sub = fsub double %mul, %c
%add = fadd double %sub, 0.000000e+00 %add = fadd double %sub, 0.000000e+00
ret double %add ret double %add
} }
define double @FOO12double(double %a, double %b, double %c) nounwind readnone { define double @FOO12double(double %a, double %b, double %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO12double: ; ALL-LABEL: FOO12double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]] ; 32-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14 ; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: mthc1 $zero, $[[T2]] ; 32R2-NAN: mthc1 $zero, $[[T2]]
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]] ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]] ; 32R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13 ; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]] ; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13 ; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]] ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14 ; 64R6-NOMADD-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]] ; 64R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
%mul = fmul double %a, %b %mul = fmul double %a, %b
%add = fadd double %mul, %c %add = fadd double %mul, %c
%sub = fsub double 0.000000e+00, %add %sub = fsub double 0.000000e+00, %add
ret double %sub ret double %sub
} }
define double @FOO13double(double %a, double %b, double %c) nounwind readnone { define double @FOO13double(double %a, double %b, double %c) nounwind readnone {
entry: entry:
; ALL-LABEL: FOO13double: ; ALL-LABEL: FOO13double:
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]] ; 32-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14 ; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: mthc1 $zero, $[[T2]] ; 32R2-NAN: mthc1 $zero, $[[T2]]
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]] ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R6-NOMADD-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14 ; 32R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]] ; 32R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]] ; 32R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13 ; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]] ; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13 ; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]] ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]] ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 ; 64R6-NOMADD-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14 ; 64R6-NOMADD-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] ; 64R6-NOMADD-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]] ; 64R6-NOMADD-DAG: sub.d $f0, $[[T2]], $[[T1]]
%mul = fmul double %a, %b %mul = fmul double %a, %b
%sub = fsub double %mul, %c %sub = fsub double %mul, %c
%sub1 = fsub double 0.000000e+00, %sub %sub1 = fsub double 0.000000e+00, %sub
ret double %sub1 ret double %sub1
} }