AMDGPU: M0 operands to spill/restore opcodes are dead

[nhaehnle]

Summary

With scalar stores, M0 is clobbered and therefore marked as implicitly
defined. However, it is also dead.

This fixes an assertion when the Greedy Register Allocator decides to
optimize a spill/restore pair away again (via tryHintsRecoloring).

[arsenm]

LGTM, although I thought it now saves/restores m0's value so it might be OK to just remove the m0 operand entirely

[arsenm]

Are you actually trying to use the scalar store path

[rampitec]

Thanks! It resolves https://bugs.llvm.org/show_bug.cgi?id=33159

[rampitec]

Nikolai, is there anything wrong with this patch? Do you plan to submit it anytime soon?

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc)
       .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
       .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
     // Add the scratch resource registers as implicit uses because we may end up
     // needing them, and need to ensure that the reserved registers are
     // correctly handled.
 
     if (ST.hasScalarStores()) {
       // m0 is used for offset to scalar stores if used to spill.
-      Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine);
+      Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
     }
 
     return;
   }
 
   if (!ST.isVGPRSpillingEnabled(*MF->getFunction())) {
     LLVMContext &Ctx = MF->getFunction()->getContext();
     Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
if (RI.isSGPRClass(RC)) {
     MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc, DestReg)
       .addFrameIndex(FrameIndex) // addr
       .addMemOperand(MMO)
       .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
       .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
 
     if (ST.hasScalarStores()) {
       // m0 is used for offset to scalar stores if used to spill.
-      Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine);
+      Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
     }
 
     return;
   }
 
   if (!ST.isVGPRSpillingEnabled(*MF->getFunction())) {
     LLVMContext &Ctx = MF->getFunction()->getContext();
     Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"

llvm/trunk/test/CodeGen/AMDGPU/spill-to-smem-m0.ll

+; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs -stop-before=prologepilog < %s
+
+; Spill to SMEM clobbers M0. Check that the implicit-def dead operand is present
+; in the pseudo instructions.
+
+; CHECK-LABEL: {{^}}spill_sgpr:
+; CHECK: SI_SPILL_S32_SAVE {{.*}}, implicit-def dead %m0
+; CHECK: SI_SPILL_S32_RESTORE {{.*}}, implicit-def dead %m0
+define amdgpu_kernel void @spill_sgpr(i32 addrspace(1)* %out, i32 %in) #0 {
+  %sgpr = call i32  asm sideeffect "; def $0", "=s" () #0
+  %cmp = icmp eq i32 %in, 0
+  br i1 %cmp, label %bb0, label %ret
+
+bb0:
+  call void asm sideeffect "; use $0", "s"(i32 %sgpr) #0
+  br label %ret
+
+ret:
+  ret void
+}
+
+attributes #0 = { nounwind }