[AMDGPU][MC] Fixed bugs in export instruction

[dp]

Summary

See Bugs 33019, 33056:

https://bugs.llvm.org//show_bug.cgi?id=33019
https://bugs.llvm.org//show_bug.cgi?id=33056

[artem.tamazov]

Looks good to me.

[artem.tamazov]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

2809 ↗

(On Diff #99322)

One thing: I would better keep ++SrcIdx in separate line.

2816 ↗

(On Diff #99322)

Ditto

[dp]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

2809 ↗

(On Diff #99322)

Ok, I'll correct this before submitting the patch

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

if (!IsGdsHardcoded) {
     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
   }
   Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
 }
 
 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
   OptionalImmIndexMap OptionalIdx;
 
+  unsigned OperandIdx[4];
   unsigned EnMask = 0;
   int SrcIdx = 0;
 
   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
 
     // Add the register arguments
     if (Op.isReg()) {
-      EnMask |= (1 << SrcIdx);
+      assert(SrcIdx < 4);
+      OperandIdx[SrcIdx] = Inst.size();
       Op.addRegOperands(Inst, 1);
       ++SrcIdx;
       continue;
     }
 
     if (Op.isOff()) {
-      ++SrcIdx;
+      assert(SrcIdx < 4);
+      OperandIdx[SrcIdx] = Inst.size();
       Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
+      ++SrcIdx;
       continue;
     }
 
     if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {
       Op.addImmOperands(Inst, 1);
       continue;
     }
 
     if (Op.isToken() && Op.getToken() == "done")
       continue;
 
     // Handle optional arguments
     OptionalIdx[Op.getImmTy()] = i;
   }
 
+  assert(SrcIdx == 4);
+
+  bool Compr = false;
+  if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {
+    Compr = true;
+    Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);
+    Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
+    Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
+  }
+
+  for (auto i = 0; i < SrcIdx; ++i) {
+    if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {
+      EnMask |= Compr? (0x3 << i * 2) : (0x1 << i);
+    }
+  }
+
   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
 
   Inst.addOperand(MCOperand::createImm(EnMask));
 }
 
 //===----------------------------------------------------------------------===//
 // s_waitcnt
static const OptionalOperand AMDGPUOptionalOperandTable[] = {
   {"dmask",   AMDGPUOperand::ImmTyDMask, false, nullptr},
   {"row_mask",   AMDGPUOperand::ImmTyDppRowMask, false, nullptr},
   {"bank_mask",  AMDGPUOperand::ImmTyDppBankMask, false, nullptr},
   {"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, ConvertBoundCtrl},
   {"dst_sel",    AMDGPUOperand::ImmTySdwaDstSel, false, nullptr},
   {"src0_sel",   AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr},
   {"src1_sel",   AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr},
   {"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
+  {"compr", AMDGPUOperand::ImmTyExpCompr, true, nullptr },
   {"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr},
   {"op_sel", AMDGPUOperand::ImmTyOpSel, false, nullptr},
   {"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr},
   {"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr},
   {"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr}
 };
 
 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

 }
 
 class EXPe : Enc64 {
   bits<4> en;
   bits<6> tgt;
   bits<1> compr;
   bits<1> done;
   bits<1> vm;
-  bits<8> vsrc0;
-  bits<8> vsrc1;
-  bits<8> vsrc2;
-  bits<8> vsrc3;
+  bits<8> src0;
+  bits<8> src1;
+  bits<8> src2;
+  bits<8> src3;
 
   let Inst{3-0} = en;
   let Inst{9-4} = tgt;
   let Inst{10} = compr;
   let Inst{11} = done;
   let Inst{12} = vm;
   let Inst{31-26} = 0x3e;
-  let Inst{39-32} = vsrc0;
-  let Inst{47-40} = vsrc1;
-  let Inst{55-48} = vsrc2;
-  let Inst{63-56} = vsrc3;
+  let Inst{39-32} = src0;
+  let Inst{47-40} = src1;
+  let Inst{55-48} = src2;
+  let Inst{63-56} = src3;
 }
 
 let Uses = [EXEC] in {
 
 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
   let VINTRP = 1;
   // VINTRP instructions read parameter values from LDS, but these parameter

llvm/trunk/test/MC/AMDGPU/exp.s

 
 exp mrt0 v4, v3, v2, v1 vm
 // SI: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
 // VI: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x04,0x03,0x02,0x01]
 
 exp mrt0 v4, v3, v2, v1 done vm
 // SI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
 // VI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01]
+
+exp mrtz, v3, v3, v7, v7 compr
+// SI: exp mrtz v3, v3, v7, v7 compr   ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00]
+// VI: exp mrtz v3, v3, v7, v7 compr   ; encoding: [0x8f,0x04,0x00,0xc4,0x03,0x07,0x00,0x00]
+
+exp mrtz, off, off, v7, v7 compr
+// SI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00]
+// VI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00]
+
+exp mrtz, v3, v3, off, off compr
+// SI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00]
+// VI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xc4,0x03,0x00,0x00,0x00]

llvm/trunk/test/MC/Disassembler/AMDGPU/exp_vi.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+# VI: exp mrt0 v1, v2, v3, v4    ; encoding: [0x0f,0x00,0x00,0xc4,0x01,0x02,0x03,0x04]
+0x0f,0x00,0x00,0xc4,0x01,0x02,0x03,0x04
+
+# VI: exp mrt0 v1, v2, v3, v4 vm    ; encoding: [0x0f,0x10,0x00,0xc4,0x01,0x02,0x03,0x04]
+0x0f,0x10,0x00,0xc4,0x01,0x02,0x03,0x04
+
+# VI: exp mrt0 v1, v1, v3, v3 compr    ; encoding: [0x0f,0x04,0x00,0xc4,0x01,0x03,0x00,0x00]
+0x0f,0x04,0x00,0xc4,0x01,0x03,0x00,0x00
+
+# VI: exp mrt0 v1, v2, v3, v4 done    ; encoding: [0x0f,0x08,0x00,0xc4,0x01,0x02,0x03,0x04]
+0x0f,0x08,0x00,0xc4,0x01,0x02,0x03,0x04
+
+# VI: exp mrt0 v2, v2, v4, v4 done compr vm    ; encoding: [0x0f,0x1c,0x00,0xc4,0x02,0x04,0x00,0x00]
+0x0f,0x1c,0x00,0xc4,0x02,0x04,0x00,0x00
+
+# VI: exp mrt0 v7, off, off, off vm    ; encoding: [0x01,0x10,0x00,0xc4,0x07,0x00,0x00,0x00]
+0x01,0x10,0x00,0xc4,0x07,0x00,0x00,0x00
+
+# VI: exp mrt0 off, off, v1, v2    ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x01,0x02]
+0x0c,0x00,0x00,0xc4,0x00,0x00,0x01,0x02
+
+# VI: exp mrt0 off, off, v8, v8 done compr    ; encoding: [0x0c,0x0c,0x00,0xc4,0x00,0x08,0x00,0x00]
+0x0c,0x0c,0x00,0xc4,0x00,0x08,0x00,0x00
+
+# VI: exp mrt0 v1, v1, off, off compr   ; encoding: [0x03,0x04,0x00,0xc4,0x01,0x00,0x00,0x00]
+0x03,0x04,0x00,0xc4,0x01,0x00,0x00,0x00
+
+# VI: exp param0 off, off, off, off compr    ; encoding: [0x00,0x06,0x00,0xc4,0x00,0x00,0x00,0x00]
+0x00,0x06,0x00,0xc4,0x00,0x00,0x00,0x00
+
+# VI: exp mrtz v0, off, off, off done vm    ; encoding: [0x81,0x18,0x00,0xc4,0x00,0x00,0x00,0x00]
+0x81,0x18,0x00,0xc4,0x00,0x00,0x00,0x00
+
+# VI: exp null v255, v0, v255, v0    ; encoding: [0x9f,0x00,0x00,0xc4,0xff,0x00,0xff,0x00]
+0x9f,0x00,0x00,0xc4,0xff,0x00,0xff,0x00
+
+# VI: exp pos0 v1, off, off, off    ; encoding: [0xc1,0x00,0x00,0xc4,0x01,0x00,0x00,0x00]
+0xc1,0x00,0x00,0xc4,0x01,0x00,0x00,0x00