[AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals
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Authored by dp on May 5 2017, 8:36 AM.

Details

Summary

Currently instructions like these cannot be disassembled:

s_add_i32 s0, 0xafaaffff, 0xafaaffff

See bug 32922: https://bugs.llvm.org//show_bug.cgi?id=32922

Diff Detail

Repository
rL LLVM
dp created this revision.May 5 2017, 8:36 AM
dp added a comment.May 18 2017, 1:28 AM

As nobody is interested reviewing this patch, it will be submitted on Friday

artem.tamazov accepted this revision.May 18 2017, 5:56 AM
This revision is now accepted and ready to land.May 18 2017, 5:56 AM
This revision was automatically updated to reflect the committed changes.