[AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals

[dp]

Summary

Currently instructions like these cannot be disassembled:

s_add_i32 s0, 0xafaaffff, 0xafaaffff

See bug 32922: https://bugs.llvm.org//show_bug.cgi?id=32922

[dp]

As nobody is interested reviewing this patch, it will be submitted on Friday

llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

 
 //===----------------------------------------------------------------------===//
 // AMDGPUDisassembler
 //===----------------------------------------------------------------------===//
 
 class AMDGPUDisassembler : public MCDisassembler {
 private:
   mutable ArrayRef<uint8_t> Bytes;
+  mutable uint32_t Literal;
+  mutable bool HasLiteral;
 
 public:
   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
     MCDisassembler(STI, Ctx) {}
 
   ~AMDGPUDisassembler() override = default;
 
   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,

llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

 
 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
                                                MCInst &MI,
                                                uint64_t Inst,
                                                uint64_t Address) const {
   assert(MI.getOpcode() == 0);
   assert(MI.getNumOperands() == 0);
   MCInst TmpInst;
+  HasLiteral = false;
   const auto SavedBytes = Bytes;
   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
     MI = TmpInst;
     return MCDisassembler::Success;
   }
   Bytes = SavedBytes;
   return MCDisassembler::Fail;
 }
MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
 }
 
 
 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
   // For now all literal constants are supposed to be unsigned integer
   // ToDo: deal with signed/unsigned 64-bit integer constants
   // ToDo: deal with float/double constants
-  if (Bytes.size() < 4)
+  if (!HasLiteral) {
+    if (Bytes.size() < 4) {
       return errOperand(0, "cannot read literal, inst bytes left " +
-                         Twine(Bytes.size()));
-  return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
+    }
+    HasLiteral = true;
+    Literal = eatBytes<uint32_t>(Bytes);
+  }
+  return MCOperand::createImm(Literal);
 }
 
 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
   using namespace AMDGPU::EncValues;
   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));

llvm/trunk/test/MC/Disassembler/AMDGPU/sopc_vi.txt

 # GCN: s_bitcmp0_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0e,0xbf]
 0x02 0x04 0x0e 0xbf
 
 # GCN: s_bitcmp1_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0f,0xbf]
 0x02 0x04 0x0f 0xbf
 
 # GCN: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]
 0x03 0x05 0x10 0xbf
+
+# GCN: s_bitcmp0_b32 0xafaaffff, 0xafaaffff ; encoding: [0xff,0xff,0x0c,0xbf,0xff,0xff,0xaa,0xaf]
+0xff 0xff 0x0c 0xbf 0xff 0xff 0xaa 0xaf