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Differential D32868

[globalisel][tablegen] Fix nullptr dereferences when getVRegDef() is called on a phys reg.
Needs ReviewPublic

Authored by dsanders on May 4 2017, 9:44 AM.

Details

Reviewers
qcolombet
ab
t.p.northover
rovka
kristof.beyls
aditya_nandakumar
Summary

This is triggered by the current version of D32278 when applied to trunk.

Diff Detail

Event Timeline

dsanders created this revision.May 4 2017, 9:44 AM
Herald added a subscriber: igorb. · View Herald TranscriptMay 4 2017, 9:44 AM
dsanders mentioned this in D32869: [globalisel][tablegen] Require that all registers between instructions of a match are virtual..May 4 2017, 9:57 AM
dsanders added a child revision: D32869: [globalisel][tablegen] Require that all registers between instructions of a match are virtual..May 4 2017, 9:59 AM
qcolombet edited edge metadata.May 11 2017, 2:45 PM

Hi Daniel,

I have trouble to relate the description of the patch and the patch itself.
I was expecting something that would generate some guard before getVRegDef and instead I see that we take the address instead of a reference to an instruction.
I am guessing this is because we want the code used to emit the matcher to work with either non-null or null instruction, but I fail to see this demonstrated in the patch. In other words, I don't see where we would have a nullptr dereferenced here.

Put differently, where does the getVRegDef come into play in that patch?

Cheers,
-Quentin

dsanders added inline comments.May 11 2017, 3:25 PM
test/TableGen/GlobalISelEmitter.td
141–142

There's only a couple of them in the test at the moment but here's one of the getVRegDef's.

getVRegDef() returns a pointer to the MI that def's the register or nullptr otherwise. Previously, we unconditionally dereferenced it which caused a nullptr dereference when the register was live-in but now we check for the nullptr first.

qcolombet added inline comments.May 12 2017, 1:59 PM
test/TableGen/GlobalISelEmitter.td
141–142

Here is it, I missed it with my previous search :).

I would rather have a check before the getVRegDef whether the register is a vreg or not.
I know getVRegDef works with PhysReg, but in practice we try not to call it on then, because it is strange :).

dsanders mentioned this in rL303253: [globalisel][tablegen] Require that all registers between instructions of a….May 17 2017, 5:56 AM

Revision Contents

PathSize
test/
TableGen/
292 lines
utils/
TableGen/
17 lines

Diff 97839

test/TableGen/GlobalISelEmitter.td

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// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I) const { // CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I) const {
// CHECK: MachineFunction &MF = *I.getParent()->getParent(); // CHECK: MachineFunction &MF = *I.getParent()->getParent();
// CHECK: const MachineRegisterInfo &MRI = MF.getRegInfo(); // CHECK: const MachineRegisterInfo &MRI = MF.getRegInfo();
//===- Test a pattern with multiple ComplexPattern operands. --------------===// //===- Test a pattern with multiple ComplexPattern operands. --------------===//
// //
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 4) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 4)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_SELECT) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_SELECT) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((Renderer0 = selectComplexPattern(MI0.getOperand(2)))))) && // CHECK-NEXT: ((Renderer0 = selectComplexPattern(MI0->getOperand(2)))))) &&
// CHECK-NEXT: ((/* src3 */ (MRI.getType(MI0.getOperand(3).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src3 */ (MRI.getType(MI0->getOperand(3).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((Renderer1 = selectComplexPattern(MI0.getOperand(3))))))) { // CHECK-NEXT: ((Renderer1 = selectComplexPattern(MI0->getOperand(3))))))) {
// CHECK-NEXT: // (select:i32 GPR32:i32:$src1, complex:i32:$src2, complex:i32:$src3) => (INSN2:i32 GPR32:i32:$src1, complex:i32:$src3, complex:i32:$src2) // CHECK-NEXT: // (select:i32 GPR32:i32:$src1, complex:i32:$src2, complex:i32:$src3) => (INSN2:i32 GPR32:i32:$src1, complex:i32:$src3, complex:i32:$src2)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN2)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN2));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src1*/);
// CHECK-NEXT: Renderer1(MIB); // CHECK-NEXT: Renderer1(MIB);
// CHECK-NEXT: Renderer0(MIB); // CHECK-NEXT: Renderer0(MIB);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
def : GINodeEquiv<G_SELECT, select>; def : GINodeEquiv<G_SELECT, select>;
def INSN2 : I<(outs GPR32:$dst), (ins GPR32Op:$src1, complex:$src2, complex:$src3), []>; def INSN2 : I<(outs GPR32:$dst), (ins GPR32Op:$src1, complex:$src2, complex:$src3), []>;
def : Pat<(select GPR32:$src1, complex:$src2, complex:$src3), def : Pat<(select GPR32:$src1, complex:$src2, complex:$src3),
(INSN2 GPR32:$src1, complex:$src3, complex:$src2)>; (INSN2 GPR32:$src1, complex:$src3, complex:$src2)>;
//===- Test a simple pattern with regclass operands. ----------------------===// //===- Test a simple pattern with regclass operands. ----------------------===//
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_ADD) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_ADD) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) { // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(2).getReg(), MRI, TRI)))))) {
// CHECK-NEXT: // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2) // CHECK-NEXT: // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2)
// CHECK-NEXT: I.setDesc(TII.get(MyTarget::ADD)); // CHECK-NEXT: I.setDesc(TII.get(MyTarget::ADD));
// CHECK-NEXT: MachineInstr &NewI = I; // CHECK-NEXT: MachineInstr &NewI = I;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
[(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>; [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
//===- Test a nested instruction match. -----------------------------------===// //===- Test a nested instruction match. -----------------------------------===//
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: PredicateBitset ExpectedFeatures = {Feature_HasABit}; // CHECK-NEXT: PredicateBitset ExpectedFeatures = {Feature_HasABit};
// CHECK-NEXT: if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures) // CHECK-NEXT: if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if (!MI0.getOperand(1).isReg()) // CHECK-NEXT: if (!MI0->getOperand(1).isReg())
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(1).getReg()); // CHECK-NEXT: MachineInstr *MI1 = MRI.getVRegDef(MI0->getOperand(1).getReg());
// CHECK-NEXT: if (MI1.getNumOperands() < 3) // CHECK-NEXT: if (!MI1 || MI1->getNumOperands() < 3)
dsandersAuthorUnsubmitted
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There's only a couple of them in the test at the moment but here's one of the getVRegDef's.

getVRegDef() returns a pointer to the MI that def's the register or nullptr otherwise. Previously, we unconditionally dereferenced it which caused a nullptr dereference when the register was live-in but now we check for the nullptr first.

dsanders: There's only a couple of them in the test at the moment but here's one of the getVRegDef's.
qcolombetUnsubmitted
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Here is it, I missed it with my previous search :).

I would rather have a check before the getVRegDef whether the register is a vreg or not.
I know getVRegDef works with PhysReg, but in practice we try not to call it on then, because it is strange :).

qcolombet: Here is it, I missed it with my previous search :). I would rather have a check before the…
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_MUL) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_MUL) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Operand 1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Operand 1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: (((MI1.getOpcode() == TargetOpcode::G_ADD) && // CHECK-NEXT: (((MI1->getOpcode() == TargetOpcode::G_ADD) &&
// CHECK-NEXT: ((/* Operand 0 */ (MRI.getType(MI1.getOperand(0).getReg()) == (LLT::scalar(32))))) && // CHECK-NEXT: ((/* Operand 0 */ (MRI.getType(MI1->getOperand(0).getReg()) == (LLT::scalar(32))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI1.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI1->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src2 */ (MRI.getType(MI1.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src2 */ (MRI.getType(MI1->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(2).getReg(), MRI, TRI)))))) // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1->getOperand(2).getReg(), MRI, TRI))))))
// CHECK-NEXT: ))) && // CHECK-NEXT: ))) &&
// CHECK-NEXT: ((/* src3 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src3 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) { // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(2).getReg(), MRI, TRI)))))) {
// CHECK-NEXT: if (!isObviouslySafeToFold(MI1)) return false; // CHECK-NEXT: if (!isObviouslySafeToFold(*MI1)) return false;
// CHECK-NEXT: // (mul:i32 (add:i32 GPR32:i32:$src1, GPR32:i32:$src2), GPR32:i32:$src3) => (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3) // CHECK-NEXT: // (mul:i32 (add:i32 GPR32:i32:$src1, GPR32:i32:$src2), GPR32:i32:$src3) => (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.add(MI1.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI1->getOperand(1)/*src1*/);
// CHECK-NEXT: MIB.add(MI1.getOperand(2)/*src2*/); // CHECK-NEXT: MIB.add(MI1->getOperand(2)/*src2*/);
// CHECK-NEXT: MIB.add(MI0.getOperand(2)/*src3*/); // CHECK-NEXT: MIB.add(MI0->getOperand(2)/*src3*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, &MI1, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, MI1, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// We also get a second rule by commutativity. // We also get a second rule by commutativity.
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: PredicateBitset ExpectedFeatures = {Feature_HasABit}; // CHECK-NEXT: PredicateBitset ExpectedFeatures = {Feature_HasABit};
// CHECK-NEXT: if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures) // CHECK-NEXT: if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if (!MI0.getOperand(2).isReg()) // CHECK-NEXT: if (!MI0->getOperand(2).isReg())
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(2).getReg()); // CHECK-NEXT: MachineInstr *MI1 = MRI.getVRegDef(MI0->getOperand(2).getReg());
// CHECK-NEXT: if (MI1.getNumOperands() < 3) // CHECK-NEXT: if (!MI1 || MI1->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_MUL) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_MUL) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src3 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src3 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: (((MI1.getOpcode() == TargetOpcode::G_ADD) && // CHECK-NEXT: (((MI1->getOpcode() == TargetOpcode::G_ADD) &&
// CHECK-NEXT: ((/* Operand 0 */ (MRI.getType(MI1.getOperand(0).getReg()) == (LLT::scalar(32))))) && // CHECK-NEXT: ((/* Operand 0 */ (MRI.getType(MI1->getOperand(0).getReg()) == (LLT::scalar(32))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI1.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI1->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src2 */ (MRI.getType(MI1.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src2 */ (MRI.getType(MI1->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(2).getReg(), MRI, TRI)))))) // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1->getOperand(2).getReg(), MRI, TRI))))))
// CHECK-NEXT: )))) { // CHECK-NEXT: )))) {
// CHECK-NEXT: if (!isObviouslySafeToFold(MI1)) return false; // CHECK-NEXT: if (!isObviouslySafeToFold(*MI1)) return false;
// CHECK-NEXT: // (mul:i32 GPR32:i32:$src3, (add:i32 GPR32:i32:$src1, GPR32:i32:$src2)) => (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3) // CHECK-NEXT: // (mul:i32 GPR32:i32:$src3, (add:i32 GPR32:i32:$src1, GPR32:i32:$src2)) => (MULADD:i32 GPR32:i32:$src1, GPR32:i32:$src2, GPR32:i32:$src3)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.add(MI1.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI1->getOperand(1)/*src1*/);
// CHECK-NEXT: MIB.add(MI1.getOperand(2)/*src2*/); // CHECK-NEXT: MIB.add(MI1->getOperand(2)/*src2*/);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src3*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src3*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, &MI1, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, MI1, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3), def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
[(set GPR32:$dst, [(set GPR32:$dst,
(mul (add GPR32:$src1, GPR32:$src2), GPR32:$src3))]>, (mul (add GPR32:$src1, GPR32:$src2), GPR32:$src3))]>,
Requires<[HasA]>; Requires<[HasA]>;
//===- Test another simple pattern with regclass operands. ----------------===// //===- Test another simple pattern with regclass operands. ----------------===//
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: PredicateBitset ExpectedFeatures = {Feature_HasABit, Feature_HasBBit, Feature_HasCBit}; // CHECK-NEXT: PredicateBitset ExpectedFeatures = {Feature_HasABit, Feature_HasBBit, Feature_HasCBit};
// CHECK-NEXT: if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures) // CHECK-NEXT: if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_MUL) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_MUL) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) { // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(2).getReg(), MRI, TRI)))))) {
// CHECK-NEXT: // (mul:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (MUL:i32 GPR32:i32:$src2, GPR32:i32:$src1) // CHECK-NEXT: // (mul:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (MUL:i32 GPR32:i32:$src2, GPR32:i32:$src1)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MUL)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MUL));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.add(MI0.getOperand(2)/*src2*/); // CHECK-NEXT: MIB.add(MI0->getOperand(2)/*src2*/);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src1*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1), def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
[(set GPR32:$dst, (mul GPR32:$src1, GPR32:$src2))]>, [(set GPR32:$dst, (mul GPR32:$src1, GPR32:$src2))]>,
Requires<[HasA, HasB, HasC]>; Requires<[HasA, HasB, HasC]>;
//===- Test a pattern with ComplexPattern operands. -----------------------===// //===- Test a pattern with ComplexPattern operands. -----------------------===//
// //
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_SUB) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_SUB) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((Renderer0 = selectComplexPattern(MI0.getOperand(2))))))) { // CHECK-NEXT: ((Renderer0 = selectComplexPattern(MI0->getOperand(2))))))) {
// CHECK-NEXT: // (sub:i32 GPR32:i32:$src1, complex:i32:$src2) => (INSN1:i32 GPR32:i32:$src1, complex:i32:$src2) // CHECK-NEXT: // (sub:i32 GPR32:i32:$src1, complex:i32:$src2) => (INSN1:i32 GPR32:i32:$src1, complex:i32:$src2)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN1)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN1));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src1*/);
// CHECK-NEXT: Renderer0(MIB); // CHECK-NEXT: Renderer0(MIB);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
def INSN1 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>; def INSN1 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
def : Pat<(sub GPR32:$src1, complex:$src2), (INSN1 GPR32:$src1, complex:$src2)>; def : Pat<(sub GPR32:$src1, complex:$src2), (INSN1 GPR32:$src1, complex:$src2)>;
//===- Test a simple pattern with a default operand. ----------------------===// //===- Test a simple pattern with a default operand. ----------------------===//
// //
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_XOR) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_XOR) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: (isOperandImmEqual(MI0.getOperand(2), -2, MRI))))) { // CHECK-NEXT: (isOperandImmEqual(MI0->getOperand(2), -2, MRI))))) {
// CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -2:i32) => (XORI:i32 GPR32:i32:$src1) // CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -2:i32) => (XORI:i32 GPR32:i32:$src1)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORI)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORI));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.addImm(-1); // CHECK-NEXT: MIB.addImm(-1);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src1*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
// The -2 is just to distinguish it from the 'not' case below. // The -2 is just to distinguish it from the 'not' case below.
def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1), def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
[(set GPR32:$dst, (xor GPR32:$src1, -2))]>; [(set GPR32:$dst, (xor GPR32:$src1, -2))]>;
//===- Test a simple pattern with a default register operand. -------------===// //===- Test a simple pattern with a default register operand. -------------===//
// //
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_XOR) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_XOR) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: (isOperandImmEqual(MI0.getOperand(2), -3, MRI))))) { // CHECK-NEXT: (isOperandImmEqual(MI0->getOperand(2), -3, MRI))))) {
// CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -3:i32) => (XOR:i32 GPR32:i32:$src1) // CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -3:i32) => (XOR:i32 GPR32:i32:$src1)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XOR)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XOR));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.addReg(MyTarget::R0); // CHECK-NEXT: MIB.addReg(MyTarget::R0);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src1*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
// The -3 is just to distinguish it from the 'not' case below and the other default op case above. // The -3 is just to distinguish it from the 'not' case below and the other default op case above.
def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1), def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
[(set GPR32:$dst, (xor GPR32:$src1, -3))]>; [(set GPR32:$dst, (xor GPR32:$src1, -3))]>;
//===- Test a simple pattern with a multiple default operands. ------------===// //===- Test a simple pattern with a multiple default operands. ------------===//
// //
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_XOR) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_XOR) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: (isOperandImmEqual(MI0.getOperand(2), -4, MRI))))) { // CHECK-NEXT: (isOperandImmEqual(MI0->getOperand(2), -4, MRI))))) {
// CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -4:i32) => (XORlike:i32 GPR32:i32:$src1) // CHECK-NEXT: // (xor:i32 GPR32:i32:$src1, -4:i32) => (XORlike:i32 GPR32:i32:$src1)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORlike)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORlike));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.addImm(-1); // CHECK-NEXT: MIB.addImm(-1);
// CHECK-NEXT: MIB.addReg(MyTarget::R0); // CHECK-NEXT: MIB.addReg(MyTarget::R0);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*src1*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*src1*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
// The -4 is just to distinguish it from the other 'not' cases. // The -4 is just to distinguish it from the other 'not' cases.
def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1), def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
[(set GPR32:$dst, (xor GPR32:$src1, -4))]>; [(set GPR32:$dst, (xor GPR32:$src1, -4))]>;
//===- Test a simple pattern with constant immediate operands. ------------===// //===- Test a simple pattern with constant immediate operands. ------------===//
// //
// This must precede the 3-register variants because constant immediates have // This must precede the 3-register variants because constant immediates have
// priority over register banks. // priority over register banks.
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 3) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 3)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_XOR) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_XOR) &&
// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* dst */ (MRI.getType(MI0->getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Wm */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Wm */ (MRI.getType(MI0->getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) && // CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0->getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) && // CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(MI0->getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: (isOperandImmEqual(MI0.getOperand(2), -1, MRI))))) { // CHECK-NEXT: (isOperandImmEqual(MI0->getOperand(2), -1, MRI))))) {
// CHECK-NEXT: // (xor:i32 GPR32:i32:$Wm, -1:i32) => (ORN:i32 R0:i32, GPR32:i32:$Wm) // CHECK-NEXT: // (xor:i32 GPR32:i32:$Wm, -1:i32) => (ORN:i32 R0:i32, GPR32:i32:$Wm)
// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::ORN)); // CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::ORN));
// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/); // CHECK-NEXT: MIB.add(MI0->getOperand(0)/*dst*/);
// CHECK-NEXT: MIB.addReg(MyTarget::R0); // CHECK-NEXT: MIB.addReg(MyTarget::R0);
// CHECK-NEXT: MIB.add(MI0.getOperand(1)/*Wm*/); // CHECK-NEXT: MIB.add(MI0->getOperand(1)/*Wm*/);
// CHECK-NEXT: for (const auto *FromMI : {&MI0, }) // CHECK-NEXT: for (const auto *FromMI : {MI0, })
// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands()) // CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
// CHECK-NEXT: MIB.addMemOperand(MMO); // CHECK-NEXT: MIB.addMemOperand(MMO);
// CHECK-NEXT: I.eraseFromParent(); // CHECK-NEXT: I.eraseFromParent();
// CHECK-NEXT: MachineInstr &NewI = *MIB; // CHECK-NEXT: MachineInstr &NewI = *MIB;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
//===- Test a pattern with an MBB operand. --------------------------------===// //===- Test a pattern with an MBB operand. --------------------------------===//
// CHECK-LABEL: if ([&]() { // CHECK-LABEL: if ([&]() {
// CHECK-NEXT: MachineInstr &MI0 = I; // CHECK-NEXT: MachineInstr *MI0 = &I;
// CHECK-NEXT: if (MI0.getNumOperands() < 1) // CHECK-NEXT: if (!MI0 || MI0->getNumOperands() < 1)
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_BR) && // CHECK-NEXT: if ((MI0->getOpcode() == TargetOpcode::G_BR) &&
// CHECK-NEXT: ((/* target */ (MI0.getOperand(0).isMBB())))) { // CHECK-NEXT: ((/* target */ (MI0->getOperand(0).isMBB())))) {
// CHECK-NEXT: // (br (bb:Other):$target) => (BR (bb:Other):$target) // CHECK-NEXT: // (br (bb:Other):$target) => (BR (bb:Other):$target)
// CHECK-NEXT: I.setDesc(TII.get(MyTarget::BR)); // CHECK-NEXT: I.setDesc(TII.get(MyTarget::BR));
// CHECK-NEXT: MachineInstr &NewI = I; // CHECK-NEXT: MachineInstr &NewI = I;
// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI); // CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
// CHECK-NEXT: return true; // CHECK-NEXT: return true;
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: return false; // CHECK-NEXT: return false;
// CHECK-NEXT: }()) { return true; } // CHECK-NEXT: }()) { return true; }
def BR : I<(outs), (ins unknown:$target), def BR : I<(outs), (ins unknown:$target),
[(br bb:$target)]>; [(br bb:$target)]>;

utils/TableGen/GlobalISelEmitter.cpp

Show First 20 Lines • Show All 448 Lines • ▼ Show 20 Linespublic:
const StringRef getSymbolicName() const { return SymbolicName; } const StringRef getSymbolicName() const { return SymbolicName; }
void setSymbolicName(StringRef Name) { void setSymbolicName(StringRef Name) {
assert(SymbolicName.empty() && "Operand already has a symbolic name"); assert(SymbolicName.empty() && "Operand already has a symbolic name");
SymbolicName = Name; SymbolicName = Name;
} }
unsigned getOperandIndex() const { return OpIdx; } unsigned getOperandIndex() const { return OpIdx; }
std::string getOperandExpr(StringRef InsnVarName) const { std::string getOperandExpr(StringRef InsnVarName) const {
return (InsnVarName + ".getOperand(" + llvm::to_string(OpIdx) + ")").str(); return (InsnVarName + "->getOperand(" + llvm::to_string(OpIdx) + ")").str();
} }
Optional<const OperandMatcher *> Optional<const OperandMatcher *>
getOptionalOperand(StringRef DesiredSymbolicName) const { getOptionalOperand(StringRef DesiredSymbolicName) const {
assert(!DesiredSymbolicName.empty() && "Cannot lookup unnamed operand"); assert(!DesiredSymbolicName.empty() && "Cannot lookup unnamed operand");
if (DesiredSymbolicName == SymbolicName) if (DesiredSymbolicName == SymbolicName)
return this; return this;
for (const auto &OP : predicates()) { for (const auto &OP : predicates()) {
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines InstructionOpcodeMatcher(const CodeGenInstruction *I)
: InstructionPredicateMatcher(IPM_Opcode), I(I) {} : InstructionPredicateMatcher(IPM_Opcode), I(I) {}
static bool classof(const InstructionPredicateMatcher *P) { static bool classof(const InstructionPredicateMatcher *P) {
return P->getKind() == IPM_Opcode; return P->getKind() == IPM_Opcode;
} }
void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule, void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
StringRef InsnVarName) const override { StringRef InsnVarName) const override {
OS << InsnVarName << ".getOpcode() == " << I->Namespace OS << InsnVarName << "->getOpcode() == " << I->Namespace
<< "::" << I->TheDef->getName(); << "::" << I->TheDef->getName();
} }
/// Compare the priority of this object and B. /// Compare the priority of this object and B.
/// ///
/// Returns true if this object is more important than B. /// Returns true if this object is more important than B.
bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const override { bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const override {
if (InstructionPredicateMatcher::isHigherPriorityThan(B)) if (InstructionPredicateMatcher::isHigherPriorityThan(B))
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linespublic:
OperandVec::const_iterator operands_end() const { return Operands.end(); } OperandVec::const_iterator operands_end() const { return Operands.end(); }
iterator_range<OperandVec::const_iterator> operands() const { iterator_range<OperandVec::const_iterator> operands() const {
return make_range(operands_begin(), operands_end()); return make_range(operands_begin(), operands_end());
} }
/// Emit C++ statements to check the shape of the match and capture /// Emit C++ statements to check the shape of the match and capture
/// instructions into local variables. /// instructions into local variables.
void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule, StringRef Expr) { void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule, StringRef Expr) {
OS << "if (" << Expr << ".getNumOperands() < " << getNumOperands() << ")\n" OS << "if (!" << Expr << " || " << Expr << "->getNumOperands() < "
<< getNumOperands() << ")\n"
<< " return false;\n"; << " return false;\n";
for (const auto &Operand : Operands) { for (const auto &Operand : Operands) {
Operand->emitCxxCaptureStmts(OS, Rule, Operand->getOperandExpr(Expr)); Operand->emitCxxCaptureStmts(OS, Rule, Operand->getOperandExpr(Expr));
} }
} }
/// Emit a C++ expression that tests whether the instruction named in /// Emit a C++ expression that tests whether the instruction named in
/// InsnVarName matches all the predicates and all the operands. /// InsnVarName matches all the predicates and all the operands.
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Linespublic:
} }
void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule, void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule,
StringRef OperandExpr) const override { StringRef OperandExpr) const override {
OS << "if (!" << OperandExpr + ".isReg())\n" OS << "if (!" << OperandExpr + ".isReg())\n"
<< " return false;\n"; << " return false;\n";
std::string InsnVarName = Rule.defineInsnVar( std::string InsnVarName = Rule.defineInsnVar(
OS, *InsnMatcher, OS, *InsnMatcher,
("*MRI.getVRegDef(" + OperandExpr + ".getReg())").str()); ("MRI.getVRegDef(" + OperandExpr + ".getReg())").str());
InsnMatcher->emitCxxCaptureStmts(OS, Rule, InsnVarName); InsnMatcher->emitCxxCaptureStmts(OS, Rule, InsnVarName);
} }
void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule, void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
StringRef OperandExpr) const override { StringRef OperandExpr) const override {
OperandExpr = Rule.getInsnVarName(*InsnMatcher); OperandExpr = Rule.getInsnVarName(*InsnMatcher);
OS << "("; OS << "(";
InsnMatcher->emitCxxPredicateExpr(OS, Rule, OperandExpr); InsnMatcher->emitCxxPredicateExpr(OS, Rule, OperandExpr);
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 LinesKind &RuleMatcher::addAction(Args &&... args) {
Actions.emplace_back(llvm::make_unique<Kind>(std::forward<Args>(args)...)); Actions.emplace_back(llvm::make_unique<Kind>(std::forward<Args>(args)...));
return *static_cast<Kind *>(Actions.back().get()); return *static_cast<Kind *>(Actions.back().get());
} }
std::string RuleMatcher::defineInsnVar(raw_ostream &OS, std::string RuleMatcher::defineInsnVar(raw_ostream &OS,
const InstructionMatcher &Matcher, const InstructionMatcher &Matcher,
StringRef Value) { StringRef Value) {
std::string InsnVarName = "MI" + llvm::to_string(NextInsnVarID++); std::string InsnVarName = "MI" + llvm::to_string(NextInsnVarID++);
OS << "MachineInstr &" << InsnVarName << " = " << Value << ";\n"; OS << "MachineInstr *" << InsnVarName << " = " << Value << ";\n";
InsnVariableNames[&Matcher] = InsnVarName; InsnVariableNames[&Matcher] = InsnVarName;
return InsnVarName; return InsnVarName;
} }
StringRef RuleMatcher::getInsnVarName(const InstructionMatcher &InsnMatcher) const { StringRef RuleMatcher::getInsnVarName(const InstructionMatcher &InsnMatcher) const {
const auto &I = InsnVariableNames.find(&InsnMatcher); const auto &I = InsnVariableNames.find(&InsnMatcher);
if (I != InsnVariableNames.end()) if (I != InsnVariableNames.end())
return I->second; return I->second;
llvm_unreachable("Matched Insn was not captured in a local variable"); llvm_unreachable("Matched Insn was not captured in a local variable");
} }
/// Emit a C++ initializer_list containing references to every matched instruction. /// Emit a C++ initializer_list containing references to every matched instruction.
void RuleMatcher::emitCxxCapturedInsnList(raw_ostream &OS) { void RuleMatcher::emitCxxCapturedInsnList(raw_ostream &OS) {
SmallVector<StringRef, 2> Names; SmallVector<StringRef, 2> Names;
for (const auto &Pair : InsnVariableNames) for (const auto &Pair : InsnVariableNames)
Names.push_back(Pair.second); Names.push_back(Pair.second);
std::sort(Names.begin(), Names.end()); std::sort(Names.begin(), Names.end());
OS << "{"; OS << "{";
for (const auto &Name : Names) for (const auto &Name : Names)
OS << "&" << Name << ", "; OS << Name << ", ";
OS << "}"; OS << "}";
} }
/// Emit C++ statements to check the shape of the match and capture /// Emit C++ statements to check the shape of the match and capture
/// instructions into local variables. /// instructions into local variables.
void RuleMatcher::emitCxxCaptureStmts(raw_ostream &OS, StringRef Expr) { void RuleMatcher::emitCxxCaptureStmts(raw_ostream &OS, StringRef Expr) {
assert(Matchers.size() == 1 && "Cannot handle multi-root matchers yet"); assert(Matchers.size() == 1 && "Cannot handle multi-root matchers yet");
std::string InsnVarName = defineInsnVar(OS, *Matchers.front(), Expr); std::string InsnVarName = defineInsnVar(OS, *Matchers.front(), Expr);
Show All 27 Lines for (const auto &Predicate : RequiredFeatures) {
OS << Separator << I->second.getEnumBitName(); OS << Separator << I->second.getEnumBitName();
Separator = ", "; Separator = ", ";
} }
OS << "};\n"; OS << "};\n";
OS << "if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures)\n" OS << "if ((AvailableFeatures & ExpectedFeatures) != ExpectedFeatures)\n"
<< " return false;\n"; << " return false;\n";
} }
emitCxxCaptureStmts(OS, "I"); emitCxxCaptureStmts(OS, "&I");
OS << " if ("; OS << " if (";
Matchers.front()->emitCxxPredicateExpr(OS, *this, Matchers.front()->emitCxxPredicateExpr(OS, *this,
getInsnVarName(*Matchers.front())); getInsnVarName(*Matchers.front()));
OS << ") {\n"; OS << ") {\n";
// We must also check if it's safe to fold the matched instructions. // We must also check if it's safe to fold the matched instructions.
if (InsnVariableNames.size() >= 2) { if (InsnVariableNames.size() >= 2) {
for (const auto &Pair : InsnVariableNames) { for (const auto &Pair : InsnVariableNames) {
// Skip the root node since it isn't moving anywhere. Everything else is // Skip the root node since it isn't moving anywhere. Everything else is
// sinking to meet it. // sinking to meet it.
if (Pair.first == Matchers.front().get()) if (Pair.first == Matchers.front().get())
continue; continue;
// Reject the difficult cases until we have a more accurate check. // Reject the difficult cases until we have a more accurate check.
OS << " if (!isObviouslySafeToFold(" << Pair.second OS << " if (!isObviouslySafeToFold(*" << Pair.second
<< ")) return false;\n"; << ")) return false;\n";
// FIXME: Emit checks to determine it's _actually_ safe to fold and/or // FIXME: Emit checks to determine it's _actually_ safe to fold and/or
// account for unsafe cases. // account for unsafe cases.
// //
// Example: // Example:
// MI1--> %0 = ... // MI1--> %0 = ...
// %1 = ... %0 // %1 = ... %0
▲ Show 20 Lines • Show All 659 Lines • Show Last 20 Lines