Switch AArch64 to use reduction intrinsics
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Authored by aemerson on Apr 19 2017, 2:47 PM.

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Reviewers

rengolin
javed.absar
aemerson

Commits

rG816542ceb39e: [AArch64] Enable use of reduction intrinsics.
rL302678: [AArch64] Enable use of reduction intrinsics.

Summary

This patch enables the use of the experimental reduction intrinsics from D30086 for AArch64.

The existing idiom recognition for the shufflevector sequence is removed and tests updated to use the new form.

Diff Detail

Repository: rL LLVM

Event Timeline

aemerson created this revision.Apr 19 2017, 2:47 PM

Herald added a reviewer: javed.absar. · View Herald TranscriptApr 19 2017, 2:47 PM

aemerson added a parent revision: D30086: Add generic IR vector reductions.Apr 19 2017, 2:53 PM

tschuett added a subscriber: tschuett.Apr 19 2017, 11:05 PM

As soon as the dependency patch is approved, this one looks ok.

Did you submit the patch that will make the MC layer recognise these patterns into the actual instructions?

lib/Target/AArch64/AArch64TargetTransformInfo.cpp
784	For now, shouldn't this be `== 128`?

No changes are needed on the MC side. The same target-specific reduction DAG nodes (e.g. AArch64ISD::UADDV) should be created and from then on everything should work as before.

lib/Target/AArch64/AArch64TargetTransformInfo.cpp
784	It's needed because vectors can be oversize, e.g. v8i32. We still want to use reductions for that as legalisation will split the vector later.
791	FYI, I haven't yet updated this version of the patch, the current generic reduction patch combines the two hooks into one so this function will merge into the one above when I do.