[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia

[mcgrathr]

Summary

This mode is just like -mcmodel=small except that it moves the
thread pointer from TPIDR_EL0 to TPIDR_EL1.

[t.p.northover]

This seems to be changing behaviour outside TPIDR_EL0, but only that gets tested so we probably need more tests of normal operation.

lib/Target/AArch64/AArch64FastISel.cpp

3150 ↗

(On Diff #93933)

I think "aka" is a bit strong. There really is a difference, even if it doesn't affect this decision.

lib/Target/AArch64/AArch64Subtarget.cpp

152–153 ↗

(On Diff #93933)

It might be an idea to put this in a function like useSmallAddressing (or whatever bikeshed you prefer) that checks the triple too. Kernel mode seems like something reasonable kernels could disagree over.

[mcgrathr]

The intent is no changes whatosever except for using TPIDR_EL1.
All the other changes are just to accept CodeModel::Kernel and treat it exactly like CodeModel::Small. Do you see something where other behavior changes under -code-model=kernel?
Since before this change, -code-model=kernel was disallowed altogether and now it's allowed only for aarch64-fuchsia where it is the same as =small in almost all regards, the "aka small" comment seems correct to me.

I will make the change to consolidate the logic into a helper function.

[t.p.northover]

Do you see something where other behavior changes under -code-model=kernel?

The behaviour change is that kernel is now supported as a mode. We want tests to make sure no-one goes in and decides that they want their kernel to use large addressing (for example) without getting told off when they run "ninja check". Adding tests might well be as simple as putting a new RUN line in an existing test of globals that also passes "-code-model=kernel".

it is the same as =small in almost all regards, the "aka small" comment seems correct to me.

IMO "aka" implies complete identity.

[mcgrathr]

Added useSmallAddressing() helper method.

[mcgrathr]

Added test runs using -mtriple=aarch64-fuchsia -code-model=kernel.

[mcgrathr]

I think I've addressed all the requests. Please take another look.

[t.p.northover]

Thanks Roland, this looks fine to me now.

llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

MachineInstrBuilder MIB2 =
             .addImm(0);
 
     transferImpOps(MI, MIB1, MIB2);
     MI.eraseFromParent();
     return true;
   }
   case AArch64::MOVbaseTLS: {
     unsigned DstReg = MI.getOperand(0).getReg();
+    auto SysReg = AArch64SysReg::TPIDR_EL0;
+    MachineFunction *MF = MBB.getParent();
+    if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
+        MF->getTarget().getCodeModel() == CodeModel::Kernel)
+      SysReg = AArch64SysReg::TPIDR_EL1;
     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
-        .addImm(AArch64SysReg::TPIDR_EL0);
+        .addImm(SysReg);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::MOVi32imm:
     return expandMOVImm(MBB, MBBI, 32);
   case AArch64::MOVi64imm:
     return expandMOVImm(MBB, MBBI, 64);

llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp

 
 unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
   // We can't handle thread-local variables quickly yet.
   if (GV->isThreadLocal())
     return 0;
 
   // MachO still uses GOT for large code-model accesses, but ELF requires
   // movz/movk sequences, which FastISel doesn't handle yet.
-  if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
+  if (!Subtarget->useSmallAddressing() && !Subtarget->isTargetMachO())
     return 0;
 
   unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
 
   EVT DestEVT = TLI.getValueType(DL, GV->getType(), true);
   if (!DestEVT.isSimple())
     return 0;
 
bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
   if (!Callee && !Symbol)
     return false;
 
   // Allow SelectionDAG isel to handle tail calls.
   if (IsTailCall)
     return false;
 
   CodeModel::Model CM = TM.getCodeModel();
-  // Only support the small and large code model.
-  if (CM != CodeModel::Small && CM != CodeModel::Large)
+  // Only support the small-addressing and large code models.
+  if (CM != CodeModel::Large && !Subtarget->useSmallAddressing())
     return false;
 
   // FIXME: Add large code model support for ELF.
   if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
     return false;
 
   // Let SDISel handle vararg functions.
   if (IsVarArg)
bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
 
   // Handle the arguments now that we've gotten them.
   unsigned NumBytes;
   if (!processCallArgs(CLI, OutVTs, NumBytes))
     return false;
 
   // Issue the call.
   MachineInstrBuilder MIB;
-  if (CM == CodeModel::Small) {
+  if (Subtarget->useSmallAddressing()) {
     const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
     if (Symbol)
       MIB.addSym(Symbol, 0);
     else if (Addr.getGlobalValue())
       MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
     else if (Addr.getReg()) {
       unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
 
   return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
 }
 
 SDValue
 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
                                                 SelectionDAG &DAG) const {
   assert(Subtarget->isTargetELF() && "This function expects an ELF target");
-  assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
+  assert(Subtarget->useSmallAddressing() &&
          "ELF TLS only supported in small memory model");
   // Different choices can be made for the maximum size of the TLS area for a
   // module. For the small address model, the default TLS size is 16MiB and the
   // maximum TLS size is 4GiB.
   // FIXME: add -mtls-size command line option and make it control the 16MiB
   // vs. 4GiB code sequence generation.
   const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
 

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

public:
   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 
   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   bool useAA() const override { return UseAA; }
 
+  bool useSmallAddressing() const {
+    switch (TLInfo.getTargetMachine().getCodeModel()) {
+      case CodeModel::Kernel:
+        // Kernel is currently allowed only for Fuchsia targets,
+        // where it is the same as Small for almost all purposes.
+      case CodeModel::Small:
+        return true;
+      default:
+        return false;
+    }
+  }
+
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   /// ClassifyGlobalReference - Find the target operand flags that describe
   /// how a global value should be referenced for the current subtarget.
   unsigned char ClassifyGlobalReference(const GlobalValue *GV,
                                         const TargetMachine &TM) const;

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
   // MachO large model always goes via a GOT, simply to get a single 8-byte
   // absolute relocation on all global addresses.
   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
     return AArch64II::MO_GOT;
 
   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
     return AArch64II::MO_GOT;
 
-  // The small code mode's direct accesses use ADRP, which cannot necessarily
-  // produce the value 0 (if the code is above 4GB).
-  if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
+  // The small code model's direct accesses use ADRP, which cannot
+  // necessarily produce the value 0 (if the code is above 4GB).
+  if (useSmallAddressing() && GV->hasExternalWeakLinkage())
     return AArch64II::MO_GOT;
 
   return AArch64II::MO_NO_FLAG;
 }
 
 /// This function returns the name of a function which has an interface
 /// like the non-standard bzero function, if such a function exists on
 /// the current subtarget and it is considered prefereable over

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
 
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
   // The default MCJIT memory managers make no guarantees about where they can
   // find an executable page; JITed code needs to be able to refer to globals
   // no matter how far away they are.
   else if (CM == CodeModel::JITDefault)
     CM = CodeModel::Large;
-  else if (CM != CodeModel::Small && CM != CodeModel::Large)
+  else if (CM != CodeModel::Small && CM != CodeModel::Large) {
+    if (!TT.isOSFuchsia())
       report_fatal_error(
           "Only small and large code models are allowed on AArch64");
+    else if (CM != CodeModel::Kernel)
+      report_fatal_error(
+          "Only small, kernel, and large code models are allowed on AArch64");
+  }
 }
 
 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)

llvm/trunk/test/CodeGen/AArch64/arm64-builtins-linux.ll

 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-fuchsia | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-fuchsia -code-model=kernel | FileCheck --check-prefix=FUCHSIA-KERNEL %s
 
 ; Function Attrs: nounwind readnone
 declare i8* @llvm.thread.pointer() #1
 
 define i8* @thread_pointer() {
 ; CHECK: thread_pointer:
 ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
+; FUCHSIA-KERNEL: thread_pointer:
+; FUCHSIA-KERNEL: mrs {{x[0-9]+}}, TPIDR_EL1
   %1 = tail call i8* @llvm.thread.pointer()
   ret i8* %1
 }

llvm/trunk/test/CodeGen/AArch64/arm64-elf-globals.ll

 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -mcpu=cyclone | FileCheck %s
 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
 ; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
 ; RUN: llc -mtriple=arm64-linux-gnu -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
+; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -o - %s -mcpu=cyclone | FileCheck %s
+; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
+; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
+; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
 
 @var8 = external global i8, align 1
 @var16 = external global i16, align 2
 @var32 = external global i32, align 4
 @var64 = external global i64, align 8
 
 define i8 @test_i8(i8 %new) {
   %val = load i8, i8* @var8, align 1

llvm/trunk/test/CodeGen/AArch64/stack-protector-target.ll

 ; Test target-specific stack cookie location.
 ; RUN: llc -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefix=ANDROID-AARCH64 %s
-; RUN: llc -mtriple=aarch64-fuchsia < %s -o - | FileCheck --check-prefix=FUCHSIA-AARCH64 %s
+; RUN: llc -mtriple=aarch64-fuchsia < %s -o - | FileCheck --check-prefixes=FUCHSIA-AARCH64-COMMON,FUCHSIA-AARCH64-USER %s
+; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel < %s -o - | FileCheck --check-prefixes=FUCHSIA-AARCH64-COMMON,FUCHSIA-AARCH64-KERNEL %s
 
 define void @_Z1fv() sspreq {
 entry:
   %x = alloca i32, align 4
   %0 = bitcast i32* %x to i8*
   call void @_Z7CapturePi(i32* nonnull %x)
   ret void
 }
 
 declare void @_Z7CapturePi(i32*)
 
 ; ANDROID-AARCH64: mrs [[A:.*]], TPIDR_EL0
 ; ANDROID-AARCH64: ldr [[B:.*]], {{\[}}[[A]], #40]
 ; ANDROID-AARCH64: str [[B]], [sp,
 ; ANDROID-AARCH64: ldr [[C:.*]], {{\[}}[[A]], #40]
 ; ANDROID-AARCH64: ldr [[D:.*]], [sp,
 ; ANDROID-AARCH64: cmp [[C]], [[D]]
 
-; FUCHSIA-AARCH64: mrs [[A:.*]], TPIDR_EL0
-; FUCHSIA-AARCH64: ldur [[B:.*]], {{\[}}[[A]], #-16]
-; FUCHSIA-AARCH64: str [[B]], [sp,
-; FUCHSIA-AARCH64: ldur [[C:.*]], {{\[}}[[A]], #-16]
-; FUCHSIA-AARCH64: ldr [[D:.*]], [sp,
-; FUCHSIA-AARCH64: cmp [[C]], [[D]]
+; FUCHSIA-AARCH64-USER: mrs [[A:.*]], TPIDR_EL0
+; FUCHSIA-AARCH64-KERNEL: mrs [[A:.*]], TPIDR_EL1
+; FUCHSIA-AARCH64-COMMON: ldur [[B:.*]], {{\[}}[[A]], #-16]
+; FUCHSIA-AARCH64-COMMON: str [[B]], [sp,
+; FUCHSIA-AARCH64-COMMON: ldur [[C:.*]], {{\[}}[[A]], #-16]
+; FUCHSIA-AARCH64-COMMON: ldr [[D:.*]], [sp,
+; FUCHSIA-AARCH64-COMMON: cmp [[C]], [[D]]