AMDGPU: Add way to specify that instructions zero high 16-bits

[arsenm]

Fix VOP3 outputs

[arsenm]

Fix VOP3 output register printing hack

[arsenm]

Rebase

[rampitec]

lib/Target/AMDGPU/SIInstrInfo.cpp

4549

Given that fixme, can we produce these instructions now? If yes, this code is dangerous.

[arsenm]

This needs to be redone differently with subregisters

lib/Target/AMDGPU/SIDefines.h

enum OperandType {
     OPERAND_INPUT_MODS,
 
     // Operand for SDWA instructions
     OPERAND_SDWA_SRC,
     OPERAND_SDWA_VOPC_DST,
 
     /// Operand with 32-bit immediate that uses the constant bus.
     OPERAND_KIMM32,
-    OPERAND_KIMM16
+    OPERAND_KIMM16,
+
+    // Output register operand with 16-bit output.
+    OPERAND_REG_DEF16
   };
 }
 
 // Input operand modifiers bit-masks
 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
 namespace SISrcMods {
   enum {
    NEG = 1 << 0,   // Floating-point negate modifier

lib/Target/AMDGPU/SIInstrFormats.td

 }
 
 class Enc64 {
   field bits<64> Inst;
   int Size = 8;
 }
 
 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
+class VOP3DstOperand <RegisterClass rc> : RegisterOperand <rc>;
+
+let OperandNamespace = "AMDGPU" in {
+def VOPDstOperand16 : VOPDstOperand<VGPR_32> {
+  let OperandType = "OPERAND_REG_DEF16";
+}
+
+def VOP3DstOperand16 : VOP3DstOperand<VGPR_32> {
+  let OperandType = "OPERAND_REG_DEF16";
+}
+
+}
+
+def VOPDstOperand32 : VOPDstOperand<VGPR_32>;
+def VOPDstOperand64 : VOPDstOperand<VReg_64>;
+def VOPDstOperand128 : VOPDstOperand<VReg_128>;
 
 class VINTRPe <bits<2> op> : Enc32 {
   bits<8> vdst;
   bits<8> vsrc;
   bits<2> attrchan;
   bits<6> attr;
 
   let Inst{7-0} = vsrc;

lib/Target/AMDGPU/SIInstrInfo.cpp

void SIInstrInfo::computeKnownBits(const MachineRegisterInfo &MRI,
   case AMDGPU::BUFFER_LOAD_USHORT_OFFSET:
   case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN:
   case AMDGPU::BUFFER_LOAD_USHORT_OFFEN_exact:
   case AMDGPU::BUFFER_LOAD_USHORT_OFFSET_exact:
   case AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_exact: {
     KnownZero = 0xffff0000;
     return;
   }
-  default:
+  default: {
+    // XXX - Are there any 16-bit output instructions with second defs?
+    // FIXME:
+    assert(Def->getOperand(0).getReg() == Op.getReg() &&
+           Def->getOperand(0).getSubReg() == Op.getSubReg());
+    if (Def->getDesc().OpInfo[0].OperandType == AMDGPU::OPERAND_REG_DEF16) {
+      // FIXME: This isn't true for all instructions on gfx9, where some new
+      // instructions default to leaving high bits intact and there is a control
+      // bit for old instructions to change zeroing behavior.
+
+      KnownZero = 0xffff0000;
       return;
     }
+
+    return;
+    }
+  }
 }

lib/Target/AMDGPU/SIInstrInfo.td

 }
 
 // Returns the register class to use for the destination of VOP[123C]
 // instructions for the given VT.
 class getVALUDstForVT<ValueType VT> {
   RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
                           !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
                             !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
-                              !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
+                              !if(!eq(VT.Size, 16), VOPDstOperand16,
                               VOPDstOperand<SReg_64>)))); // else VT == i1
 }
 
+// Hack to avoid printing _e64 for instructions that must be VOP3.
+class getVALUDstForVT_VOP3<ValueType VT> {
+  RegisterOperand ret = !if(!eq(VT.Size, 32), VOP3DstOperand<VGPR_32>,
+                          !if(!eq(VT.Size, 128), VOP3DstOperand<VReg_128>,
+                            !if(!eq(VT.Size, 64), VOP3DstOperand<VReg_64>,
+                              !if(!eq(VT.Size, 16), VOP3DstOperand16,
+                              VOP3DstOperand<SReg_64>)))); // else VT == i1
+}
+
 // Returns the register class to use for the destination of VOP[12C]
 // instructions with SDWA extension
 class getSDWADstForVT<ValueType VT> {
   RegisterOperand ret = !if(!eq(VT.Size, 1),
                             SDWAVopcDst, // VOPC
                             VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
 }
 

lib/Target/AMDGPU/VOP3Instructions.td

class VOP3OpSelInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
 
   let AsmMatchConverter = "cvtVOP3OpSel";
 }
 
 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
 // only VOP instruction that implicitly reads VCC.
 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
 def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
-  let Outs64 = (outs DstRC.RegClass:$vdst);
+  // FIXME: Hack to stop printing _e64
+  let DstRC = getVALUDstForVT_VOP3<f32>.ret;
 }
+
 def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
-  let Outs64 = (outs DstRC.RegClass:$vdst);
+  // FIXME: Hack to stop printing _e64
+  let DstRC = getVALUDstForVT_VOP3<f64>.ret;
 }
 }
 
 class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
   list<dag> ret =
     [(set P.DstVT:$vdst,
       (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
             (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
             (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
             (i1 VCC)))];
 }
 
 class VOP3_Profile<VOPProfile P> : VOPProfile<P.ArgVT> {
   // FIXME: Hack to stop printing _e64
-  let Outs64 = (outs DstRC.RegClass:$vdst);
+  let DstRC = getVALUDstForVT_VOP3<DstVT>.ret;
   let Asm64 = " " # P.Asm64;
 }
 
 class VOP3OpSel_Profile<VOPProfile P> : VOP3_Profile<P> {
   let HasClamp = 1;
   let HasOpSel = 1;
 }
 
 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
   // v_div_scale_{f32|f64} do not support input modifiers.
   let HasModifiers = 0;
   let HasOMod = 0;
   let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
   let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
 }
 
 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
   // FIXME: Hack to stop printing _e64
-  let DstRC = RegisterOperand<VGPR_32>;
+  let DstRC = getVALUDstForVT_VOP3<f32>.ret;
 }
 
 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
   // FIXME: Hack to stop printing _e64
-  let DstRC = RegisterOperand<VReg_64>;
+  let DstRC = getVALUDstForVT_VOP3<f64>.ret;
 }
 
 def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
   // FIXME: Hack to stop printing _e64
-  let DstRC = RegisterOperand<VReg_64>;
+  let DstRC = getVALUDstForVT_VOP3<i64>.ret;
 
   let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
   let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
 }
 
 //===----------------------------------------------------------------------===//
 // VOP3 Instructions
 //===----------------------------------------------------------------------===//