This is an archive of the discontinued LLVM Phabricator instance.

Differential D31595

[AMDGPU][MC] Fix for Bug 28159 + LIT tests
ClosedPublic

Authored by dp on Apr 3 2017, 4:22 AM.

Details

Reviewers
vpykhtin
Commits
rG12194e9bec6f: [AMDGPU][MC] Corrected src0 size for s_cbranch_join
rL300055: [AMDGPU][MC] Corrected src0 size for s_cbranch_join
Summary

Corrected src0 size for s_cbranch_join

Diff Detail

Event Timeline

dp created this revision.Apr 3 2017, 4:22 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptApr 3 2017, 4:22 AM
arsenm added a comment.Apr 3 2017, 11:06 AM

Needs a test rejecting immediate input

dp updated this revision to Diff 94221.Apr 5 2017, 7:15 AM

Added negative tests

dp added a comment.Apr 12 2017, 3:29 AM

ping

vpykhtin accepted this revision.Apr 12 2017, 3:30 AM

LGTM.

This revision is now accepted and ready to land.Apr 12 2017, 3:30 AM
Closed by commit rL300055: [AMDGPU][MC] Corrected src0 size for s_cbranch_join (authored by dpreobra). · Explain WhyApr 12 2017, 5:52 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
test/
MC/
AMDGPU/
6 lines
Disassembler/
AMDGPU/
2 lines

Diff 93840

lib/Target/AMDGPU/SOPInstructions.td

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
// 32-bit input, no output. // 32-bit input, no output.
class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo < class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo <
opName, (outs), (ins SSrc_b32:$src0), opName, (outs), (ins SSrc_b32:$src0),
"$src0", pattern> { "$src0", pattern> {
let has_sdst = 0; let has_sdst = 0;
} }
class SOP1_0_32R <string opName, list<dag> pattern = []> : SOP1_Pseudo <
opName, (outs), (ins SReg_32:$src0),
"$src0", pattern> {
let has_sdst = 0;
}
class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0), opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
"$sdst, $src0", pattern "$sdst, $src0", pattern
>; >;
// 64-bit input, 32-bit output. // 64-bit input, 32-bit output.
class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0), opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
let Uses = [M0] in { let Uses = [M0] in {
def S_MOVRELS_B32 : SOP1_32 <"s_movrels_b32">; def S_MOVRELS_B32 : SOP1_32 <"s_movrels_b32">;
def S_MOVRELS_B64 : SOP1_64 <"s_movrels_b64">; def S_MOVRELS_B64 : SOP1_64 <"s_movrels_b64">;
def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">; def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">;
def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">; def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">;
} // End Uses = [M0] } // End Uses = [M0]
def S_CBRANCH_JOIN : SOP1_1 <"s_cbranch_join">; def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">;
def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">; def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">;
let Defs = [SCC] in { let Defs = [SCC] in {
def S_ABS_I32 : SOP1_32 <"s_abs_i32">; def S_ABS_I32 : SOP1_32 <"s_abs_i32">;
} // End Defs = [SCC] } // End Defs = [SCC]
def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">; def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">;
let SubtargetPredicate = HasVGPRIndexMode in { let SubtargetPredicate = HasVGPRIndexMode in {
def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> { def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {
▲ Show 20 Lines • Show All 1,019 Lines • Show Last 20 Lines

test/MC/AMDGPU/sop1.s

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Lines
s_movreld_b32 s1, s2 s_movreld_b32 s1, s2
// SICI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe] // SICI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
// VI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe] // VI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe]
s_movreld_b64 s[2:3], s[4:5] s_movreld_b64 s[2:3], s[4:5]
// SICI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe] // SICI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe]
// VI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe] // VI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
s_cbranch_join s[4:5] s_cbranch_join s4
// SICI: s_cbranch_join s[4:5] ; encoding: [0x04,0x32,0x80,0xbe] // SICI: s_cbranch_join s4 ; encoding: [0x04,0x32,0x80,0xbe]
// VI: s_cbranch_join s[4:5] ; encoding: [0x04,0x2e,0x80,0xbe] // VI: s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
s_abs_i32 s1, s2 s_abs_i32 s1, s2
// SICI: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe] // SICI: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe]
// VI: s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe] // VI: s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
s_mov_fed_b32 s1, s2 s_mov_fed_b32 s1, s2
// SICI: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe] // SICI: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe]
s_set_gpr_idx_idx s0 s_set_gpr_idx_idx s0
// VI: s_set_gpr_idx_idx s0 ; encoding: [0x00,0x32,0x80,0xbe] // VI: s_set_gpr_idx_idx s0 ; encoding: [0x00,0x32,0x80,0xbe]
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU

test/MC/Disassembler/AMDGPU/sop1_vi.txt

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
0x04 0x2b 0x82 0xbe 0x04 0x2b 0x82 0xbe
# VI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe] # VI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe]
0x02 0x2c 0x81 0xbe 0x02 0x2c 0x81 0xbe
# VI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe] # VI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
0x04 0x2d 0x82 0xbe 0x04 0x2d 0x82 0xbe
# VI: s_cbranch_join s[4:5] ; encoding: [0x04,0x2e,0x80,0xbe] # VI: s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
0x04 0x2e 0x80 0xbe 0x04 0x2e 0x80 0xbe
# VI: s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe] # VI: s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
0x02 0x30 0x81 0xbe 0x02 0x30 0x81 0xbe