[AMDGPU][MC] Fix for Bug 28159 + LIT tests

[dp]

Summary

Corrected src0 size for s_cbranch_join

[arsenm]

Needs a test rejecting immediate input

[dp]

Added negative tests

[dp]

ping

[vpykhtin]

LGTM.

llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td

 
 // 32-bit input, no output.
 class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo <
   opName, (outs), (ins SSrc_b32:$src0),
   "$src0", pattern> {
   let has_sdst = 0;
 }
 
+class SOP1_0_32R <string opName, list<dag> pattern = []> : SOP1_Pseudo <
+  opName, (outs), (ins SReg_32:$src0),
+  "$src0", pattern> {
+  let has_sdst = 0;
+}
+
 class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
   opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
   "$sdst, $src0", pattern
 >;
 
 // 64-bit input, 32-bit output.
 class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
   opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),

 
 let Uses = [M0] in {
 def S_MOVRELS_B32 : SOP1_32 <"s_movrels_b32">;
 def S_MOVRELS_B64 : SOP1_64 <"s_movrels_b64">;
 def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">;
 def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">;
 } // End Uses = [M0]
 
-def S_CBRANCH_JOIN : SOP1_1  <"s_cbranch_join">;
+def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">;
 def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">;
 let Defs = [SCC] in {
 def S_ABS_I32 : SOP1_32 <"s_abs_i32">;
 } // End Defs = [SCC]
 def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">;
 
 let SubtargetPredicate = HasVGPRIndexMode in {
 def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {

llvm/trunk/test/MC/AMDGPU/sop1.s

 s_movreld_b32 s1, s2
 // SICI: s_movreld_b32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
 // VI:   s_movreld_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe]
 
 s_movreld_b64 s[2:3], s[4:5]
 // SICI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe]
 // VI:   s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
 
-s_cbranch_join s[4:5]
-// SICI: s_cbranch_join s[4:5] ; encoding: [0x04,0x32,0x80,0xbe]
-// VI:   s_cbranch_join s[4:5] ; encoding: [0x04,0x2e,0x80,0xbe]
+s_cbranch_join s4
+// SICI: s_cbranch_join s4 ; encoding: [0x04,0x32,0x80,0xbe]
+// VI:   s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
+
+s_cbranch_join 1
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+
+s_cbranch_join 100
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
 
 s_abs_i32 s1, s2
 // SICI: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe]
 // VI:   s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
 
 s_mov_fed_b32 s1, s2
 // SICI: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe]
 
 s_set_gpr_idx_idx s0
 // VI: s_set_gpr_idx_idx s0 ; encoding: [0x00,0x32,0x80,0xbe]
 // NOSICI: error: instruction not supported on this GPU

llvm/trunk/test/MC/Disassembler/AMDGPU/sop1_vi.txt

 0x04 0x2b 0x82 0xbe
 
 # VI:   s_movreld_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe]
 0x02 0x2c 0x81 0xbe
 
 # VI:   s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
 0x04 0x2d 0x82 0xbe
 
-# VI:   s_cbranch_join s[4:5] ; encoding: [0x04,0x2e,0x80,0xbe]
+# VI:   s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
 0x04 0x2e 0x80 0xbe
 
 # VI:   s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
 0x02 0x30 0x81 0xbe