MIParser/MIRPrinter: Compute block successors if not explicitely specified

[MatzeB]

Summary

• MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough.
• MIRPrinter: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal.

[MatzeB]

Updated:

• Actually remove nearly all the successors: lines from X86,ARM,AArch64 and AMDGPU tests
• Ignore phi block arguments now
• Fix a bug when condjump and fallthrough to the same block corner case: We would get the same successor twice instead of just one which MI expects.

[qcolombet]

Hi Matthias,

Thanks for doing this, this is a long overdue!

MIRPrinter: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it.

I'd like the printer to always print everything. I don't think there is any value in having magic here.

Therefore, LGTM modulo drop the test case changes and MIRPrinter changes.

Cheers,
-Quentin

lib/CodeGen/MIRParser/MIParser.cpp

16

Do we have other relative path in the code base?
It feels awful.

[ab]

In D31262#710542, @qcolombet wrote:

I'd like the printer to always print everything. I don't think there is any value in having magic here.

IMO this kind of magic is very useful: it makes output much easier to read, and easier to start from when writing tests.

[MatzeB]

In D31262#710545, @ab wrote:

In D31262#710542, @qcolombet wrote:

I'd like the printer to always print everything. I don't think there is any value in having magic here.

IMO this kind of magic is very useful: it makes output much easier to read, and easier to start from when writing tests.

I also think there is value in reducing the amount of information printed. In this specific case the information omitted is quite obvious IMO.

[MatzeB]

lib/CodeGen/MIRParser/MIParser.cpp

16

Not many, but there are some in ExecutionEngine/RuntimeDyld, for example:

ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.h:#include "../RuntimeDyldCOFF.h"

but ok, I can move MIRPrinter.h to include/llvm/CodeGen instead. I'll do that in the next update.

[qcolombet]

I also think there is value in reducing the amount of information printed. In this specific case the information omitted is quite obvious IMO.

Something we talked with Vivek, if we really want something easier to edit, we could have two modes:

• One that prints everything (the default)
• One that prints only what cannot be deduced and is meant for editing

I really believe keeping the printer simple (print everything) for the default case is more sustainable in the long run.

Cheers,
-Quentin

[qcolombet]

In a nutshell, I am saying that we shouldn't conflict two goals: editing and printing. Printing should be full fledged, editing should be minimal.

[MatzeB]

In D31262#742311, @qcolombet wrote:

In a nutshell, I am saying that we shouldn't conflict two goals: editing and printing. Printing should be full fledged, editing should be minimal.

Sounds like we are not in sync what we do with .mir... It is a tool to create llvm lit tests, isn't it? Printing at least today is mostly done via MachineFunction::print() etc. Sure we want to unify the formats used there and .mir in the long term. But printing with llc -stop-after is the main tool to get started writing a lit test and we should promoted/encourage nice syntax there.

[MatzeB]

I'm still not completely convinced. But in the interest of compromise and getting this patch through:

• Added a -simplify-mir flag (off by default) that controls whether unnecessary successor list will be omitted.

[MatzeB]

• Move MIRPrinter.h to include/llvm/CodeGen to avoid ../ relative path.

[qcolombet]

Thanks Matthias.

LGTM, nitpicks below.

include/llvm/CodeGen/MIRPrinter.h

42

Although I understand why this is here, this illustrates my point that this should be a parser thing.

test/CodeGen/MIR/X86/auto-successor.mir

1

Could we have a positive test as well? (I.e., where successors are printed.)

test/CodeGen/MIR/X86/branch-probabilities.mir

6

This does not seem related to this patch.

[MatzeB]

Thanks for the review.

test/CodeGen/MIR/X86/auto-successor.mir

1

bb.0, bb.1, bb.2 are various levels of positive tests. For printing without -simplify-mir we already have test/CodeGen/MIR/X86/successor-basic-blocks.mir.

test/CodeGen/MIR/X86/branch-probabilities.mir

6

This is a translation of test/CodeGen/MIR/Generic/branch-probabilities.ll to .mir.

When this patch had the -simplify-mir beahvior the existing test would break because the probabilities were just balanced and therefore perfectly predictable.

Even though the change is not necessary anymore as the default printing behavior doesn't change I think I'll still keep this in here as it improves upon the robustness of the test.

[qcolombet]

test/CodeGen/MIR/X86/auto-successor.mir

1

I meant in the same file.
Like having this test being run twice.

docs/MIRLangRef.rst

 the embedded LLVM IR module.
 
 Simplifying MIR files
 ^^^^^^^^^^^^^^^^^^^^^
 
 The MIR code coming out of ``-stop-after``/``-stop-before`` is very verbose;
 Tests are more accessible and future proof when simplified:
 
+- Use the ``-simplify-mir`` option with llc.
+
 - Machine function attributes often have default values or the test works just
   as well with default values. Typical candidates for this are: `alignment:`,
   `exposesReturnsTwice`, `legalized`, `regBankSelected`, `selected`.
   The whole `frameInfo` section is often unnecessary if there is no special
   frame usage in the function. `tracksRegLiveness` on the other hand is often
   necessary for some passes that care about block livein lists.
 
 - The (global) `liveins:` list is typically only interesting for early

include/llvm/CodeGen/MIRPrinter.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_CODEGEN_MIRPRINTER_H
 #define LLVM_LIB_CODEGEN_MIRPRINTER_H
 
 namespace llvm {
 
+class MachineBasicBlock;
 class MachineFunction;
 class Module;
 class raw_ostream;
+template <typename T> class SmallVectorImpl;
 
 /// Print LLVM IR using the MIR serialization format to the given output stream.
 void printMIR(raw_ostream &OS, const Module &M);
 
 /// Print a machine function using the MIR serialization format to the given
 /// output stream.
 void printMIR(raw_ostream &OS, const MachineFunction &MF);
 
+/// Determine a possible list of successors of a basic block based on the
+/// basic block machine operand being used inside the block. This should give
+/// you the correct list of successor blocks in most cases except for things
+/// like jump tables where the basic block references can't easily be found.
+/// The MIRPRinter will skip printing successors if they match the result of
+/// this funciton and the parser will use this function to construct a list if
+/// it is missing.
+void guessSuccessors(const MachineBasicBlock &MBB,
+                     SmallVectorImpl<MachineBasicBlock*> &Successors,
+                     bool &IsFallthrough);
+
 } // end namespace llvm
 
 #endif

lib/CodeGen/MIRParser/MIParser.cpp

 //===- MIParser.cpp - Machine instructions parser implementation ----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the parsing of machine instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MIParser.h"
+
 #include "MILexer.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/AsmParser/Parser.h"
 #include "llvm/AsmParser/SlotMapping.h"
+#include "llvm/CodeGen/MIRPrinter.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
public:
   bool parseStandaloneNamedRegister(unsigned &Reg);
   bool parseStandaloneVirtualRegister(VRegInfo *&Info);
   bool parseStandaloneRegister(unsigned &Reg);
   bool parseStandaloneStackObject(int &FI);
   bool parseStandaloneMDNode(MDNode *&Node);
 
   bool
   parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
-  bool parseBasicBlock(MachineBasicBlock &MBB);
+  bool parseBasicBlock(MachineBasicBlock &MBB,
+                       MachineBasicBlock *&AddFalthroughFrom);
   bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
   bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
 
   bool parseNamedRegister(unsigned &Reg);
   bool parseVirtualRegister(VRegInfo *&Info);
   bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo);
   bool parseRegisterFlag(unsigned &Flags);
   bool parseRegisterClassOrBank(VRegInfo &RegInfo);
if (consumeIfPresent(MIToken::lparen)) {
         return true;
     }
     MBB.addSuccessor(SuccMBB, BranchProbability::getRaw(Weight));
   } while (consumeIfPresent(MIToken::comma));
   MBB.normalizeSuccProbs();
   return false;
 }
 
-bool MIParser::parseBasicBlock(MachineBasicBlock &MBB) {
+bool MIParser::parseBasicBlock(MachineBasicBlock &MBB,
+                               MachineBasicBlock *&AddFalthroughFrom) {
   // Skip the definition.
   assert(Token.is(MIToken::MachineBasicBlockLabel));
   lex();
   if (consumeIfPresent(MIToken::lparen)) {
     while (Token.isNot(MIToken::rparen) && !Token.isErrorOrEOF())
       lex();
     consumeIfPresent(MIToken::rparen);
   }
   consumeIfPresent(MIToken::colon);
 
   // Parse the liveins and successors.
   // N.B: Multiple lists of successors and liveins are allowed and they're
   // merged into one.
   // Example:
   //   liveins: %edi
   //   liveins: %esi
   //
   // is equivalent to
   //   liveins: %edi, %esi
+  bool ExplicitSuccesors = false;
   while (true) {
     if (Token.is(MIToken::kw_successors)) {
       if (parseBasicBlockSuccessors(MBB))
         return true;
+      ExplicitSuccesors = true;
     } else if (Token.is(MIToken::kw_liveins)) {
       if (parseBasicBlockLiveins(MBB))
         return true;
     } else if (consumeIfPresent(MIToken::Newline)) {
       continue;
     } else
       break;
     if (!Token.isNewlineOrEOF())
       return error("expected line break at the end of a list");
     lex();
   }
 
   // Parse the instructions.
   bool IsInBundle = false;
   MachineInstr *PrevMI = nullptr;
-  while (true) {
-    if (Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof))
-      return false;
-    else if (consumeIfPresent(MIToken::Newline))
+  while (!Token.is(MIToken::MachineBasicBlockLabel) &&
+         !Token.is(MIToken::Eof)) {
+    if (consumeIfPresent(MIToken::Newline))
       continue;
     if (consumeIfPresent(MIToken::rbrace)) {
       // The first parsing pass should verify that all closing '}' have an
       // opening '{'.
       assert(IsInBundle);
       IsInBundle = false;
       continue;
     }
if (Token.is(MIToken::lbrace)) {
       IsInBundle = true;
       if (!Token.is(MIToken::Newline))
         // The next instruction can be on the same line.
         continue;
     }
     assert(Token.isNewlineOrEOF() && "MI is not fully parsed");
     lex();
   }
+
+  // Construct successor list by searching for basic block machine operands.
+  if (!ExplicitSuccesors) {
+    SmallVector<MachineBasicBlock*,4> Successors;
+    bool IsFallthrough;
+    guessSuccessors(MBB, Successors, IsFallthrough);
+    for (MachineBasicBlock *Succ : Successors)
+      MBB.addSuccessor(Succ);
+
+    if (IsFallthrough) {
+      AddFalthroughFrom = &MBB;
+    } else {
+      MBB.normalizeSuccProbs();
+    }
+  }
+
   return false;
 }
 
 bool MIParser::parseBasicBlocks() {
   lex();
   // Skip until the first machine basic block.
   while (Token.is(MIToken::Newline))
     lex();
   if (Token.isErrorOrEOF())
     return Token.isError();
   // The first parsing pass should have verified that this token is a MBB label
   // in the 'parseBasicBlockDefinitions' method.
   assert(Token.is(MIToken::MachineBasicBlockLabel));
+  MachineBasicBlock *AddFalthroughFrom = nullptr;
   do {
     MachineBasicBlock *MBB = nullptr;
     if (parseMBBReference(MBB))
       return true;
-    if (parseBasicBlock(*MBB))
+    if (AddFalthroughFrom) {
+      if (!AddFalthroughFrom->isSuccessor(MBB))
+        AddFalthroughFrom->addSuccessor(MBB);
+      AddFalthroughFrom->normalizeSuccProbs();
+      AddFalthroughFrom = nullptr;
+    }
+    if (parseBasicBlock(*MBB, AddFalthroughFrom))
       return true;
     // The method 'parseBasicBlock' should parse the whole block until the next
     // block or the end of file.
     assert(Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof));
   } while (Token.isNot(MIToken::Eof));
   return false;
 }
 

lib/CodeGen/MIRPrinter.cpp

 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the class that prints out the LLVM IR and machine
 // functions using the MIR serialization format.
 //
 //===----------------------------------------------------------------------===//
 
-#include "MIRPrinter.h"
+#include "llvm/CodeGen/MIRPrinter.h"
+
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallBitVector.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DebugInfo.h"
 #include "llvm/IR/IRPrintingPasses.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/ModuleSlotTracker.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Options.h"
 #include "llvm/Support/YAMLTraits.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetIntrinsicInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 using namespace llvm;
 
+static cl::opt<bool> SimplifyMIR("simplify-mir",
+    cl::desc("Leave out unnecessary information when printing MIR"));
+
 namespace {
 
 /// This structure describes how to print out stack object references.
 struct FrameIndexOperand {
   std::string Name;
   unsigned ID;
   bool IsFixed;
 

 /// This class prints out the machine instructions using the MIR serialization
 /// format.
 class MIPrinter {
   raw_ostream &OS;
   ModuleSlotTracker &MST;
   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
 
+  bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
+  bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
+
 public:
   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
         StackObjectOperandMapping(StackObjectOperandMapping) {}
 
   void print(const MachineBasicBlock &MBB);

 
 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
   const auto *TRI = MF.getSubtarget().getRegisterInfo();
   unsigned I = 0;
   for (const uint32_t *Mask : TRI->getRegMasks())
     RegisterMaskIds.insert(std::make_pair(Mask, I++));
 }
 
+void llvm::guessSuccessors(const MachineBasicBlock &MBB,
+                           SmallVectorImpl<MachineBasicBlock*> &Result,
+                           bool &IsFallthrough) {
+  SmallPtrSet<MachineBasicBlock*,8> Seen;
+
+  for (const MachineInstr &MI : MBB) {
+    if (MI.isPHI())
+      continue;
+    for (const MachineOperand &MO : MI.operands()) {
+      if (!MO.isMBB())
+        continue;
+      MachineBasicBlock *Succ = MO.getMBB();
+      auto RP = Seen.insert(Succ);
+      if (RP.second)
+        Result.push_back(Succ);
+    }
+  }
+  MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
+  IsFallthrough = I == MBB.end() || !I->isBarrier();
+}
+
+bool
+MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
+  if (MBB.succ_size() <= 1)
+    return true;
+  if (!MBB.hasSuccessorProbabilities())
+    return true;
+
+  SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
+                                              MBB.Probs.end());
+  BranchProbability::normalizeProbabilities(Normalized.begin(),
+                                            Normalized.end());
+  SmallVector<BranchProbability,8> Equal(Normalized.size());
+  BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
+
+  return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
+}
+
+bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
+  SmallVector<MachineBasicBlock*,8> GuessedSuccs;
+  bool GuessedFallthrough;
+  guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
+  if (GuessedFallthrough) {
+    const MachineFunction &MF = *MBB.getParent();
+    MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
+    if (NextI != MF.end()) {
+      MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
+      if (!is_contained(GuessedSuccs, Next))
+        GuessedSuccs.push_back(Next);
+    }
+  }
+  if (GuessedSuccs.size() != MBB.succ_size())
+    return false;
+  return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
+}
+
+
 void MIPrinter::print(const MachineBasicBlock &MBB) {
   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
   OS << "bb." << MBB.getNumber();
   bool HasAttributes = false;
   if (const auto *BB = MBB.getBasicBlock()) {
     if (BB->hasName()) {
       OS << "." << BB->getName();
     } else {
if (MBB.getAlignment()) {
     HasAttributes = true;
   }
   if (HasAttributes)
     OS << ")";
   OS << ":\n";
 
   bool HasLineAttributes = false;
   // Print the successors
-  if (!MBB.succ_empty()) {
+  bool canPredictProbs = canPredictBranchProbabilities(MBB);
+  if (!MBB.succ_empty() && (!SimplifyMIR || !canPredictProbs ||
+                            !canPredictSuccessors(MBB))) {
     OS.indent(2) << "successors: ";
     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
       if (I != MBB.succ_begin())
         OS << ", ";
       printMBBReference(**I);
-      if (MBB.hasSuccessorProbabilities())
+      if (!SimplifyMIR || !canPredictProbs)
         OS << '('
            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
            << ')';
     }
     OS << "\n";
     HasLineAttributes = true;
   }
 

lib/CodeGen/MIRPrintingPass.cpp

 //===- MIRPrintingPass.cpp - Pass that prints out using the MIR format ----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a pass that prints out the LLVM module using the MIR
 // serialization format.
 //
 //===----------------------------------------------------------------------===//
 
-#include "MIRPrinter.h"
+#include "llvm/CodeGen/MIRPrinter.h"
+
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 

test/CodeGen/AArch64/loh.mir

bb.12:
     ; %X9<def> = ADDXri %X9, <ga:@g4>
     ; %X5<def> = LDRXui %X9, 0
     %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
     %x5 = LDRXui %x9, 0
     %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g5
 
   bb.13:
-    successors: %bb.14
     ; Cannot produce a LOH for multiple users
     ; CHECK-NOT: MCLOH_AdrpAdd
     %x10 = ADRP target-flags(aarch64-page) @g0
     %x11 = ADDXri %x10, target-flags(aarch64-pageoff) @g0, 0
     B %bb.14
 
   bb.14:
     liveins: %x10
     %x12 = ADDXri %x10, target-flags(aarch64-pageoff) @g0, 0
 ...

test/CodeGen/AArch64/machine-copy-remove.mir

 # RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-copyelim %s -verify-machineinstrs -o - | FileCheck %s
 ---
 # Check that bb.0 COPY is seen through to allow the bb.1 COPY of XZR to be removed.
 # CHECK-LABEL: name: test1
 # CHECK-NOT: COPY %xzr
 name:            test1
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     %x0 = COPY %x1
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Similar to test1, but with reversed COPY.
 # CHECK-LABEL: name: test2
 # CHECK-NOT: COPY %xzr
 name:            test2
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     %x1 = COPY %x0
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Similar to test1, but with a clobber that prevents removal of the XZR COPY.
 # CHECK-LABEL: name: test3
 # CHECK: COPY %xzr
 name:            test3
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1, %x2
 
     %x0 = COPY %x1
     %x1 = LDRXui %x1, 0
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Similar to test2, but with a clobber that prevents removal of the XZR COPY.
 # CHECK-LABEL: name: test4
 # CHECK: COPY %xzr
 name:            test4
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1, %x2
 
     %x1 = COPY %x0
     %x1 = LDRXui %x1, 0
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Similar to test2, but with a clobber that prevents removal of the XZR COPY.
 # CHECK-LABEL: name: test5
 # CHECK: COPY %xzr
 name:            test5
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1, %x2
 
     %x1 = COPY %x0
     %x0 = LDRXui %x1, 0
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Similar to test1, but with two levels of COPYs.
 # CHECK-LABEL: name: test6
 # CHECK-NOT: COPY %xzr
 name:            test6
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1, %x2
 
     %x2 = COPY %x0
     %x1 = COPY %x2
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Similar to test1, but with two levels of COPYs and a clobber preventing COPY of XZR removal.
 # CHECK-LABEL: name: test7
 # CHECK: COPY %xzr
 name:            test7
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1, %x2
 
     %x2 = COPY %x0
     %x0 = LDRXui %x1, 0
     %x1 = COPY %x2
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
-
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Check that the TargetRegs vector clobber update loop in
 #  AArch64RedundantCopyElimination::optimizeCopy works correctly.
 # CHECK-LABEL: name: test8
 # CHECK: x0 = COPY %xzr
 # CHECK: x1 = COPY %xzr
 name:            test8
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     %x1 = COPY %x0
     CBNZX %x1, %bb.2
 
   bb.1:
-    successors: %bb.3
     liveins: %x0, %x2
 
     %x0, %x1 = LDPXi %x2, 0
     %x0 = COPY %xzr
     %x1 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Check that copy isn't removed from a block with multiple predecessors.
 # CHECK-LABEL: name: test9
 # CHECK: x0 = COPY %xzr
 # CHECK-NEXT: B %bb.3
 name:            test9
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     CBNZX %x0, %bb.2
 
   bb.1:
-    successors: %bb.3
     liveins: %x0, %x2
 
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    successors: %bb.1, %bb.3
     liveins: %x1
 
     %x0 = LDRXui %x1, 0
 
     CBNZX %x1, %bb.1
 
   bb.3:
     liveins: %x0
 
     RET_ReallyLR implicit %x0
 
 ...
 # Eliminate redundant MOVi32imm 7 in bb.1
 # Note: 32-bit compare/32-bit move imm
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test10
 # CHECK: SUBSWri %w0, 7, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test10
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 7
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Eliminate redundant MOVi32imm 7 in bb.1
 # Note: 64-bit compare/32-bit move imm w/implicit def
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test11
 # CHECK: SUBSXri %x0, 7, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test11
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     dead %xzr = SUBSXri killed %x0, 7, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 7, implicit-def %x0
     STRXui killed %x0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Eliminate redundant MOVi32imm 7 in bb.1
 # Note: 64-bit compare/32-bit move imm
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test12
 # CHECK: SUBSXri %x0, 7, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test12
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     dead %xzr = SUBSXri killed %x0, 7, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 7
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Don't eliminate MOVi32imm 7 in bb.1 as we don't necessarily know the upper 32-bits.
 # Note: 32-bit compare/32-bit move imm w/implicit def
 # Kill marker should remain on compare.
 # CHECK-LABEL: name: test13
 # CHECK: SUBSWri killed %w0, 7, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK: MOVi32imm
 name:            test13
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 7, implicit-def %x0
     STRXui killed %x0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # We can't eliminate the MOVi32imm because of the clobbering LDRWui.
 # CHECK-LABEL: name: test14
 # CHECK: bb.1:
 # CHECK: MOVi32imm
 name:            test14
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1, %x2
 
     dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
     %w0 = LDRWui %x1, 0
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 7
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # We can't eliminate the MOVi32imm because of the clobbering LDRWui.
 # CHECK-LABEL: name: test15
 # CHECK: bb.1:
 # CHECK: MOVi32imm
 name:            test15
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1, %x2
 
     dead %wzr = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1, %x2
 
     %w0 = LDRWui %x1, 0
     STRWui killed %w0, killed %x2, 0
     %w0 = MOVi32imm 7
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Check that bb.0 COPY is seen through to allow the bb.1 MOVi32imm to be removed.
 # CHECK-LABEL: name: test16
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test16
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %wzr = SUBSWri %w0, 7, 0, implicit-def %nzcv
     %w2 = COPY %w0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w2 = MOVi32imm 7
     STRWui killed %w2, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Check that bb.1 MOVi32imm is not removed due to self clobbering compare.
 # CHECK-LABEL: name: test17
 # CHECK: bb.1:
 # CHECK: MOVi32imm
 name:            test17
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %w0 = SUBSWri killed %w0, 7, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 7
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Make sure the MOVi64imm is not removed.  In one version of this patch the
 # MOVi64imm immediate was truncated to 32 bits and incorrectly matched because
 # the low 32 bits of 4252017623040 are all zero.
 # CHECK-LABEL: name: test18
 # CHECK: bb.1:
 # CHECK: MOVi64imm
 name:            test18
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     CBNZX killed %x0, %bb.2
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %x0 = MOVi64imm 4252017623040
     STRXui killed %x0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Eliminate redundant MOVi32imm -1 in bb.1
 # Note: 32-bit compare/32-bit move imm
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test19
 # CHECK: ADDSWri %w0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test19
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %wzr = ADDSWri killed %w0, 1, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm -1
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Eliminate redundant MOVi64imm -1 in bb.1
 # Note: 64-bit compare/64-bit move imm
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test20
 # CHECK: ADDSXri %x0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: MOVi64imm
 name:            test20
 tracksRegLiveness: true
 body:             |
   bb.0:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     dead %xzr = ADDSXri killed %x0, 1, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %x0 = MOVi64imm -1
     STRXui killed %x0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Eliminate redundant MOVi32imm -1 in bb.1
 # Note: 64-bit compare/32-bit move imm
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test21
 # CHECK: ADDSXri %x0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test21
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %x0, %x1
 
     dead %xzr = ADDSXri killed %x0, 1, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm -1
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Don't eliminate MOVi64imm -1 in bb.1 as we don't necessarily know the upper 32-bits.
 # Note: 32-bit compare/64-bit move imm
 # CHECK-LABEL: name: test22
 # CHECK: bb.1:
 # CHECK: MOVi64imm
 name:            test22
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %wzr = ADDSWri killed %w0, 1, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %x0 = MOVi64imm -1
     STRXui killed %x0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Eliminate redundant MOVi32imm 4096 in bb.1 when the compare has a shifted immediate.
 # CHECK-LABEL: name: test23
 # CHECK: bb.1:
 # CHECK-NOT: MOVi32imm
 name:            test23
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2
     liveins: %w0, %x1
 
     dead %wzr = SUBSWri killed %w0, 1, 12, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
-    successors: %bb.2
     liveins: %x1
 
     %w0 = MOVi32imm 4096
     STRWui killed %w0, killed %x1, 0
 
   bb.2:
     RET_ReallyLR

test/CodeGen/AArch64/machine-sink-zr.mir

registers:
   - { id: 3, class: gpr32 }
   - { id: 4, class: gpr32 }
 body:             |
   ; Check that WZR copy is sunk into the loop preheader.
   ; CHECK-LABEL: name: sinkwzr
   ; CHECK-LABEL: bb.0:
   ; CHECK-NOT: COPY %wzr
   bb.0:
-    successors: %bb.3, %bb.1
     liveins: %w0
 
     %0 = COPY %w0
     %1 = COPY %wzr
     CBZW %0, %bb.3
 
   ; CHECK-LABEL: bb.1:
   ; CHECK: COPY %wzr
 
   bb.1:
-    successors: %bb.2
-
     B %bb.2
 
   bb.2:
-    successors: %bb.3, %bb.2
-
     %2 = PHI %0, %bb.1, %4, %bb.2
     %w0 = COPY %1
     %3 = SUBSWri %2, 1, 0, implicit-def dead %nzcv
     %4 = COPY %3
     CBZW %3, %bb.3
     B %bb.2
 
   bb.3:
     RET_ReallyLR
 
 ...

test/CodeGen/AArch64/regcoal-physreg.mir

bb.0:
     %fp = COPY %9
 ...
 ---
 # Check coalescing of COPYs from reserved physregs.
 # CHECK-LABEL: name: func1
 name: func1
 body: |
   bb.0:
-    successors: %bb.1, %bb.2
     ; Cannot coalesce physreg because we have reads on other CFG paths (we
     ; currently abort for any control flow)
     ; CHECK-NOT: %fp = SUBXri
     ; CHECK: %0 = SUBXri %fp, 12, 0
     ; CHECK: CBZX undef %x0, %bb.1
     ; CHECK: B %bb.2
     %0 : gpr64sp = SUBXri %fp, 12, 0
     CBZX undef %x0, %bb.1
     B %bb.2
 
   bb.1:
     %fp = COPY %0
     RET_ReallyLR
 
   bb.2:
     STRXui %fp, %fp, 0
     RET_ReallyLR
 ...
 ---
 # CHECK-LABEL: name: func2
 name: func2
 body: |
   bb.0:
-    successors: %bb.1, %bb.2
     ; We can coalesce copies from physreg to vreg across multiple blocks.
     ; CHECK-NOT: COPY
     ; CHECK: CBZX undef %x0, %bb.1
     ; CHECK-NEXT: B %bb.2
     %0 : gpr64sp = COPY %fp
     CBZX undef %x0, %bb.1
     B %bb.2
 

test/CodeGen/AMDGPU/detect-dead-lanes.mir

registers:
   - { id: 0, class: sreg_32_xm0 }
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sreg_32_xm0 }
   - { id: 3, class: sreg_128 }
   - { id: 4, class: sreg_128 }
   - { id: 5, class: sreg_128 }
 body: |
   bb.0:
-    successors: %bb.1
     S_NOP 0, implicit-def %0
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def %2
     %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.1, %bb.2
     %4 = PHI %3, %bb.0, %5, %bb.1
 
     ; let's swiffle some lanes around for fun...
     %5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
registers:
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sreg_32_xm0 }
   - { id: 3, class: sreg_32_xm0 }
   - { id: 4, class: sreg_128 }
   - { id: 5, class: sreg_128 }
   - { id: 6, class: sreg_128 }
 body: |
   bb.0:
-    successors: %bb.1
     S_NOP 0, implicit-def %0
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def dead %2
     S_NOP 0, implicit-def %3
     %4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.1, %bb.2
     %5 = PHI %4, %bb.0, %6, %bb.1
 
     ; rotate lanes, but skip sub2 lane...
     %6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 

 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32_xm0 }
   - { id: 1, class: sreg_128 }
   - { id: 2, class: sreg_128 }
   - { id: 3, class: sreg_128 }
 body: |
   bb.0:
-    successors: %bb.1
     S_NOP 0, implicit-def %0
     %1 = REG_SEQUENCE %0, %subreg.sub0
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.1, %bb.2
     %2 = PHI %1, %bb.0, %3, %bb.1
 
     ; rotate subreg lanes, skipping sub1
     %3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
     S_NOP 0, implicit %2.sub0
     S_NOP 0, implicit undef %2.sub1
     S_NOP 0, implicit %2.sub2
     S_NOP 0, implicit %2.sub3
 ...

test/CodeGen/AMDGPU/inserted-wait-states.mir

 # GCN: S_NOP
 # GCN: S_NOP
 # GCN: S_NOP
 # GCN: V_DIV_FMAS_F32
 name: div_fmas
 
 body: |
   bb.0:
-    successors: %bb.1
     %vcc = S_MOV_B64 0
     %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.2
     implicit %vcc = V_CMP_EQ_I32_e32 %vgpr1, %vgpr2, implicit %exec
     %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
     S_BRANCH %bb.2
 
   bb.2:
-    successors: %bb.3
     %vcc = V_CMP_EQ_I32_e64 %vgpr1, %vgpr2, implicit %exec
     %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
     S_BRANCH %bb.3
 
   bb.3:
     %vgpr4, %vcc = V_DIV_SCALE_F32 %vgpr1, %vgpr1, %vgpr3, implicit %exec
     %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
     S_ENDPGM

 # GCN-LABEL: bb.3:
 # GCN: S_SETREG
 # GCN-NEXT: S_GETREG
 
 name: s_getreg
 
 body: |
   bb.0:
-    successors: %bb.1
     S_SETREG_B32 %sgpr0, 1
     %sgpr1 = S_GETREG_B32 1
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.2
     S_SETREG_IMM32_B32 0, 1
     %sgpr1 = S_GETREG_B32 1
     S_BRANCH %bb.2
 
   bb.2:
-    successors: %bb.3
     S_SETREG_B32 %sgpr0, 1
     %sgpr1 = S_MOV_B32 0
     %sgpr2 = S_GETREG_B32 1
     S_BRANCH %bb.3
 
   bb.3:
     S_SETREG_B32 %sgpr0, 0
     %sgpr1 = S_GETREG_B32 1

 # GCN-LABEL: bb.2:
 # GCN: S_SETREG
 # GCN-NEXT: S_SETREG
 
 name: s_setreg
 
 body: |
   bb.0:
-    successors: %bb.1
     S_SETREG_B32 %sgpr0, 1
     S_SETREG_B32 %sgpr1, 1
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.2
     S_SETREG_B32 %sgpr0, 64
     S_SETREG_B32 %sgpr1, 128
     S_BRANCH %bb.2
 
   bb.2:
     S_SETREG_B32 %sgpr0, 1
     S_SETREG_B32 %sgpr1, 0
     S_ENDPGM

 # GCN: FLAT_ATOMIC_FCMPSWAP_X2
 # CIVI: S_NOP
 # GCN: V_MOV_B32
 
 name: vmem_gt_8dw_store
 
 body: |
   bb.0:
-    successors: %bb.1
     BUFFER_STORE_DWORD_OFFSET %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
     %vgpr3 = V_MOV_B32_e32 0, implicit %exec
     BUFFER_STORE_DWORDX3_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec
     %vgpr3 = V_MOV_B32_e32 0, implicit %exec
     BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
     %vgpr3 = V_MOV_B32_e32 0, implicit %exec
     BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec
     %vgpr3 = V_MOV_B32_e32 0, implicit %exec

 # GCN: S_NOP
 # GCN: S_NOP
 # GCN: V_WRITELANE_B32
 
 name: readwrite_lane
 
 body: |
   bb.0:
-    successors: %bb.1
     %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
     %sgpr4 = V_READLANE_B32 %vgpr4, %sgpr0
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.2
     %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
     %vgpr4 = V_WRITELANE_B32 %sgpr0, %sgpr0
     S_BRANCH %bb.2
 
   bb.2:
-    successors: %bb.3
     %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
     %sgpr4 = V_READLANE_B32 %vgpr4, %vcc_lo
     S_BRANCH %bb.3
 
   bb.3:
     %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
     %vgpr4 = V_WRITELANE_B32 %sgpr4, %vcc_lo
     S_ENDPGM

 # GCN-LABEL: bb.1:
 # GCN: S_SETREG
 # GCN-NEXT: S_RFE_B64
 
 name: rfe
 
 body: |
   bb.0:
-    successors: %bb.1
     S_SETREG_B32 %sgpr0, 3
     S_RFE_B64 %sgpr2_sgpr3
     S_BRANCH %bb.1
 
   bb.1:
     S_SETREG_B32 %sgpr0, 0
     S_RFE_B64 %sgpr2_sgpr3
     S_ENDPGM

 # GCN-LABEL: bb.1:
 # GCN: S_MOV_FED_B32
 # GFX9: S_NOP
 # GCN-NEXT: V_MOV_B32
 name: s_mov_fed_b32
 
 body: |
   bb.0:
-    successors: %bb.1
     %sgpr0 = S_MOV_FED_B32 %sgpr0
     %sgpr0 = S_MOV_B32 %sgpr0
     S_BRANCH %bb.1
 
   bb.1:
     %sgpr0 = S_MOV_FED_B32 %sgpr0
     %vgpr0 = V_MOV_B32_e32 %sgpr0, implicit %exec
     S_ENDPGM

 # GCN: S_MOV_B32
 # GFX9: S_NOP
 # GCN-NEXT: S_MOVRELD_B64
 
 name: s_movrel
 
 body: |
   bb.0:
-    successors: %bb.1
     %m0 = S_MOV_B32 0
     %sgpr0 = S_MOVRELS_B32 %sgpr0, implicit %m0
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.2
     %m0 = S_MOV_B32 0
     %sgpr0_sgpr1 = S_MOVRELS_B64 %sgpr0_sgpr1, implicit %m0
     S_BRANCH %bb.2
 
   bb.2:
-    successors: %bb.3
     %m0 = S_MOV_B32 0
     %sgpr0 = S_MOVRELD_B32 %sgpr0, implicit %m0
     S_BRANCH %bb.3
 
   bb.3:
     %m0 = S_MOV_B32 0
     %sgpr0_sgpr1 = S_MOVRELD_B64 %sgpr0_sgpr1, implicit %m0
     S_ENDPGM

 # GCN: S_MOV_B32
 # GFX9: S_NOP
 # GCN-NEXT: V_INTERP_MOV_F32
 
 name: v_interp
 
 body: |
   bb.0:
-    successors: %bb.1
     %m0 = S_MOV_B32 0
     %vgpr0 = V_INTERP_P1_F32 %vgpr0, 0, 0, implicit %m0, implicit %exec
     S_BRANCH %bb.1
 
   bb.1:
-    successors: %bb.2
     %m0 = S_MOV_B32 0
     %vgpr0 = V_INTERP_P2_F32 %vgpr0, %vgpr1, 0, 0, implicit %m0, implicit %exec
     S_BRANCH %bb.2
 
   bb.2:
-    successors: %bb.3
     %m0 = S_MOV_B32 0
     %vgpr0 = V_INTERP_P1_F32_16bank %vgpr0, 0, 0, implicit %m0, implicit %exec
     S_BRANCH %bb.3
 
   bb.3:
     %m0 = S_MOV_B32 0
     %vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit %m0, implicit %exec
     S_ENDPGM

test/CodeGen/AMDGPU/invert-br-undef-vcc.mir

frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
-    successors: %bb.2.if, %bb.1.else
     liveins: %sgpr0_sgpr1
 
     %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     S_CBRANCH_VCCNZ %bb.2.if, implicit undef %vcc
 
   bb.1.else:
-    successors: %bb.3.done
     liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %vgpr0 = V_MOV_B32_e32 100, implicit %exec
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
     %vgpr0 = V_MOV_B32_e32 1, implicit %exec
     S_BRANCH %bb.3.done
 
   bb.2.if:
-    successors: %bb.3.done
     liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %vgpr0 = V_MOV_B32_e32 9, implicit %exec
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
     %vgpr0 = V_MOV_B32_e32 0, implicit %exec
 
   bb.3.done:
     liveins: %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %sgpr3 = S_MOV_B32 61440
     %sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
     S_ENDPGM
 
 ...

test/CodeGen/AMDGPU/liveness.mir

--- |
   define amdgpu_kernel void @test0() { ret void }
 ...
 ---
 name: test0
 registers:
   - { id: 0, class: sreg_64 }
 body: |
   bb.0:
-    successors: %bb.1, %bb.2
     S_NOP 0, implicit-def undef %0.sub0
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.1:
-    successors: %bb.2
     S_NOP 0, implicit-def %0.sub1
     S_NOP 0, implicit %0.sub1
     S_BRANCH %bb.2
 
   bb.2:
     S_NOP 0, implicit %0.sub0
 ...

test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_OR_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     BUFFER_STORE_DWORD_OFFSET %vgpr0, undef %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into `i32 addrspace(1)* undef`)
     %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr6 = S_MOV_B32 -1
     %sgpr7 = S_MOV_B32 61440
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr0_sgpr1 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %sgpr0_sgpr1 = S_XOR_B64 undef %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc
     %exec = S_MOV_B64_term %sgpr0_sgpr1
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1 , %sgpr4_sgpr5_sgpr6_sgpr7
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1, %sgpr4_sgpr5_sgpr6_sgpr7
 
     %exec = S_OR_B64 %exec, killed %sgpr0_sgpr1, implicit-def %scc
     %sgpr3 = S_MOV_B32 61440
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %sgpr2_sgpr3 = S_OR_B64 killed %sgpr2_sgpr3, 1, implicit-def %scc
     %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc
     %exec = S_MOV_B64_term %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1, %sgpr2_sgpr3
     S_SLEEP 0, implicit %sgpr2_sgpr3
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_LSHR_B64 %sgpr0_sgpr1, killed %vcc_lo, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_ANDN2_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.main_body:
-    successors: %bb.1.if, %bb.2.end
     liveins: %vgpr0
 
     %sgpr0_sgpr1 = COPY %exec
     %vcc = V_CMP_EQ_I32_e64 0, killed %vgpr0, implicit %exec
     %vgpr0 = V_MOV_B32_e32 4, implicit %exec
     %sgpr2_sgpr3 = S_ANDN2_B64 killed %vcc, %sgpr0_sgpr1, implicit-def %scc
     %exec = S_MOV_B64_term killed %sgpr2_sgpr3
     SI_MASK_BRANCH %bb.2.end, implicit %exec
     S_BRANCH %bb.1.if
 
   bb.1.if:
-    successors: %bb.2.end
     liveins: %sgpr0_sgpr1
 
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
 
   bb.2.end:
     liveins: %vgpr0, %sgpr0_sgpr1
 
     %exec = S_OR_B64 %exec, killed %sgpr0_sgpr1, implicit-def %scc
     %sgpr3 = S_MOV_B32 61440
     %sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into `i32 addrspace(1)* undef`)
     S_ENDPGM
 
 ...

test/CodeGen/AMDGPU/rename-independent-subregs.mir

 # CHECK: bb.2
 # CHECK: S_NOP 0, implicit %2.sub
 name: test1
 registers:
   - { id: 0, class: sreg_128 }
   - { id: 1, class: sreg_128 }
 body: |
   bb.0:
-    successors: %bb.1, %bb.2
     S_NOP 0, implicit-def undef %0.sub2
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.1:
     S_NOP 0, implicit-def %0.sub1
     S_NOP 0, implicit-def %0.sub3
     %1 = COPY %0

test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir

registers:
   - { id: 10, class: sreg_64 }
   - { id: 11, class: sreg_32_xm0 }
 
 body: |
   ; GCN-LABEL: name: phi_visit_order
   ; GCN: V_ADD_I32
   bb.0:
     liveins: %vgpr0
-    successors: %bb.1
     %7 = COPY %vgpr0
     %8 = S_MOV_B32 0
 
   bb.1:
-    successors: %bb.1, %bb.2
     %0 = PHI %8, %bb.0, %0, %bb.1, %2, %bb.2
     %9 = V_MOV_B32_e32 9, implicit %exec
     %10 = V_CMP_EQ_U32_e64 %7, %9, implicit %exec
     %1 = SI_IF %10, %bb.2, implicit-def %exec, implicit-def %scc, implicit %exec
     S_BRANCH %bb.1
 
   bb.2:
-    successors: %bb.1
     SI_END_CF %1, implicit-def %exec, implicit-def %scc, implicit %exec
     %11 = S_MOV_B32 1
     %2 = S_ADD_I32 %0, %11, implicit-def %scc
     S_BRANCH %bb.1
 
 ...
 ---

test/CodeGen/AMDGPU/subreg-intervals.mir

bb.0:
     S_NOP 0, implicit %0
 ...
 ---
 name: test1
 registers:
   - { id: 0, class: sreg_64 }
 body: |
   bb.0:
-    successors: %bb.1, %bb.2
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.1:
-    successors: %bb.3
     S_NOP 0, implicit-def undef %0.sub0
     S_BRANCH %bb.3
 
   bb.2:
-    successors: %bb.3
     S_NOP 0, implicit-def %0
     S_BRANCH %bb.3
 
   bb.3:
     S_NOP 0
     S_NOP 0, implicit %0
 ...

test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir

frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
-    successors: %bb.2.if, %bb.1.else
     liveins: %sgpr0_sgpr1
 
     %sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 9, 0 :: (non-temporal dereferenceable invariant load 4 from `float addrspace(2)* undef`)
     %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vcc = V_CMP_EQ_F32_e64 0, 0, 0, %sgpr2, 0, 0, implicit %exec
     S_CBRANCH_VCCZ %bb.1.else, implicit killed %vcc
 
   bb.2.if:
-    successors: %bb.3.done
     liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %vgpr0 = V_MOV_B32_e32 9, implicit %exec
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
     %vgpr0 = V_MOV_B32_e32 0, implicit %exec
     S_BRANCH %bb.3.done
 
   bb.1.else:
-    successors: %bb.3.done
     liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %vgpr0 = V_MOV_B32_e32 100, implicit %exec
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
     %vgpr0 = V_MOV_B32_e32 1, implicit %exec
 
   bb.3.done:
     liveins: %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
-    successors: %bb.2.if, %bb.1.else
     liveins: %sgpr0_sgpr1
 
     %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     S_CBRANCH_VCCZ %bb.1.else, implicit undef %vcc
 
   bb.2.if:
-    successors: %bb.3.done
     liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %vgpr0 = V_MOV_B32_e32 9, implicit %exec
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
     %vgpr0 = V_MOV_B32_e32 0, implicit %exec
     S_BRANCH %bb.3.done
 
   bb.1.else:
-    successors: %bb.3.done
     liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %vgpr0 = V_MOV_B32_e32 100, implicit %exec
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
     %vgpr0 = V_MOV_B32_e32 1, implicit %exec
 
   bb.3.done:
     liveins: %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
 
     %sgpr3 = S_MOV_B32 61440
     %sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
     S_ENDPGM
 
 ...

test/CodeGen/ARM/ARMLoadStoreDBG.mir

frameInfo:
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 stack:
   - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
   - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
 body:             |
   bb.0.entry:
-    successors: %bb.1, %bb.2.if.end
     liveins: %r0, %r1, %r2, %r3, %lr, %r7
 
     DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
     DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
     t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31
     t2Bcc %bb.2.if.end, 2, killed %cpsr

test/CodeGen/ARM/cmp1-peephole-thumb.mir

frameInfo:
   hasMustTailInVarArgFunc: false
 
 # CHECK:  tMOVi8 1, 14, _
 # CHECK:  tMOVi8 0, 14, _
 # CHECK:  tMUL %1, %0, 14, _
 # CHECK-NOT: tCMPi8
 body:             |
   bb.0.entry:
-    successors: %bb.1.entry(0x40000000), %bb.2.entry(0x40000000)
     liveins: %r0, %r1
 
     %1 = COPY %r1
     %0 = COPY %r0
     %2, %cpsr = tMUL %1, %0, 14, _
     %3, %cpsr = tMOVi8 1, 14, _
     %4, %cpsr = tMOVi8 0, 14, _
     tCMPi8 killed %2, 0, 14, _, implicit-def %cpsr
     tBcc %bb.2.entry, 0, %cpsr
 
   bb.1.entry:
-    successors: %bb.2.entry(0x80000000)
-
 
   bb.2.entry:
     %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
     %r0 = COPY %5
     tBX_RET 14, _, implicit %r0
 
 ...

test/CodeGen/ARM/cmp2-peephole-thumb.mir

stack:
   - { id: 0, name: retval, offset: 0, size: 4, alignment: 4, local-offset: -4 }
   - { id: 1, name: mul, offset: 0, size: 4, alignment: 4, local-offset: -8 }
 
 # CHECK: tMUL
 # CHECK-NEXT: tSTRspi
 # CHECK-NEXT: tCMPi8
 body:             |
   bb.0.entry:
-    successors: %bb.1.if.then(0x40000000), %bb.2.if.end(0x40000000)
     liveins: %r0, %r1
 
     %1 = COPY %r1
     %0 = COPY %r0
     %2, %cpsr = tMUL %0, %1, 14, _
     tSTRspi %2, %stack.1.mul, 0, 14, _ :: (store 4 into %ir.mul)
     tCMPi8 %2, 0, 14, _, implicit-def %cpsr
     tBcc %bb.2.if.end, 12, %cpsr
     tB %bb.1.if.then, 14, _
 
   bb.1.if.then:
-    successors: %bb.3.return(0x80000000)
-
     %4, %cpsr = tMOVi8 42, 14, _
     tSTRspi killed %4, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
     tB %bb.3.return, 14, _
 
   bb.2.if.end:
-    successors: %bb.3.return(0x80000000)
-
     %3, %cpsr = tMOVi8 1, 14, _
     tSTRspi killed %3, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
 
   bb.3.return:
     %5 = tLDRspi %stack.0.retval, 0, 14, _ :: (dereferenceable load 4 from %ir.retval)
     %r0 = COPY %5
     tBX_RET 14, _, implicit %r0
 
 ...

test/CodeGen/ARM/dbg-range-extension.mir

stack:
   - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
   - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r11' }
   - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%r7' }
   - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%r6' }
   - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%r5' }
   - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
 body:             |
   bb.0.entry:
-    successors: %bb.5.if.end, %bb.1.if.then
     liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
   
     %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
     frame-setup CFI_INSTRUCTION def_cfa_offset 24
     frame-setup CFI_INSTRUCTION offset %lr, -4
     frame-setup CFI_INSTRUCTION offset %r11, -8
     frame-setup CFI_INSTRUCTION offset %r7, -12
     frame-setup CFI_INSTRUCTION offset %r6, -16
     frame-setup CFI_INSTRUCTION offset %r5, -20
     frame-setup CFI_INSTRUCTION offset %r4, -24
     DBG_VALUE debug-use %r0, debug-use _, !13, !20, debug-location !21
     %r4 = MOVr killed %r0, 14, _, _
     DBG_VALUE debug-use %r4, debug-use _, !13, !20, debug-location !21
     %r0 = MOVi 10, 14, _, _, debug-location !22
     %r1 = MOVi 11, 14, _, _, debug-location !22
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22
     %r5 = MOVr killed %r0, 14, _, _, debug-location !22
     DBG_VALUE debug-use %r5, debug-use _, !14, !20, debug-location !23
     CMPri %r4, 0, 14, _, implicit-def %cpsr, debug-location !25
     Bcc %bb.5.if.end, 0, killed %cpsr
   
   bb.1.if.then:
-    successors: %bb.3.for.cond
     liveins: %r4, %r5
   
     %r0 = MOVi 12, 14, _, _, debug-location !26
     %r1 = MOVi 13, 14, _, _, debug-location !26
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26
     %r6 = MOVr killed %r0, 14, _, _, debug-location !26
     DBG_VALUE debug-use %r6, debug-use _, !15, !20, debug-location !27
     %r7 = MOVi 1, 14, _, _
     DBG_VALUE 1, 0, !18, !20, debug-location !28
     B %bb.3.for.cond
   
   bb.2.for.body:
-    successors: %bb.3.for.cond
     liveins: %r4, %r5, %r6, %r7
   
     %r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36
     %r0 = MOVr %r7, 14, _, _, debug-location !36
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36
     %r7 = ADDri killed %r7, 1, 14, _, _, debug-location !38
     DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
   
   bb.3.for.cond:
-    successors: %bb.2.for.body, %bb.4.for.cond.cleanup
     liveins: %r4, %r5, %r6, %r7
   
     DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
     CMPrr %r7, %r4, 14, _, implicit-def %cpsr, debug-location !33
     Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
   
   bb.4.for.cond.cleanup:
-    successors: %bb.5.if.end
     liveins: %r4, %r5, %r6
   
     %r0 = MOVr %r5, 14, _, _, debug-location !34
     %r1 = MOVr killed %r6, 14, _, _, debug-location !34
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34
   
   bb.5.if.end:
     liveins: %r4, %r5
   
     %r0 = MOVr killed %r5, 14, _, _, debug-location !43
     %r1 = MOVr killed %r4, 14, _, _, debug-location !43
     %sp = LDMIA_UPD %sp, 14, _, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
     TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43
 
 ...

test/CodeGen/MIR/Generic/branch-probabilities.ll

-; RUN: llc -stop-after machine-sink %s -o %t.mir
-; RUN: FileCheck %s < %t.mir
-; RUN: llc %t.mir -run-pass machine-sink
-; Check that branch probabilities are printed in a format that can then be parsed.
-; This test fails on powerpc because of an undefined physical register use in the MIR.  See PR31062.
-; XFAIL: powerpc
-
-declare void @foo()
-declare void @bar()
-
-define void @test(i1 %c) {
-; CHECK-LABEL: name: test
-entry:
-        br i1 %c, label %then, label %else
-
-then:
-        call void @foo()
-        br label %end
-; CHECK: successors: %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}}), %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}})
-
-else:
-        call void @bar()
-        br label %end
-; CHECK: successors: %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}})
-
-end:
-        ret void
-}

test/CodeGen/MIR/X86/auto-successor.mir

+# RUN: llc -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s
+---
+# We shouldn't need any explicit successor lists in these examples
+# CHECK-LABEL: name: func0
+# CHECK: bb.0:
+# CHECK-NOT: successors
+# CHECK: JE_1 %bb.1, implicit undef %eflags
+# CHECK: JMP_1 %bb.3
+# CHECK: bb.1:
+# CHECK-NOT: successors
+# CHECK: bb.2:
+# CHECK-NOT: successors
+# CHECK: JE_1 %bb.1, implicit undef %eflags
+# CHECK: bb.3:
+# CHECK: RETQ undef %eax
+name: func0
+body: |
+  bb.0:
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.3
+
+  bb.1:
+
+  bb.2:
+    JE_1 %bb.1, implicit undef %eflags
+
+  bb.3:
+    JE_1 %bb.4, implicit undef %eflags   ; condjump+fallthrough to same block
+
+  bb.4:
+    RETQ undef %eax
+...
+---
+# Some cases that need explicit successors:
+# CHECK-LABEL: name: func1
+name: func1
+body: |
+  bb.0:
+    ; CHECK: bb.0:
+    ; CHECK: successors: %bb.3, %bb.1
+    successors: %bb.3, %bb.1   ; different order than operands
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.3
+
+  bb.1:
+    ; CHECK: bb.1:
+    ; CHECK: successors: %bb.2, %bb.1
+    successors: %bb.2, %bb.1   ; different order (fallthrough variant)
+    JE_1 %bb.1, implicit undef %eflags
+
+  bb.2:
+    ; CHECK: bb.2:
+    ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
+    successors: %bb.1(3), %bb.3(1)  ; branch probabilities not normalized
+    JE_1 %bb.1, implicit undef %eflags
+
+  bb.3:
+    ; CHECK: bb.3:
+    ; CHECK: RETQ undef %eax
+    RETQ undef %eax
+...

test/CodeGen/MIR/X86/branch-probabilities.mir

+# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | FileCheck %s
+---
+# Check that branch probabilities are printed correctly as hex numbers.
+# CHECK-LABEL: name: test
+# CHECK: bb.0:
+# CHECK-NEXT: successors: %bb.1(0x66666666), %bb.2(0x1999999a)
+name: test
+body: |
+  bb.0:
+    successors: %bb.1(4), %bb.2(1)
+    JE_1 %bb.2, implicit undef %eflags
+
+  bb.1:
+    NOOP
+
+  bb.2:
+    RETQ undef %eax
+...

test/CodeGen/MIR/X86/successor-basic-blocks.mir

; <label>:1
     ret i32 %a
   }
 
 ...
 ---
 name:            foo
 body: |
   ; CHECK-LABEL: bb.0.entry:
-  ; CHECK:         successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000)
   ; CHECK-LABEL: bb.1.less:
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
     liveins: %edi
 
     CMP32ri8 %edi, 10, implicit-def %eflags
     JG_1 %bb.2.exit, implicit killed %eflags
 

test/CodeGen/X86/branchfolding-undef.mir

 # CHECK-NOT: RET
 # CHECK: bb.2:
 # CHECK-NOT: RET 0, undef %eax
 # CHECK: RET 0, %eax
 name: func
 tracksRegLiveness: true
 body: |
   bb.0:
-    successors: %bb.1, %bb.2
     JE_1 %bb.1, implicit undef %eflags
     JMP_1 %bb.2
 
   bb.1:
     %eax = MOV32ri 2
     RET 0, %eax
 
   bb.2:
     RET 0, undef %eax
 ...

test/CodeGen/X86/eflags-copy-expansion.mir

 ---
 name:            foo
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0.entry:
     liveins: %edi
-    successors: %bb.1.false
     NOOP implicit-def %al
 
     ; The bug was triggered only when LivePhysReg is used, which
     ; happens only when the heuristic for the liveness computation
     ; failed. The liveness computation heuristic looks at 10 instructions
     ; before and after the copy. Make sure we do not reach the definition of
     ; AL in 10 instructions, otherwise the heuristic will see that it is live.
     NOOP

test/CodeGen/X86/implicit-null-checks.mir

liveins:
   - { reg: '%esi' }
 # CHECK:  bb.0.entry:
 # CHECK:    %eax = MOV32ri 2200000
 # CHECK-NEXT:    %eax = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
 # CHECK-NEXT:    JMP_1 %bb.1.not_null
 
 body:             |
   bb.0.entry:
-    successors: %bb.3.is_null, %bb.1.not_null
     liveins: %esi, %rdi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.3.is_null, implicit %eflags
 
   bb.1.not_null:
-    successors: %bb.4.ret_100, %bb.2.ret_200
     liveins: %esi, %rdi
 
     %eax = MOV32ri 2200000
     %eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
     CMP32rr killed %eax, killed %esi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
   bb.2.ret_200:
liveins:
   - { reg: '%rdx' }
 # CHECK: bb.0.entry:
 # CHECK:    %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
 # CHECK-NEXT:    TEST64rr %rdi, %rdi, implicit-def %eflags
 # CHECK-NEXT:    JE_1 %bb.3.is_null, implicit %eflags
 
 body:             |
   bb.0.entry:
-    successors: %bb.3.is_null, %bb.1.not_null
     liveins: %esi, %rdi, %rdx
 
     %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.3.is_null, implicit %eflags
 
   bb.1.not_null:
-    successors: %bb.4.ret_100, %bb.2.ret_200
     liveins: %esi, %rdi
 
     %eax = MOV32ri 2200000
     %eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
     CMP32rr killed %eax, killed %esi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
   bb.2.ret_200:
-    successors: %bb.3.is_null
 
     %eax = MOV32ri 200
 
   bb.3.is_null:
     liveins: %eax, %ah, %al, %ax, %bh, %bl, %bp, %bpl, %bx, %eax, %ebp, %ebx, %rax, %rbp, %rbx, %r12, %r13, %r14, %r15, %r12b, %r13b, %r14b, %r15b, %r12d, %r13d, %r14d, %r15d, %r12w, %r13w, %r14w, %r15w
 
     RETQ %eax
 
liveins:
   - { reg: '%rdi' }
   - { reg: '%esi' }
 # CHECK:  bb.0.entry:
 # CHECK:    TEST64rr %rdi, %rdi, implicit-def %eflags
 # CHECK-NEXT:    JE_1 %bb.3.is_null, implicit %eflags
 
 body:             |
   bb.0.entry:
-    successors: %bb.3.is_null, %bb.1.not_null
     liveins: %esi, %rdi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.3.is_null, implicit %eflags
 
   bb.1.not_null:
-    successors: %bb.4.ret_100, %bb.2.ret_200
     liveins: %esi, %rdi
 
     %eax = MOV32ri 2200000
     %eax = ADD32ri killed %eax, 100, implicit-def dead %eflags
     %eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
     CMP32rr killed %eax, killed %esi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 # CHECK:  bb.0.entry:
 # CHECK:    TEST64rr %rdi, %rdi, implicit-def %eflags
 # CHECK-NEXT:    JE_1 %bb.3.is_null, implicit %eflags
 
 body:             |
   bb.0.entry:
-    successors: %bb.3.is_null, %bb.1.not_null
     liveins: %rsi, %rdi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.3.is_null, implicit %eflags
 
   bb.1.not_null:
-    successors: %bb.4.ret_100, %bb.2.ret_200
     liveins: %rsi, %rdi
 
     %rdi  = MOV64ri 5000
     %rdi = AND64rm killed %rdi, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
     CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
   bb.2.ret_200:
liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 # CHECK:  bb.0.entry:
 # CHECK:  %rbx = MOV64rr %rdx
 # CHECK-NEXT:  %rdi = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
 
 body:             |
   bb.0.entry:
-    successors: %bb.3.is_null, %bb.1.not_null
     liveins: %rsi, %rdi, %rdx
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.3.is_null, implicit %eflags
 
   bb.1.not_null:
-    successors: %bb.4.ret_100, %bb.2.ret_200
     liveins: %rsi, %rdi, %rdx
 
     %rbx  = MOV64rr %rdx
     %rdi = AND64rm killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
     %rdx = MOV64ri 0
     CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
                         '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
                         '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
 # CHECK: body:
 # CHECK-NOT: FAULTING_OP
 # CHECK: bb.1.stay:
 # CHECK: CALL64pcrel32
 body:             |
   bb.0.entry:
-    successors: %bb.2.leave, %bb.1.stay
     liveins: %rdi, %rbx
 
     frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
     CFI_INSTRUCTION def_cfa_offset 16
     CFI_INSTRUCTION offset %rbx, -16
     %rbx = MOV64rr %rdi
     TEST64rr %rbx, %rbx, implicit-def %eflags
     JE_1 %bb.2.leave, implicit killed %eflags

 # the first instruction in bb.1.not_null.
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 # CHECK-NEXT:    JMP_1 %bb.1.not_null
 alignment:       4
 tracksRegLiveness: true
 liveins:         
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000)
     liveins: %rsi, %rdi
   
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.1.is_null, implicit %eflags
   
   bb.2.not_null:
     liveins: %rdi, %rsi
   

 # CHECK-NEXT:    JMP_1 %bb.1.not_null
 alignment:       4
 tracksRegLiveness: true
 liveins:         
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000)
     liveins: %rsi, %rdi
   
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.1.is_null, implicit %eflags
   
   bb.2.not_null:
     liveins: %rdi, %rsi
   

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 liveins:
   - { reg: '%rdi' }
 calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
                         '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
                         '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
                         '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rbx
 
     frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
     CFI_INSTRUCTION def_cfa_offset 16
     CFI_INSTRUCTION offset %rbx, -16
     %rbx = MOV64rr killed %rdi
     TEST64rr %rbx, %rbx, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

 
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 body:             |
   bb.0.entry:
-    successors: %bb.2.is_null, %bb.1.not_null
     liveins: %rdi, %rsi
 
     TEST64rr %rdi, %rdi, implicit-def %eflags
     JE_1 %bb.2.is_null, implicit killed %eflags
 
   bb.1.not_null:
     liveins: %rdi, %rsi
 

test/CodeGen/X86/invalid-liveness.mir

 #
 # CHECK: Use of %vreg0 does not have a corresponding definition on every path
 # CHECK: ERROR: Use not jointly dominated by defs.
 name: func
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0:
-    successors: %bb.2, %bb.3
     JG_1 %bb.2, implicit %eflags
     JMP_1 %bb.3
 
   bb.2:
-    successors: %bb.3
     %0 = IMPLICIT_DEF
     JMP_1 %bb.3
 
   bb.3:
     %eax = COPY %0
     RETQ %eax
 ...

test/CodeGen/X86/machine-region-info.mir

 # RUN: llc -mtriple=x86_64-- -run-pass=machine-region-info %s -debug-only=machine-region-info -o /dev/null 2>&1 | FileCheck %s
 # REQUIRES: asserts
 ---
 name:            fun
 body:             |
   bb.0:
-    successors: %bb.1, %bb.7
-
     CMP32ri8 %edi, 40, implicit-def %eflags
     JNE_1 %bb.7, implicit killed %eflags
     JMP_1 %bb.1
 
   bb.1:
-    successors: %bb.2, %bb.11
-
     CMP32ri8 %edi, 1, implicit-def %eflags
     JNE_1 %bb.11, implicit killed %eflags
     JMP_1 %bb.2
 
   bb.2:
-    successors: %bb.3, %bb.5
-
     CMP32ri8 %edi, 2, implicit-def %eflags
     JNE_1 %bb.5, implicit killed %eflags
     JMP_1 %bb.3
 
   bb.3:
-    successors: %bb.4, %bb.5
-
     CMP32ri8 %edi, 90, implicit-def %eflags
     JNE_1 %bb.5, implicit killed %eflags
     JMP_1 %bb.4
 
   bb.4:
-    successors: %bb.5
 
   bb.5:
-    successors: %bb.6, %bb.11
-
     CMP32ri8 %edi, 4, implicit-def %eflags
     JNE_1 %bb.11, implicit killed %eflags
     JMP_1 %bb.6
 
   bb.6:
-    successors: %bb.11
-
     JMP_1 %bb.11
 
   bb.7:
-    successors: %bb.9, %bb.8
-
     CMP32ri8 %edi, 5, implicit-def %eflags
     JE_1 %bb.9, implicit killed %eflags
     JMP_1 %bb.8
 
   bb.8:
-    successors: %bb.9
 
   bb.9:
-    successors: %bb.11, %bb.10
-
     CMP32ri8 %edi, 6, implicit-def %eflags
     JE_1 %bb.11, implicit killed %eflags
     JMP_1 %bb.10
 
   bb.10:
-    successors: %bb.11
 
   bb.11:
     RET 0
 
 ...
 
 # CHECK: Region tree:
 # CHECK-NEXT: [0] BB#0 => <Function Return>
 # CHECK-NEXT:   [1] BB#0 => BB#11
+# CHECK-NEXT:     [2] BB#7 => BB#9
+# CHECK-NEXT:     [2] BB#9 => BB#11
 # CHECK-NEXT:     [2] BB#1 => BB#11
 # CHECK-NEXT:       [3] BB#2 => BB#5
 # CHECK-NEXT:         [4] BB#3 => BB#5
 # CHECK-NEXT:       [3] BB#5 => BB#11
-# CHECK-NEXT:     [2] BB#7 => BB#9
-# CHECK-NEXT:     [2] BB#9 => BB#11
 # CHECK-NEXT: End region tree

test/CodeGen/X86/pr27681.mir

fixedStack:
   - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%ebx' }
   - { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%ebp' }
 stack:
   - { id: 0, type: spill-slot, offset: -53, size: 1, alignment: 1 }
   - { id: 1, type: spill-slot, offset: -48, size: 4, alignment: 4 }
   - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
 body:             |
   bb.0:
-    successors: %bb.1
     liveins: %ebp, %ebx, %edi, %esi
 
     frame-setup PUSH32r killed %ebp, implicit-def %esp, implicit %esp
     frame-setup PUSH32r killed %ebx, implicit-def %esp, implicit %esp
     frame-setup PUSH32r killed %edi, implicit-def %esp, implicit %esp
     frame-setup PUSH32r killed %esi, implicit-def %esp, implicit %esp
     %esp = frame-setup SUB32ri8 %esp, 36, implicit-def dead %eflags
     %eax = MOV32ri 1
     %ebp = MOV32ri 2
     %ebx = MOV32ri 3
     %ecx = MOV32ri 4
     %edi = MOV32ri 5
     %edx = MOV32ri 6
 
   bb.1:
-    successors: %bb.3, %bb.2
     liveins: %eax, %ebp, %ebx, %ecx, %edi, %edx
 
     %ebp = SHR32rCL killed %ebp, implicit-def dead %eflags, implicit %cl
     %ebp = XOR32rr killed %ebp, killed %ebx, implicit-def dead %eflags
     TEST32rr %edx, %edx, implicit-def %eflags
     %cl = SETNEr implicit %eflags
     ; This %bl def is antidependent on the above use of %ebx
     %bl = MOV8rm %esp, 1, _, 3, _ ; :: (load 1 from %stack.0)
     %cl = OR8rr killed %cl, %bl, implicit-def dead %eflags
     %esi = MOVZX32rr8 killed %cl
     %esi = ADD32rr killed %esi, killed %edi, implicit-def dead %eflags
     %ecx = MOV32rm %esp, 1, _, 24, _ ; :: (load 4 from %stack.2)
     %edx = SAR32rCL killed %edx, implicit-def dead %eflags, implicit %cl
     TEST32rr killed %edx, %edx, implicit-def %eflags
     %cl = SETNEr implicit %eflags
     ; Verify that removal of the %bl antidependence does not use %ch
     ; as a replacement register.
     ; CHECK: %cl = AND8rr %cl, killed %b
     %cl = AND8rr killed %cl, killed %bl, implicit-def dead %eflags
     CMP32ri8 %ebp, -1, implicit-def %eflags
     %edx = MOV32ri 0
     JE_1 %bb.3, implicit %eflags
 
   bb.2:
-    successors: %bb.3
     liveins: %cl, %eax, %ebp, %esi
 
     OR32mr %esp, 1, _, 8, _, killed %eax, implicit-def %eflags ; :: (store 4 into %stack.1)
     %dl = SETNEr implicit %eflags, implicit-def %edx
 
   bb.3:
     liveins: %cl, %ebp, %edx, %esi
 

test/CodeGen/X86/pre-coalesce.mir

frameInfo:
   adjustsStack:    false
   hasCalls:        false
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
-    successors: %bb.4(0x30000000), %bb.1.while.body.preheader(0x50000000)
-  
     %0 = MOV64rm %rip, 1, _, @b, _ :: (dereferenceable load 8 from @b)
     %12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
     TEST8rr %12, %12, implicit-def %eflags
     %11 = MOV32rm %rip, 1, _, @a, _ :: (dereferenceable load 4 from @a)
     JNE_1 %bb.1.while.body.preheader, implicit killed %eflags
   
   bb.4:
-    successors: %bb.3.while.end(0x80000000)
-  
     %10 = COPY %11
     JMP_1 %bb.3.while.end
   
   bb.1.while.body.preheader:
-    successors: %bb.2.while.body(0x80000000)
 
   bb.2.while.body:
-    successors: %bb.3.while.end(0x04000000), %bb.2.while.body(0x7c000000)
-  
     %8 = MOVSX32rr8 %12
     %10 = COPY %11
     %10 = SHL32ri %10, 5, implicit-def dead %eflags
     %10 = ADD32rr %10, %11, implicit-def dead %eflags
     %10 = ADD32rr %10, %8, implicit-def dead %eflags
     MOV32mr %rip, 1, _, @a, _, %10 :: (store 4 into @a)
     %12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
     TEST8rr %12, %12, implicit-def %eflags