The DAG makes it difficult/impossible to make the right
decisions when there are no direct equivalents between SALU
and VALU instructions.
For example, we can use the v_cvt_pk_u16_u32 instruction to
pack a v2i16 if the known high bits are 0. However there is no
scalar equivalent, so pattern matching this in the DAG
introduces divergences from what would be a simple bit pattern.
With known bits, we can pattern match this after it is known
to really be a vector op.
This also may be useful for the SDWA pass.