Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics

[rivanvx]

Summary

Presently AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI.

[arsenm]

Needs tests

lib/Target/AMDGPU/SIISelLowering.cpp

297 ↗

(On Diff #88374)

Should also handle f16?

3478 ↗

(On Diff #88374)

I've been meaning to remove the dependent on the math.h constants. Can you define this somewhere locally?

[rivanvx]

Better version: handle log10 as well, define constants locally, handle f16, do not pretend to handle f64. Tests incoming.

[arsenm]

Needs tests

[jvesely]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

250

v2f32 and v4f32 can be moved to
for (MVT VT : FloatVectorTypes) {
block (line ~398)

1891

Does FDIV have good enough precision to do this? OCL requires 2.5 ULP, and I'm not sure how good the EG/CM hw is.
libclc uses precomputed constants and multiplication, maybe the same can be applied here.

[rivanvx]

TODO: TESTS NEED TO BE UPDATED

Addresed the comments.

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

16–18

Should name something else that doesn't collide with the standard names

test/CodeGen/AMDGPU/llvm.log.f16.ll

3

Can you also add a gfx900 lines for testing <2 x hal>

test/CodeGen/AMDGPU/llvm.log10.ll

4

Remove -mcpu=SI. Also should sort r600 lines later

[rivanvx]

Sorry for the delay, updated patch, now passes tests, addressed all the comments. I would appreciate if you could check if I got all the R_ and A_ prefixes correctly (it's just variable naming, but there is some logic behind it -- register vs address, I presume?) in f16 tests.

[arsenm]

LGTM with minor test cleanup

test/CodeGen/AMDGPU/llvm.log10.ll

3

s/SI/GCN

19

Can you name these vars?

[rivanvx]

This should be it.

[rivanvx]

That was only a partial diff, should be correct now.

[jvesely]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1895

You can pass the log2base constant here to avoid second switch and simplify the code. Just a nitpick

1914

Using FMUL and inverted Log2Base should be both faster and more precise.

[rivanvx]

@jvesely I would like to get an ACK before I tackle the tests.

[jvesely]

looks ok to me. hope you were not waiting for me this whole time.

[rivanvx]

In D29942#861582, @jvesely wrote:

looks ok to me. hope you were not waiting for me this whole time.

No, absolutely not, it was a combination of limited time for Clover/Clang/LLVM and reluctance to finish things that are almost done but not "interesting" to complete. Thanks for the OK, full patch coming much sooner than this one. :-)

[rivanvx]

This should be it.

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUISelLowering.h

   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag) const;
 
   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
 

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 //
 //===----------------------------------------------------------------------===//
 
+#define M_LOG2E_F     1.44269504088896340735992468100189214f
+#define M_LN2_F       0.693147180559945309417232121458176568f
+#define M_LN10_F      2.30258509299404568401799145468436421f
+
 #include "AMDGPUISelLowering.h"
 #include "AMDGPU.h"
 #include "AMDGPUCallLowering.h"

   setOperationAction(ISD::FREM, MVT::f32, Custom);
   setOperationAction(ISD::FREM, MVT::f64, Custom);
 
+  setOperationAction(ISD::FLOG, MVT::f32, Custom);
+  setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
+  setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
+  setOperationAction(ISD::FLOG10, MVT::f32, Custom);
+  setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
+  setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
+
   // v_mad_f32 does not support denormals according to some sources.
   if (!Subtarget->hasFP32Denormals())
     setOperationAction(ISD::FMAD, MVT::f32, Legal);

   // Expand to fneg + fadd.
   setOperationAction(ISD::FSUB, MVT::f64, Expand);
 
+  if (Subtarget->has16BitInsts()) {
+    setOperationAction(ISD::FLOG, MVT::f16, Custom);
+    setOperationAction(ISD::FLOG10, MVT::f16, Custom);
+  }
+
   setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
   setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
   setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);

   case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
   case ISD::FROUND: return LowerFROUND(Op, DAG);
   case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
+  case ISD::FLOG:
+  case ISD::FLOG10:
+    return LowerFLOG(Op, DAG);
   case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
   case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
   case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);

   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
 }
 
+SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+
+  SDLoc SL(Op);
+  SDValue Operand = Op.getOperand(0);
+
+  SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
+  SDValue Log2Base;
+  switch (Op.getOpcode()) {
+  case ISD::FLOG:
+    Log2Base = DAG.getConstantFP(M_LOG2E_F, SL, VT);
+    break;
+  case ISD::FLOG10:
+    Log2Base = DAG.getConstantFP(M_LN10_F / M_LN2_F, SL, VT);
+    break;
+  default:
+    llvm_unreachable("Wrong log opcode");
+  }
+
+  return DAG.getNode(ISD::FDIV, SL, VT, Log2Operand, Log2Base);
+}
+
 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
   SDLoc SL(Op);
   SDValue Src = Op.getOperand(0);

test/CodeGen/AMDGPU/llvm.log.f16.ll

+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare half @llvm.log.f16(half %a)
+declare <2 x half> @llvm.log.v2f16(<2 x half> %a)
+
+; GCN-LABEL: {{^}}log_f16
+; GCN: buffer_load_ushort v[[A_F16_0:[0-9]+]]
+; SI:  v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
+; SI:  v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
+; SI:  v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:  v_div_scale_f32 v[[A_F32_2:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, v[[A_F32_1]], v[[A_F32_1]], v[[A_F32_0]]
+; SI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; VI:  v_rcp_f32_e32 v[[A_F32_0:[0-9]+]]
+; VI:  v_log_f16_e32 v[[R_F16_1:[0-9]+]], v[[A_F16_0]]
+; VI:  v_cvt_f32_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_1]]
+; VI:  v_mul_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[R_F32_2]]
+; VI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; GCN: buffer_store_short v[[R_F16_0]]
+; GCN: s_endpgm
+define void @log_f16(
+    half addrspace(1)* %r,
+    half addrspace(1)* %a) {
+entry:
+  %a.val = load half, half addrspace(1)* %a
+  %r.val = call half @llvm.log.f16(half %a.val)
+  store half %r.val, half addrspace(1)* %r
+  ret void
+}
+
+; GCN-LABEL: {{^}}log_v2f16
+; GCN: buffer_load_dword v[[A_F16_0:[0-9]+]]
+; SI:  v_mov_b32_e32 v[[A_F32_2:[0-9]+]]
+; SI:  v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
+; VI:  v_rcp_f32_e32 v[[A_F32_0:[0-9]+]]
+; GCN: v_lshrrev_b32_e32 v[[R_F16_0:[0-9]+]], 16, v[[A_F16_0]]
+; SI:  v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[R_F16_0]]
+; SI:  v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
+; SI:  v_div_scale_f32 v[[A_F32_3:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, v[[A_F32_2]], v[[A_F32_2]], v[[R_F32_1]]
+; SI:  v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:  v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
+; SI:  v_div_scale_f32 v[[A_F32_3:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, v[[A_F32_2]], v[[A_F32_2]], v[[R_F32_0]]
+; VI:  v_log_f16_e32 v[[R_F16_1:[0-9]+]], v[[A_F16_0]]
+; VI:  v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[R_F16_0]]
+; VI:  v_cvt_f32_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_1]]
+; VI:  v_cvt_f32_f16_e32 v[[R_F32_4:[0-9]+]], v[[R_F16_2]]
+; VI:  v_mul_f32_e32 v[[R_F32_3:[0-9]+]], v[[A_F32_0]], v[[R_F32_3]]
+; VI:  v_mul_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[R_F32_4]]
+; VI:  v_cvt_f16_f32_e32 v[[R_F16_3:[0-9]+]], v[[R_F32_3]]
+; VI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; GCN: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_1]]
+; SI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; GCN: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
+; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_LO]]
+; GCN: buffer_store_dword v[[R_V2_F16]]
+; GCN: s_endpgm
+define void @log_v2f16(
+    <2 x half> addrspace(1)* %r,
+    <2 x half> addrspace(1)* %a) {
+entry:
+  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
+  %r.val = call <2 x half> @llvm.log.v2f16(<2 x half> %a.val)
+  store <2 x half> %r.val, <2 x half> addrspace(1)* %r
+  ret void
+}

test/CodeGen/AMDGPU/llvm.log.ll

+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
+; RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI --check-prefix=FUNC
+; RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC
+
+; FUNC-LABEL: {{^}}test:
+; EG: LOG_IEEE
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+
+define void @test(float addrspace(1)* %out, float %in) {
+entry:
+   %0 = call float @llvm.log.f32(float %in)
+   store float %0, float addrspace(1)* %out
+   ret void
+}
+
+; FUNC-LABEL: {{^}}testv2:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+
+define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+entry:
+  %0 = call <2 x float> @llvm.log.v2f32(<2 x float> %in)
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}testv4:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
+entry:
+  %0 = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
+  store <4 x float> %0, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+declare float @llvm.log.f32(float) readnone
+declare <2 x float> @llvm.log.v2f32(<2 x float>) readnone
+declare <4 x float> @llvm.log.v4f32(<4 x float>) readnone

test/CodeGen/AMDGPU/llvm.log10.f16.ll

+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare half @llvm.log10.f16(half %a)
+declare <2 x half> @llvm.log10.v2f16(<2 x half> %a)
+
+; GCN-LABEL: {{^}}log10_f16
+; GCN: buffer_load_ushort v[[A_F16_0:[0-9]+]]
+; SI:  v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
+; SI:  v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
+; SI:  v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:  v_div_scale_f32 v[[A_F32_2:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, v[[A_F32_1]], v[[A_F32_1]], v[[A_F32_0]]
+; SI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; VI:  v_rcp_f32_e32 v[[A_F32_0:[0-9]+]]
+; VI:  v_log_f16_e32 v[[R_F16_1:[0-9]+]], v[[A_F16_0]]
+; VI:  v_cvt_f32_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_1]]
+; VI:  v_mul_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[R_F32_2]]
+; VI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; GCN: buffer_store_short v[[R_F16_0]]
+; GCN: s_endpgm
+define void @log10_f16(
+    half addrspace(1)* %r,
+    half addrspace(1)* %a) {
+entry:
+  %a.val = load half, half addrspace(1)* %a
+  %r.val = call half @llvm.log10.f16(half %a.val)
+  store half %r.val, half addrspace(1)* %r
+  ret void
+}
+
+; GCN-LABEL: {{^}}log10_v2f16
+; GCN: buffer_load_dword v[[A_F16_0:[0-9]+]]
+; SI:  v_mov_b32_e32 v[[A_F32_2:[0-9]+]]
+; SI:  v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
+; VI:  v_rcp_f32_e32 v[[A_F32_0:[0-9]+]]
+; GCN: v_lshrrev_b32_e32 v[[R_F16_0:[0-9]+]], 16, v[[A_F16_0]]
+; SI:  v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[R_F16_0]]
+; SI:  v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
+; SI:  v_div_scale_f32 v[[A_F32_3:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, v[[A_F32_2]], v[[A_F32_2]], v[[R_F32_1]]
+; SI:  v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:  v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
+; SI:  v_div_scale_f32 v[[A_F32_3:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, v[[A_F32_2]], v[[A_F32_2]], v[[R_F32_0]]
+; VI:  v_log_f16_e32 v[[R_F16_1:[0-9]+]], v[[A_F16_0]]
+; VI:  v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[R_F16_0]]
+; VI:  v_cvt_f32_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_1]]
+; VI:  v_cvt_f32_f16_e32 v[[R_F32_4:[0-9]+]], v[[R_F16_2]]
+; VI:  v_mul_f32_e32 v[[R_F32_3:[0-9]+]], v[[A_F32_0]], v[[R_F32_3]]
+; VI:  v_mul_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[R_F32_4]]
+; VI:  v_cvt_f16_f32_e32 v[[R_F16_3:[0-9]+]], v[[R_F32_3]]
+; VI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; GCN: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_1]]
+; SI:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
+; GCN: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
+; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_LO]]
+; GCN: buffer_store_dword v[[R_V2_F16]]
+; GCN: s_endpgm
+define void @log10_v2f16(
+    <2 x half> addrspace(1)* %r,
+    <2 x half> addrspace(1)* %a) {
+entry:
+  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
+  %r.val = call <2 x half> @llvm.log10.v2f16(<2 x half> %a.val)
+  store <2 x half> %r.val, <2 x half> addrspace(1)* %r
+  ret void
+}

test/CodeGen/AMDGPU/llvm.log10.ll

+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
+; RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI --check-prefix=FUNC
+; RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC
+
+; FUNC-LABEL: {{^}}test:
+; EG: LOG_IEEE
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+
+define void @test(float addrspace(1)* %out, float %in) {
+entry:
+   %0 = call float @llvm.log10.f32(float %in)
+   store float %0, float addrspace(1)* %out
+   ret void
+}
+
+; FUNC-LABEL: {{^}}testv2:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+
+define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+entry:
+  %0 = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}testv4:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+; SI: v_log_f32
+; SI: v_div_scale_f32
+; SI: v_div_scale_f32
+define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
+entry:
+  %0 = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
+  store <4 x float> %0, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+declare float @llvm.log10.f32(float) readnone
+declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone
+declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone