Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics

[rivanvx]

Summary

Presently AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI.

[arsenm]

Needs tests

lib/Target/AMDGPU/SIISelLowering.cpp

297

Should also handle f16?

3478

I've been meaning to remove the dependent on the math.h constants. Can you define this somewhere locally?

[rivanvx]

Better version: handle log10 as well, define constants locally, handle f16, do not pretend to handle f64. Tests incoming.

[arsenm]

Needs tests

[jvesely]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

250 ↗

(On Diff #89036)

v2f32 and v4f32 can be moved to
for (MVT VT : FloatVectorTypes) {
block (line ~398)

1891 ↗

(On Diff #89036)

Does FDIV have good enough precision to do this? OCL requires 2.5 ULP, and I'm not sure how good the EG/CM hw is.
libclc uses precomputed constants and multiplication, maybe the same can be applied here.

[rivanvx]

TODO: TESTS NEED TO BE UPDATED

Addresed the comments.

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

16–18 ↗

(On Diff #91190)

Should name something else that doesn't collide with the standard names

test/CodeGen/AMDGPU/llvm.log.f16.ll

2 ↗

(On Diff #91190)

Can you also add a gfx900 lines for testing <2 x hal>

test/CodeGen/AMDGPU/llvm.log10.ll

3 ↗

(On Diff #91190)

Remove -mcpu=SI. Also should sort r600 lines later

[rivanvx]

Sorry for the delay, updated patch, now passes tests, addressed all the comments. I would appreciate if you could check if I got all the R_ and A_ prefixes correctly (it's just variable naming, but there is some logic behind it -- register vs address, I presume?) in f16 tests.

[arsenm]

LGTM with minor test cleanup

test/CodeGen/AMDGPU/llvm.log10.ll

2 ↗

(On Diff #95598)

s/SI/GCN

18 ↗

(On Diff #95598)

Can you name these vars?

[rivanvx]

This should be it.

[rivanvx]

That was only a partial diff, should be correct now.

[jvesely]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1895 ↗

(On Diff #95718)

You can pass the log2base constant here to avoid second switch and simplify the code. Just a nitpick

1914 ↗

(On Diff #95718)

Using FMUL and inverted Log2Base should be both faster and more precise.

[rivanvx]

@jvesely I would like to get an ACK before I tackle the tests.

[jvesely]

looks ok to me. hope you were not waiting for me this whole time.

[rivanvx]

In D29942#861582, @jvesely wrote:

looks ok to me. hope you were not waiting for me this whole time.

No, absolutely not, it was a combination of limited time for Clover/Clang/LLVM and reluctance to finish things that are almost done but not "interesting" to complete. Thanks for the OK, full patch coming much sooner than this one. :-)

[rivanvx]

This should be it.

[arsenm]

LGTM

lib/Target/AMDGPU/SIISelLowering.h

   SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag) const;
   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;

lib/Target/AMDGPU/SIISelLowering.cpp

   setOperationAction(ISD::FDIV, MVT::f32, Custom);
   setOperationAction(ISD::FDIV, MVT::f64, Custom);
 
+  setOperationAction(ISD::FLOG, MVT::f32, Custom);
+  setOperationAction(ISD::FLOG, MVT::f64, Custom);
+
   if (Subtarget->has16BitInsts()) {
     setOperationAction(ISD::Constant, MVT::i16, Legal);
 

     return LowerTrig(Op, DAG);
   case ISD::SELECT: return LowerSELECT(Op, DAG);
   case ISD::FDIV: return LowerFDIV(Op, DAG);
+  case ISD::FLOG: return LowerFLOG(Op, DAG);
   case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
   case ISD::STORE: return LowerSTORE(Op, DAG);
   case ISD::GlobalAddress: {

   llvm_unreachable("Unexpected type for fdiv");
 }
 
+SDValue SITargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+
+  SDLoc SL(Op);
+  SDValue Operand = Op.getOperand(0);
+
+  SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
+  const SDValue Log2e = DAG.getConstantFP(M_LOG2E, SL, VT);
+
+  return DAG.getNode(ISD::FDIV, SL, VT, Log2Operand, Log2e);
+}
+
 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   StoreSDNode *Store = cast<StoreSDNode>(Op);