[ARM] Replace HasT2ExtractPack with HasDSP

[samparker]

Summary

Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel.

[zzheng]

lib/Target/ARM/ARMSubtarget.h

171

Any reason they needed to be commented out rather than removed?

[samparker]

lib/Target/ARM/ARMSubtarget.h

171

Ah, no! Just something I missed. Thanks.

[samparker]

Removed a few lines which I had just commented out before.

[rovka]

This looks mechanically sound to me, and I'm always in favor of removing subtarget features if we don't really need them. That being said, I'd appreciate it if someone that knows more about these extensions gave the final ok.

lib/Target/ARM/ARMInstrThumb2.td

1145

You mean Requires DSP, right?

test/CodeGen/Thumb2/thumb2-sxt-uxt.ll

39

You should share the same check prefixes for the similar cases, e.g. CHECK-NO-DSP for cortex-m3 and armv8m, and CHECK-DSP for the others. Then you don't have to repeat yourself in the checks :)

Same for the other test files.

41

This is too tight, I think it's better to use CHECK-NOT: sxtab (like you did in the other test files) since you don't want to see sxtab _at all_ (the registers don't matter).

test/CodeGen/Thumb2/thumb2-uxt_rot.ll

29

Same as above, get rid of the registers here.

test/CodeGen/Thumb2/thumb2-uxtb.ll

12

Same as above (in the whole file)

[samparker]

Hi Diana,

Thanks for the testing tips, I'll make the changes. For the flags I found that no target specified T2Extract without specifying DSP and I only found a single test that referenced it. I also crossed checked the manuals and couldn't see why the extract instructions had been predicated on that specify flag.

Thanks,
sam

[samparker]

Simplified the tests.

[olista01]

I've had a look through the architecture manuals, and I think we do need two different features here.

For example:

• The QADD instruction (currently predicated on FeatureDSP) was introduced by the DSP extension to ARMv5 (aka ARMv5TE)
• The SXTAB instruction (currently predicated on FeatureT2XtPk) was introduced by ARMv6 (but is also optionally available as part of the DSP extension to ARMv7-M)

Therefore, I think we need to keep two separate features. However, we may be able to make FeatureT2XtPk depend on FeatureDSP, as I haven't been able to find any architecture where SXTAB is available without QADD.

[samparker]

Hi Oli,

As far as I can see, instructions such as QADD aren't available for Thumb prior to T2 so predicating these instructions on IsThumb2 and HasDSP should cover them. I think the same is true for SXTAB, the difference between v7M and v7E-M targets is the HasDSP feature and the tests hopefully proved that SXTAB is only selected in the correct cases. Since HasT2ExtractPack was never defined without HasDSP, I can't see how this can break the expected functionality.

cheers

[olista01]

LGTM

lib/Target/ARM/ARM.td

                                        [FeatureFPARMv8]>;
 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
                                      "Restrict FP to 16 double registers">;
 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
                                      "Enable divide instructions">;
 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
                                         "HasHardwareDivideInARM", "true",
                                       "Enable divide instructions in ARM mode">;
-def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
-                                 "Enable Thumb2 extract and pack instructions">;
 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
                                    "Has data barrier (dmb / dsb) instructions">;
 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
                                       "Has v7 clrex instruction">;
 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
                                              "HasAcquireRelease", "true",
                          "Has v8 acquire/release (lda/ldaex etc) instructions">;
 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",

                                    "Support ARM v6t2 instructions",
                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
                                    "Support ARM v7 instructions",
                                    [HasV6T2Ops, FeaturePerfMon,
                                     FeatureV7Clrex]>;
 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
                                    "Support ARM v8 instructions",
-                                   [HasV7Ops, FeatureAcquireRelease,
-                                    FeatureT2XtPk]>;
+                                   [HasV7Ops, FeatureAcquireRelease]>;
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
                                    "Support ARM v8.1a instructions",
                                    [HasV8Ops]>;
 def HasV8_2aOps   : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
                                    "Support ARM v8.2a instructions",
                                    [HasV8_1aOps]>;
 def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
                                          "Support ARM v8M Mainline instructions",

 
 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 
 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 
 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
 
 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
-                                                       FeatureDSP,
-                                                       FeatureT2XtPk]>;
+                                                       FeatureDSP]>;
 
 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 
 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
                                                        FeatureTrustZone]>;
 
 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureMClass]>;
 
 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureMClass]>;
 
 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
                                                        FeatureNEON,
                                                        FeatureDB,
                                                        FeatureDSP,
-                                                       FeatureAClass,
-                                                       FeatureT2XtPk]>;
+                                                       FeatureAClass]>;
 
 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
                                                        FeatureDB,
                                                        FeatureDSP,
                                                        FeatureHWDiv,
-                                                       FeatureRClass,
-                                                       FeatureT2XtPk]>;
+                                                       FeatureRClass]>;
 
 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
                                                        FeatureThumb2,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureHWDiv,
                                                        FeatureMClass]>;
 
 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
                                                        FeatureThumb2,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureHWDiv,
                                                        FeatureMClass,
-                                                       FeatureDSP,
-                                                       FeatureT2XtPk]>;
+                                                       FeatureDSP]>;
 
 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
                                                        FeatureAClass,
                                                        FeatureDB,
                                                        FeatureFPARMv8,
                                                        FeatureNEON,
                                                        FeatureDSP,
                                                        FeatureTrustZone,

                                                        FeatureCRC,
                                                        FeatureRAS]>;
 
 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
                                                        FeatureRClass,
                                                        FeatureDB,
                                                        FeatureHWDiv,
                                                        FeatureHWDivARM,
-                                                       FeatureT2XtPk,
                                                        FeatureDSP,
                                                        FeatureCRC,
                                                        FeatureMP,
                                                        FeatureVirtualization,
                                                        FeatureFPARMv8,
                                                        FeatureNEON]>;
 
 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",

                                                          FeatureFPARMv8,
                                                          FeatureD16]>;
 
 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
                                                          FeatureNoMovt]>;
 
 def : ProcNoItin<"cortex-m33",                          [ARMv8mMainline,
                                                          FeatureDSP,
-                                                         FeatureT2XtPk,
                                                          FeatureFPARMv8,
                                                          FeatureD16,
                                                          FeatureVFPOnlySP]>;
 
 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,

lib/Target/ARM/ARMISelLowering.cpp

     unsigned Mask2 = N11C->getZExtValue();
 
     // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
     // as is to match.
     if (ARM::isBitFieldInvertedMask(Mask) &&
         (Mask == ~Mask2)) {
       // The pack halfword instruction works better for masks that fit it,
       // so use that when it's available.
-      if (Subtarget->hasT2ExtractPack() &&
+      if (Subtarget->hasDSP() &&
           (Mask == 0xffff || Mask == 0xffff0000))
         return SDValue();
       // 2a
       unsigned amt = countTrailingZeros(Mask2);
       Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
                         DAG.getConstant(amt, DL, MVT::i32));
       Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
                         DAG.getConstant(Mask, DL, MVT::i32));
       // Do not add new nodes to DAG combiner worklist.
       DCI.CombineTo(N, Res, false);
       return SDValue();
     } else if (ARM::isBitFieldInvertedMask(~Mask) &&
                (~Mask == Mask2)) {
       // The pack halfword instruction works better for masks that fit it,
       // so use that when it's available.
-      if (Subtarget->hasT2ExtractPack() &&
+      if (Subtarget->hasDSP() &&
           (Mask2 == 0xffff || Mask2 == 0xffff0000))
         return SDValue();
       // 2b
       unsigned lsb = countTrailingZeros(Mask);
       Res = DAG.getNode(ISD::SRL, DL, VT, N00,
                         DAG.getConstant(lsb, DL, MVT::i32));
       Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
                         DAG.getConstant(Mask2, DL, MVT::i32));

lib/Target/ARM/ARMInstrFormats.td

   list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
 }
 class Thumb2DSPPat<dag pattern, dag result> : Pat<pattern, result> {
   list<Predicate> Predicates = [IsThumb2, HasDSP];
 }
 class Thumb2DSPMulPat<dag pattern, dag result> : Pat<pattern, result> {
   list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
 }
-class Thumb2ExtractPat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsThumb2, HasT2ExtractPack];
-}
 //===----------------------------------------------------------------------===//
 // Thumb Instruction Format Definitions.
 //
 
 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
              InstrItinClass itin, string asm, string cstr, list<dag> pattern>
   : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
   let OutOperandList = oops;

lib/Target/ARM/ARMInstrInfo.td

 def HasFP16          : Predicate<"Subtarget->hasFP16()">,
                                  AssemblerPredicate<"FeatureFP16","half-float conversions">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicate<"FeatureFullFP16","full half-float">;
 def HasDivide        : Predicate<"Subtarget->hasDivide()">,
                                  AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
 def HasDivideInARM   : Predicate<"Subtarget->hasDivideInARMMode()">,
                                  AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
-def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
-                                 AssemblerPredicate<"FeatureT2XtPk",
-                                                     "pack/extract">;
 def HasDSP           : Predicate<"Subtarget->hasDSP()">,
                                  AssemblerPredicate<"FeatureDSP", "dsp">;
 def HasDB            : Predicate<"Subtarget->hasDataBarrier()">,
                                  AssemblerPredicate<"FeatureDB",
                                                     "data-barriers">;
 def HasV7Clrex  : Predicate<"Subtarget->hasV7Clrex()">,
                             AssemblerPredicate<"FeatureV7Clrex",
                                                "v7 clrex">;

lib/Target/ARM/ARMInstrThumb2.td

     let Inst{19-16}   = addr{9-6}; // Rn
     let Inst{3-0} = addr{5-2}; // Rm
     let Inst{5-4}   = addr{1-0}; // imm
   }
 }
 
 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
-class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
-  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
-             opc, ".w\t$Rd, $Rm$rot",
-             [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
-             Requires<[IsThumb2]> {
-   let Inst{31-27} = 0b11111;
-   let Inst{26-23} = 0b0100;
-   let Inst{22-20} = opcod;
-   let Inst{19-16} = 0b1111; // Rn
-   let Inst{15-12} = 0b1111;
-   let Inst{7} = 1;
-
-   bits<2> rot;
-   let Inst{5-4} = rot{1-0}; // rotate
-}
-
-// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
-class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
-  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
-             IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
-            [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
-          Requires<[HasT2ExtractPack, IsThumb2]> {
+class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops,
+                        string opc, string oprs,
+                        list<dag> pattern>
+  : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> {
   bits<2> rot;
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0100;
   let Inst{22-20} = opcod;
   let Inst{19-16} = 0b1111; // Rn
   let Inst{15-12} = 0b1111;
   let Inst{7} = 1;
-  let Inst{5-4} = rot;
+  let Inst{5-4} = rot; // rotate
 }
 
-// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
-// supported yet.
-class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
-  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
-             opc, "\t$Rd, $Rm$rot", []>,
-          Requires<[IsThumb2, HasT2ExtractPack]> {
-  bits<2> rot;
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0100;
-  let Inst{22-20} = opcod;
-  let Inst{19-16} = 0b1111; // Rn
-  let Inst{15-12} = 0b1111;
-  let Inst{7} = 1;
-  let Inst{5-4} = rot;
-}
+class T2I_ext_rrot<bits<3> opcod, string opc>
+  : T2I_ext_rrot_base<opcod,
+                      (outs rGPR:$Rd),
+                      (ins rGPR:$Rm, rot_imm:$rot),
+                      opc, ".w\t$Rd, $Rm$rot", []>,
+                      Requires<[IsThumb2]>;
+
+// UXTB16, SXTB16 - Requires T2ExtractPack, does not need the .w qualifier.
+class T2I_ext_rrot_xtb16<bits<3> opcod, string opc>
+  : T2I_ext_rrot_base<opcod,
+                      (outs rGPR:$Rd),
+                      (ins rGPR:$Rm, rot_imm:$rot),
+                      opc, "\t$Rd, $Rm$rot", []>,
+                      Requires<[HasDSP, IsThumb2]>;
 
 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
-class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
+class T2I_exta_rrot<bits<3> opcod, string opc>
   : T2ThreeReg<(outs rGPR:$Rd),
                (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
-               IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
-             [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
-           Requires<[HasT2ExtractPack, IsThumb2]> {
-  bits<2> rot;
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0100;
-  let Inst{22-20} = opcod;
-  let Inst{15-12} = 0b1111;
-  let Inst{7} = 1;
-  let Inst{5-4} = rot;
-}
-
-class T2I_exta_rrot_np<bits<3> opcod, string opc>
-  : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
                IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
-               Requires<[HasT2ExtractPack, IsThumb2]> {
+               Requires<[HasDSP, IsThumb2]> {
   bits<2> rot;
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0100;
   let Inst{22-20} = opcod;
   let Inst{15-12} = 0b1111;
   let Inst{7} = 1;
   let Inst{5-4} = rot;
 }

 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
 
 //===----------------------------------------------------------------------===//
 //  Extend Instructions.
 //
 
 // Sign extenders
 
-def t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
-                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
-def t2SXTH  : T2I_ext_rrot<0b000, "sxth",
-                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
-def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
+def t2SXTB  : T2I_ext_rrot<0b100, "sxtb">;
+def t2SXTH  : T2I_ext_rrot<0b000, "sxth">;
+def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
+
+def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;
+def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
+def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;
+
+def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8),
+            (t2SXTB rGPR:$Rn, rot_imm:$rot)>;
+def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16),
+            (t2SXTH rGPR:$Rn, rot_imm:$rot)>;
+def : Thumb2DSPPat<(add rGPR:$Rn,
+                            (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)),
+            (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
+def : Thumb2DSPPat<(add rGPR:$Rn,
+                            (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)),
+            (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
 
-def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
-                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
-def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
-                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
-def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
 
 // A simple right-shift can also be used in most cases (the exception is the
 // SXTH operations with a rotate of 24: there the non-contiguous bits are
 // relevant).
-def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
+def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
                                         (srl rGPR:$Rm, rot_imm:$rot), i8)),
                        (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
-def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
+def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
                                         (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
                        (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
-def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
+def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
                                         (rotr rGPR:$Rm, (i32 24)), i16)),
                        (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
-def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg
+def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
                                         (or (srl rGPR:$Rm, (i32 24)),
                                               (shl rGPR:$Rm, (i32 8))), i16)),
                        (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
 
 // Zero extenders
 
 let AddedComplexity = 16 in {
-def t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
-                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
-def t2UXTH   : T2I_ext_rrot<0b001, "uxth",
-                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
-def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
-                                   UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
+def t2UXTB   : T2I_ext_rrot<0b101, "uxtb">;
+def t2UXTH   : T2I_ext_rrot<0b001, "uxth">;
+def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;
+
+def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),
+                       (t2UXTB rGPR:$Rm, rot_imm:$rot)>;
+def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),
+                       (t2UXTH rGPR:$Rm, rot_imm:$rot)>;
+def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),
+                       (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>;
 
 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
 //        The transformation should probably be done as a combiner action
 //        instead so we can include a check for masking back in the upper
 //        eight bits of the source into the lower eight bits of the result.
 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
 //            (t2UXTB16 rGPR:$Src, 3)>,
 //          Requires<[HasT2ExtractPack, IsThumb2]>;
 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
             (t2UXTB16 rGPR:$Src, 1)>,
-        Requires<[HasT2ExtractPack, IsThumb2]>;
+        Requires<[HasDSP, IsThumb2]>;
 
-def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
-                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
-def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
-                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
-def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
+def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;
+def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;
+def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;
 
-def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
+def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
+                                            0x00FF)),
+                       (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
+def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
+                                            0xFFFF)),
+                       (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
+def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
                                            0xFF)),
                        (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
-def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
+def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
                                             0xFFFF)),
                        (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
 }
 
 
 //===----------------------------------------------------------------------===//
 //  Arithmetic Instructions.
 //

             (t2REVSH rGPR:$Rm)>;
 
 def t2PKHBT : T2ThreeReg<
             (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
                   IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
                   [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
                                       (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
                                            0xFFFF0000)))]>,
-                  Requires<[HasT2ExtractPack, IsThumb2]>,
+                  Requires<[HasDSP, IsThumb2]>,
                   Sched<[WriteALUsi, ReadALU]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-20} = 0b01100;
   let Inst{5} = 0; // BT form
   let Inst{4} = 0;
 
   bits<5> sh;
   let Inst{14-12} = sh{4-2};
   let Inst{7-6}   = sh{1-0};
 }
 
 // Alternate cases for PKHBT where identities eliminate some nodes.
 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
             (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
             (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 
 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
 // will match the pattern below.
 def t2PKHTB : T2ThreeReg<
                   (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
                   IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
                   [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
                                        (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
                                             0xFFFF)))]>,
-                  Requires<[HasT2ExtractPack, IsThumb2]>,
+                  Requires<[HasDSP, IsThumb2]>,
                   Sched<[WriteALUsi, ReadALU]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-20} = 0b01100;
   let Inst{5} = 1; // TB form
   let Inst{4} = 0;
 
   bits<5> sh;
   let Inst{14-12} = sh{4-2};
   let Inst{7-6}   = sh{1-0};
 }
 
 // Alternate cases for PKHTB where identities eliminate some nodes.  Note that
 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
 // pkhtb src1, src2, asr (17..31).
 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
             (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
             (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
                 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
             (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 
 //===----------------------------------------------------------------------===//
 // CRC32 Instructions
 //
 // Polynomials:
 // + CRC32{B,H,W}       0x04C11DB7
 // + CRC32C{B,H,W}      0x1EDC6F41
 //

 
 // SXT/UXT with no rotate
 let AddedComplexity = 16 in {
 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
            Requires<[IsThumb2]>;
 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
            Requires<[IsThumb2]>;
 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
-           Requires<[HasT2ExtractPack, IsThumb2]>;
+           Requires<[HasDSP, IsThumb2]>;
 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
             (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
-           Requires<[HasT2ExtractPack, IsThumb2]>;
+           Requires<[HasDSP, IsThumb2]>;
 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
             (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
-           Requires<[HasT2ExtractPack, IsThumb2]>;
+           Requires<[HasDSP, IsThumb2]>;
 }
 
 def : T2Pat<(sext_inreg rGPR:$Src, i8),  (t2SXTB rGPR:$Src, 0)>,
            Requires<[IsThumb2]>;
 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
            Requires<[IsThumb2]>;
 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
             (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
-           Requires<[HasT2ExtractPack, IsThumb2]>;
+           Requires<[HasDSP, IsThumb2]>;
 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
             (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
-           Requires<[HasT2ExtractPack, IsThumb2]>;
+           Requires<[HasDSP, IsThumb2]>;
 
 // Atomic load/store patterns
 def : T2Pat<(atomic_load_8   t2addrmode_imm12:$addr),
             (t2LDRBi12  t2addrmode_imm12:$addr)>;
 def : T2Pat<(atomic_load_8   t2addrmode_negimm8:$addr),
             (t2LDRBi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_load_8   t2addrmode_so_reg:$addr),
             (t2LDRBs    t2addrmode_so_reg:$addr)>;

            (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
            (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
 
 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
 // input operands swapped when the shift amount is zero (i.e., unspecified).
 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
                 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
                 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
-            Requires<[HasT2ExtractPack, IsThumb2]>;
+            Requires<[HasDSP, IsThumb2]>;
 
 // PUSH/POP aliases for STM/LDM
 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 
 // STMIA/STMIA_UPD aliases w/o the optional .w suffix

 def : t2InstAlias<"strb${p} $Rt, $addr",
                   (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
 def : t2InstAlias<"strh${p} $Rt, $addr",
                   (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
 
 // Extend instruction optional rotate operand.
 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
               (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
               (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
               (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"sxtb16${p} $Rd, $Rm",
               (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 
 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
                 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"sxth${p} $Rd, $Rm",
                 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
                 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
                 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 
 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
               (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
               (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
               (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 def : InstAlias<"uxtb16${p} $Rd, $Rm",
               (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
-              Requires<[HasT2ExtractPack, IsThumb2]>;
+              Requires<[HasDSP, IsThumb2]>;
 
 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
                 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"uxth${p} $Rd, $Rm",
                 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
                 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
                 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
 
 // Extend instruction w/o the ".w" optional width specifier.
 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
                   (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
                 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
-                Requires<[HasT2ExtractPack, IsThumb2]>;
+                Requires<[HasDSP, IsThumb2]>;
 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
                   (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
 
 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
                   (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
                 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
-                Requires<[HasT2ExtractPack, IsThumb2]>;
+                Requires<[HasDSP, IsThumb2]>;
 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
                   (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
 
 
 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
 // for isel.
 def : t2InstAlias<"mov${p} $Rd, $imm",
                   (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;

lib/Target/ARM/ARMSubtarget.h

   bool HasD16 = false;
 
   /// HasHardwareDivide - True if subtarget supports [su]div
   bool HasHardwareDivide = false;
 
   /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
   bool HasHardwareDivideInARM = false;
 
-  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
-  /// instructions.
-  bool HasT2ExtractPack = false;
-
   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
   /// instructions.
   bool HasDataBarrier = false;
 
   /// HasV7Clrex - True if the subtarget supports CLREX instructions
   bool HasV7Clrex = false;
 
   /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
   /// instructions
   bool HasAcquireRelease = false;
 

   bool hasVirtualization() const { return HasVirtualization; }
 
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP;
   }
 
   bool hasDivide() const { return HasHardwareDivide; }
   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
-  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
   bool hasDataBarrier() const { return HasDataBarrier; }
   bool hasV7Clrex() const { return HasV7Clrex; }
   bool hasAcquireRelease() const { return HasAcquireRelease; }
 
   bool hasAnyDataBarrier() const {
     return HasDataBarrier || (hasV6Ops() && !isThumb());
   }
 

test/CodeGen/Thumb2/thumb2-sxt-uxt.ll

 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m4 %s -o - | FileCheck %s --check-prefix=CHECK-M4
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv7EM
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M-DSP
 
 define i32 @test1(i16 zeroext %z) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK: sxth
   %r = sext i16 %z to i32
   ret i32 %r
 }
 
; CHECK: uxtb
   %r = zext i8 %z to i32
   ret i32 %r
 }
 
 define i32 @test5(i32 %a, i8 %b) {
 ; CHECK-LABEL: test5:
 ; CHECK-NOT: sxtab
 ; CHECK-M4: sxtab r0, r0, r1
+; CHECK-ARMv7EM: sxtab r0, r0, r1
+; CHECK-ARMv8M-DSP: sxtab r0, r0, r1
+; CHECK-ARMv8M-NOT: sxtab r0, r0, r1
   %sext = sext i8 %b to i32
   %add = add i32 %a, %sext
   ret i32 %add
 }
 
 define i32 @test6(i32 %a, i32 %b) {
 ; CHECK-LABEL: test6:
 ; CHECK-NOT: sxtab
 ; CHECK-M4: sxtab r0, r0, r1
+; CHECK-ARMv7EM: sxtab r0, r0, r1
+; CHECK-ARMv8M-DSP: sxtab r0, r0, r1
+; CHECK-ARMv8M-NOT: sxtab r0, r0, r1
   %shl = shl i32 %b, 24
   %ashr = ashr i32 %shl, 24
   %add = add i32 %a, %ashr
   ret i32 %add
 }
 
 define i32 @test7(i32 %a, i16 %b) {
 ; CHECK-LABEL: test7:
 ; CHECK-NOT: sxtah
 ; CHECK-M4: sxtah r0, r0, r1
+; CHECK-ARMv7EM: sxtah r0, r0, r1
+; CHECK-ARMv8M-DSP: sxtah r0, r0, r1
+; CHECK-ARMv8M-NOT: sxtah r0, r0, r1
   %sext = sext i16 %b to i32
   %add = add i32 %a, %sext
   ret i32 %add
 }
 
 define i32 @test8(i32 %a, i32 %b) {
 ; CHECK-LABEL: test8:
 ; CHECK-NOT: sxtah
 ; CHECK-M4: sxtah r0, r0, r1
+; CHECK-ARMv7EM: sxtah r0, r0, r1
+; CHECK-ARMv8M-DSP: sxtah r0, r0, r1
+; CHECK-ARMv8M-NOT: sxtah r0, r0, r1
   %shl = shl i32 %b, 16
   %ashr = ashr i32 %shl, 16
   %add = add i32 %a, %ashr
   ret i32 %add
 }
 
 define i32 @test9(i32 %a, i8 %b) {
 ; CHECK-LABEL: test9:
 ; CHECK-NOT: uxtab
 ; CHECK-M4: uxtab r0, r0, r1
+; CHECK-ARMv7EM: uxtab r0, r0, r1
+; CHECK-ARMv8M-DSP: uxtab r0, r0, r1
+; CHECK-ARMv8M-NOT: uxtab r0, r0, r1
   %zext = zext i8 %b to i32
   %add = add i32 %a, %zext
   ret i32 %add
 }
 
 define i32 @test10(i32 %a, i32 %b) {
 ;CHECK-LABEL: test10:
 ;CHECK-NOT: uxtab
 ;CHECK-M4: uxtab r0, r0, r1
+;CHECK-ARMv7EM: uxtab r0, r0, r1
+;CHECK-ARMv8M-DSP: uxtab r0, r0, r1
+;CHECK-ARMv8M-NOT: uxtab r0, r0, r1
   %and = and i32 %b, 255
   %add = add i32 %a, %and
   ret i32 %add
 }
 
 define i32 @test11(i32 %a, i16 %b) {
 ; CHECK-LABEL: test11:
 ; CHECK-NOT: uxtah
 ; CHECK-M4: uxtah r0, r0, r1
+; CHECK-ARMv7EM: uxtah r0, r0, r1
+; CHECK-ARMv8M-DSP: uxtah r0, r0, r1
+; CHECK-ARMv8M-NOT: uxtah r0, r0, r1
   %zext = zext i16 %b to i32
   %add = add i32 %a, %zext
   ret i32 %add
 }
 
 define i32 @test12(i32 %a, i32 %b) {
 ;CHECK-LABEL: test12:
 ;CHECK-NOT: uxtah
 ;CHECK-M4: uxtah r0, r0, r1
+;CHECK-ARMv7EM: uxtah r0, r0, r1
+;CHECK-ARMv8M-DSP: uxtah r0, r0, r1
+;CHECK-ARMv8M-NOT: uxtah r0, r0, r1
   %and = and i32 %b, 65535
   %add = add i32 %a, %and
   ret i32 %add
 }
 

test/CodeGen/Thumb2/thumb2-sxt_rot.ll

-; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2,+t2xtpk %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-M3
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv7EM
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M-DSP
 
 define i32 @test0(i8 %A) {
 ; CHECK-LABEL: test0:
 ; CHECK: sxtb r0, r0
 ; CHECK-M3: sxtb r0, r0
+; CHECK-ARMv7EM: sxtb r0, r0
+; CHECK-ARMv8M: sxtb r0, r0
+; CHECK-ARMv8M-DSP: sxtb r0, r0
         %B = sext i8 %A to i32
   ret i32 %B
 }
 
 define signext i8 @test1(i32 %A)  {
 ; CHECK-LABEL: test1:
 ; CHECK: sbfx r0, r0, #8, #8
 ; CHECK-M3: sbfx r0, r0, #8, #8
+; CHECK-ARMv7M: sbfx r0, r0, #8, #8
+; CHECK-ARMv8M: sbfx r0, r0, #8, #8
+; CHECK-ARMv8M-DSP: sbfx r0, r0, #8, #8
   %B = lshr i32 %A, 8
   %C = shl i32 %A, 24
   %D = or i32 %B, %C
   %E = trunc i32 %D to i8
   ret i8 %E
 }
 
 define signext i32 @test2(i32 %A, i32 %X)  {
 ; CHECK-LABEL: test2:
 ; CHECK: sxtab  r0, r1, r0, ror #8
+; CHECK-ARMv7EM: sxtab  r0, r1, r0, ror #8
+; CHECK-ARMv8M-DSP: sxtab  r0, r1, r0, ror #8
 ; CHECK-M3-NOT: sxtab
+; CHECK-ARMv8M-NOT: sxtab
   %B = lshr i32 %A, 8
   %C = shl i32 %A, 24
   %D = or i32 %B, %C
   %E = trunc i32 %D to i8
         %F = sext i8 %E to i32
         %G = add i32 %F, %X
   ret i32 %G
 }
 
 define i32 @test3(i32 %A, i32 %X) {
 ; CHECK-LABEL: test3:
 ; CHECK: sxtah r0, r0, r1, ror #8
+; CHECK-ARMv7EM: sxtah  r0, r0, r1, ror #8
+; CHECK-ARMv8M-DSP: sxtah  r0, r0, r1, ror #8
 ; CHECK-M3-NOT: sxtah
+; CHECK-ARMv8M-NOT: sxtah
   %X.hi = lshr i32 %X, 8
   %X.trunc = trunc i32 %X.hi to i16
   %addend = sext i16 %X.trunc to i32
   %sum = add i32 %A, %addend
   ret i32 %sum
 }
 
 define signext i32 @test4(i32 %A, i32 %X)  {
 ; CHECK-LABEL: test4:
 ; CHECK: sxtab  r0, r1, r0, ror #16
+; CHECK-ARMv7EM: sxtab  r0, r1, r0, ror #16
+; CHECK-ARMv8M-DSP: sxtab  r0, r1, r0, ror #16
 ; CHECK-M3-NOT: sxtab
+; CHECK-ARMv8M-NOT: sxtab
   %B = lshr i32 %A, 16
   %C = shl i32 %A, 16
   %D = or i32 %B, %C
   %E = trunc i32 %D to i8
         %F = sext i8 %E to i32
         %G = add i32 %F, %X
   ret i32 %G
 }
 
 define signext i32 @test5(i32 %A, i32 %X)  {
 ; CHECK-LABEL: test5:
 ; CHECK: sxtah  r0, r1, r0, ror #24
+; CHECK-ARMv7EM: sxtah  r0, r1, r0, ror #24
+; CHECK-ARMv8M-DSP: sxtah  r0, r1, r0, ror #24
 ; CHECK-M3-NOT: sxtah
+; CHECK-ARMv8M-NOT: sxtah
   %B = lshr i32 %A, 24
   %C = shl i32 %A, 8
   %D = or i32 %B, %C
   %E = trunc i32 %D to i16
         %F = sext i16 %E to i32
         %G = add i32 %F, %X
   ret i32 %G
 }

test/CodeGen/Thumb2/thumb2-uxt_rot.ll

 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=A8
 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=M3
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=ARMv7EM
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=ARMv8M
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=ARMv8M-DSP
 ; rdar://11318438
 
 define zeroext i8 @test1(i32 %A.u)  {
 ; CHECK-LABEL: test1:
 ; A8: uxtb r0, r0
+; ARMv7EM: uxtb r0, r0
+; ARMv8M: uxtb r0, r0
+; ARMv8M-DSP: uxtb r0, r0
     %B.u = trunc i32 %A.u to i8
     ret i8 %B.u
 }
 
 define zeroext i32 @test2(i32 %A.u, i32 %B.u)  {
 ; CHECK-LABEL: test2:
 ; A8: uxtab  r0, r0, r1
+; ARMv7EM: uxtab  r0, r0, r1
+; ARMv8M-DSP: uxtab  r0, r0, r1
 
 ; M3: uxtb  r1, r1
 ; M3-NOT: uxtab
 ; M3: add   r0, r1
+
+; ARMv8M: uxtb r1, r1
+; ARMv8M-NOT: uxtab  r0, r0, r1
+; ARMv8M: add r0, r1
     %C.u = trunc i32 %B.u to i8
     %D.u = zext i8 %C.u to i32
     %E.u = add i32 %A.u, %D.u
     ret i32 %E.u
 }
 
 define zeroext i32 @test3(i32 %A.u)  {
 ; CHECK-LABEL: test3:
 ; A8: ubfx  r0, r0, #8, #16
 ; M3: ubfx r0, r0, #8, #16
+; ARMv7EM: ubfx r0, r0, #8, #16
+; ARMv8M: ubfx r0, r0, #8, #16
+; ARMv8M-DSP: ubfx r0, r0, #8, #16
     %B.u = lshr i32 %A.u, 8
     %C.u = shl i32 %A.u, 24
     %D.u = or i32 %B.u, %C.u
     %E.u = trunc i32 %D.u to i16
     %F.u = zext i16 %E.u to i32
     ret i32 %F.u
 }
 
 define i32 @test4(i32 %A, i32 %X) {
 ; CHECK-LABEL: test4:
 ; A8: uxtab r0, r0, r1, ror #16
+; ARMv7EM: uxtab r0, r0, r1, ror #16
+; ARMv8M-DSP: uxtab r0, r0, r1, ror #16
 ; M3-NOT: uxtab
+; ARMv8M-NOT: uxtab
   %X.hi = lshr i32 %X, 16
   %X.trunc = trunc i32 %X.hi to i8
   %addend = zext i8 %X.trunc to i32
   %sum = add i32 %A, %addend
   ret i32 %sum
 }
 
 define i32 @test5(i32 %A, i32 %X) {
 ; CHECK-LABEL: test5:
 ; A8: uxtah r0, r0, r1, ror #8
+; ARMv7EM: uxtah r0, r0, r1, ror #8
+; ARMv8M-DSP: uxtah r0, r0, r1, ror #8
 ; M3-NOT: uxtah
+; ARMv8M-NOT: uxtah
   %X.hi = lshr i32 %X, 8
   %X.trunc = trunc i32 %X.hi to i16
   %addend = zext i16 %X.trunc to i32
   %sum = add i32 %A, %addend
   ret i32 %sum
 }
 
 define i32 @test6(i32 %A, i32 %X) {
 ; CHECK-LABEL: test6:
 ; A8: uxtab r0, r0, r1, ror #8
+; ARMv7EM: uxtab r0, r0, r1, ror #8
+; ARMv8M-DSP: uxtab r0, r0, r1, ror #8
 ; M3-NOT: uxtab
+; ARMv8M-NOT: uxtab
   %X.hi = lshr i32 %X, 8
   %X.trunc = trunc i32 %X.hi to i8
   %addend = zext i8 %X.trunc to i32
   %sum = add i32 %A, %addend
   ret i32 %sum
 }
 
 define i32 @test7(i32 %A, i32 %X) {
 ; CHECK-LABEL: test7:
 ; A8: uxtah r0, r0, r1, ror #24
+; ARMv7EM: uxtah r0, r0, r1, ror #24
+; ARMv8M-DSP: uxtah r0, r0, r1, ror #24
 ; M3-NOT: uxtah
+; ARMv8M-NOT: uxtah
   %lshr = lshr i32 %X, 24
   %shl = shl i32 %X, 8
   %or = or i32 %lshr, %shl
   %trunc = trunc i32 %or to i16
   %zext = zext i16 %trunc to i32
   %add = add i32 %A, %zext
   ret i32 %add
 }
 
 define i32 @test8(i32 %A, i32 %X) {
 ; CHECK-LABEL: test8:
 ; A8: uxtah r0, r0, r1, ror #24
+; ARMv7EM: uxtah r0, r0, r1, ror #24
+; ARMv8M-DSP: uxtah r0, r0, r1, ror #24
 ; M3-NOT: uxtah
+; ARMv8M-NOT: uxtah
   %lshr = lshr i32 %X, 24
   %shl = shl i32 %X, 8
   %or = or i32 %lshr, %shl
   %and = and i32 %or, 65535
   %add = add i32 %A, %and
   ret i32 %add
 }

test/CodeGen/Thumb2/thumb2-uxtb.ll

 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=ARMv7A
 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=ARMv7M
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=ARMv7EM
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=ARMv8M
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=ARMv8M-DSP
 
 define i32 @test1(i32 %x) {
-; ARMv7A: test1
+; CHECK-LABEL: test1
 ; ARMv7A: uxtb16 r0, r0
-
-; ARMv7M: test1
 ; ARMv7M: bic r0, r0, #-16711936
+; ARMv7EM: uxtb16 r0, r0
+; ARMv8M-NOT: uxtb16 r0, r0
+; ARMv8M-DSP: uxtb16 r0, r0
   %tmp1 = and i32 %x, 16711935    ; <i32> [#uses=1]
   ret i32 %tmp1
 }
 
 ; PR7503
 define i32 @test2(i32 %x) {
-; ARMv7A: test2
+; CHECK-LABEL: test2
 ; ARMv7A: uxtb16  r0, r0, ror #8
-
-; ARMv7M: test2
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, lsr #8
+; ARMv7EM: uxtb16 r0, r0, ror #8
+; ARMv8M-NOT: uxtb16
+; ARMv8M-DSP: uxtb16 r0, r0, ror #8
   %tmp1 = lshr i32 %x, 8    ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 16711935   ; <i32> [#uses=1]
   ret i32 %tmp2
 }
 
 define i32 @test3(i32 %x) {
-; ARMv7A: test3
+; CHECK-LABEL: test3
 ; ARMv7A: uxtb16  r0, r0, ror #8
-
-; ARMv7M: test3
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, lsr #8
+; ARMv7EM: uxtb16  r0, r0, ror #8
+; ARMv8M-NOT: uxtb16 r0, r0, ror #8
+; ARMv8M-DSP: uxtb16 r0, r0, ror #8
   %tmp1 = lshr i32 %x, 8    ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 16711935   ; <i32> [#uses=1]
   ret i32 %tmp2
 }
 
 define i32 @test4(i32 %x) {
-; ARMv7A: test4
+; CHECK-LABEL: test4
 ; ARMv7A: uxtb16  r0, r0, ror #8
-
-; ARMv7M: test4
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, lsr #8
+; ARMv7EM: uxtb16  r0, r0, ror #8
+; ARMv8M-NOT: uxtb16  r0, r0, ror #8
+; ARMv8M-DSP: uxtb16  r0, r0, ror #8
   %tmp1 = lshr i32 %x, 8    ; <i32> [#uses=1]
   %tmp6 = and i32 %tmp1, 16711935   ; <i32> [#uses=1]
   ret i32 %tmp6
 }
 
 define i32 @test5(i32 %x) {
-; ARMv7A: test5
+; CHECK-LABEL: test5
 ; ARMv7A: uxtb16  r0, r0, ror #8
-
-; ARMv7M: test5
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, lsr #8
+; ARMv7EM: uxtb16  r0, r0, ror #8
+; ARMv8M-NOT: uxtb16  r0, r0, ror #8
+; ARMv8M-DSP: uxtb16  r0, r0, ror #8
   %tmp1 = lshr i32 %x, 8    ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 16711935   ; <i32> [#uses=1]
   ret i32 %tmp2
 }
 
 define i32 @test6(i32 %x) {
-; ARMv7A: test6
+; CHECK-LABEL: test6
 ; ARMv7A: uxtb16  r0, r0, ror #16
-
-; ARMv7M: test6
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, ror #16
+; ARMv7EM: uxtb16  r0, r0, ror #16
+; ARMv8M-NOT: uxtb16  r0, r0, ror #16
+; ARMv8M-DSP: uxtb16  r0, r0, ror #16
   %tmp1 = lshr i32 %x, 16   ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 255    ; <i32> [#uses=1]
   %tmp4 = shl i32 %x, 16    ; <i32> [#uses=1]
   %tmp5 = and i32 %tmp4, 16711680   ; <i32> [#uses=1]
   %tmp6 = or i32 %tmp2, %tmp5   ; <i32> [#uses=1]
   ret i32 %tmp6
 }
 
 define i32 @test7(i32 %x) {
-; ARMv7A: test7
+; CHECK-LABEL: test7
 ; ARMv7A: uxtb16  r0, r0, ror #16
-
-; ARMv7M: test7
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, ror #16
+; ARMv7EM: uxtb16  r0, r0, ror #16
+; ARMv8M-NOT: uxtb16  r0, r0, ror #16
+; ARMv8M-DSP: uxtb16  r0, r0, ror #16
   %tmp1 = lshr i32 %x, 16   ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 255    ; <i32> [#uses=1]
   %tmp4 = shl i32 %x, 16    ; <i32> [#uses=1]
   %tmp5 = and i32 %tmp4, 16711680   ; <i32> [#uses=1]
   %tmp6 = or i32 %tmp2, %tmp5   ; <i32> [#uses=1]
   ret i32 %tmp6
 }
 
 define i32 @test8(i32 %x) {
-; ARMv7A: test8
+; CHECK-LABEL: test8
 ; ARMv7A: uxtb16  r0, r0, ror #24
-
-; ARMv7M: test8
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, ror #24
+; ARMv7EM: uxtb16  r0, r0, ror #24
+; ARMv8M-NOT: uxtb16  r0, r0, ror #24
+; ARMv8M-DSP: uxtb16  r0, r0, ror #24
   %tmp1 = shl i32 %x, 8   ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 16711680   ; <i32> [#uses=1]
   %tmp5 = lshr i32 %x, 24   ; <i32> [#uses=1]
   %tmp6 = or i32 %tmp2, %tmp5   ; <i32> [#uses=1]
   ret i32 %tmp6
 }
 
 define i32 @test9(i32 %x) {
-; ARMv7A: test9
+; CHECK-LABEL: test9
 ; ARMv7A: uxtb16  r0, r0, ror #24
-
-; ARMv7M: test9
 ; ARMv7M: mov.w r1, #16711935
 ; ARMv7M: and.w r0, r1, r0, ror #24
+; ARMv7EM: uxtb16  r0, r0, ror #24
+; ARMv8M-NOT: uxtb16  r0, r0, ror #24
+; ARMv8M-DSP: uxtb16  r0, r0, ror #24
   %tmp1 = lshr i32 %x, 24   ; <i32> [#uses=1]
   %tmp4 = shl i32 %x, 8   ; <i32> [#uses=1]
   %tmp5 = and i32 %tmp4, 16711680   ; <i32> [#uses=1]
   %tmp6 = or i32 %tmp5, %tmp1   ; <i32> [#uses=1]
   ret i32 %tmp6
 }
 
 define i32 @test10(i32 %p0) {
-; ARMv7A: test10
+; CHECK-LABEL: test10
 ; ARMv7A: mov.w r1, #16253176
 ; ARMv7A: and.w r0, r1, r0, lsr #7
 ; ARMv7A: lsrs  r1, r0, #5
 ; ARMv7A: uxtb16  r1, r1
 ; ARMv7A: orrs r0, r1
 
-; ARMv7M: test10
 ; ARMv7M: mov.w r1, #16253176
 ; ARMv7M: and.w r0, r1, r0, lsr #7
 ; ARMv7M: mov.w r1, #458759
 ; ARMv7M: and.w r1, r1, r0, lsr #5
 ; ARMv7M: orrs r0, r1
   %tmp1 = lshr i32 %p0, 7   ; <i32> [#uses=1]
   %tmp2 = and i32 %tmp1, 16253176   ; <i32> [#uses=2]
   %tmp4 = lshr i32 %tmp2, 5   ; <i32> [#uses=1]
   %tmp5 = and i32 %tmp4, 458759   ; <i32> [#uses=1]
   %tmp7 = or i32 %tmp5, %tmp2   ; <i32> [#uses=1]
   ret i32 %tmp7
 }