[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)

[deadalnix]

Summary

This is extracted from D29443 .

[RKSimon]

LGTM with one style minor

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1840

clang-format this

[zvi]

test/CodeGen/X86/adde-carry.ll

89

If you intend to improve this test case in future patches, i think you should add a dedicated minimal test to ensure the combine introduced this patch will be covered. Other than that LGTM

[deadalnix]

test/CodeGen/X86/adde-carry.ll

89

I don't think that's a problem. The add case is always the bottom turtle.

[deadalnix]

clang-format

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
     VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
     if (TN->getVT() == MVT::i1) {
       SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
                                  DAG.getConstant(1, DL, VT));
       return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
     }
   }
 
+  // (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)
+  if (N1.getOpcode() == ISD::ADDE && N1->hasOneUse() &&
+      isNullConstant(N1.getOperand(1)))
+    return DAG.getNode(ISD::ADDE, DL, DAG.getVTList(VT, MVT::Glue),
+                       N0, N1->getOperand(0), N1->getOperand(2));
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitADDC(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N0.getValueType();
 

test/CodeGen/X86/adde-carry.ll

  %5 = add i128 %4, %2
  %6 = trunc i128 %5 to i8
  store i8 %6, i8* %r, align 4
  ret void
 }
 
 %scalar = type { [4 x i64] }
 
 define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) {
 ; CHECK-LABEL: pr31719:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq (%rsi), %rdx
 ; CHECK-NEXT:    sbbq %r10, %r10
 ; CHECK-NEXT:    andl $1, %r10d
 ; CHECK-NEXT:    addq 8(%rsi), %rcx
-; CHECK-NEXT:    sbbq %r11, %r11
-; CHECK-NEXT:    andl $1, %r11d
-; CHECK-NEXT:    addq %r10, %rcx
-; CHECK-NEXT:    adcq $0, %r11
-; CHECK-NEXT:    addq 16(%rsi), %r8
 ; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    andl $1, %eax
-; CHECK-NEXT:    addq %r11, %r8
+; CHECK-NEXT:    addq %r10, %rcx
 ; CHECK-NEXT:    adcq $0, %rax
+; CHECK-NEXT:    addq 16(%rsi), %r8
+; CHECK-NEXT:    sbbq %r10, %r10
+; CHECK-NEXT:    andl $1, %r10d
 ; CHECK-NEXT:    addq 24(%rsi), %r9
-; CHECK-NEXT:    addq %rax, %r9
+; CHECK-NEXT:    addq %rax, %r8
+; CHECK-NEXT:    adcq %r10, %r9
 ; CHECK-NEXT:    movq %rdx, (%rdi)
 ; CHECK-NEXT:    movq %rcx, 8(%rdi)
 ; CHECK-NEXT:    movq %r8, 16(%rdi)
 ; CHECK-NEXT:    movq %r9, 24(%rdi)
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %0 = extractvalue %scalar %arg.b, 0