[DAGCombiner] Push truncate through adde when the carry isn't used.

[deadalnix]

Summary

As per title.

[arsenm]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7781 ↗

(On Diff #87064)

Extra whitespace change

7870–7872 ↗

(On Diff #87064)

Needs a legality check for the resulting adde?

[deadalnix]

Check for adde's validity before combining.

[arsenm]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7874 ↗

(On Diff #87092)

Usually this is done as !LegalizeDAG || TLI.isOperationLegal..

7875 ↗

(On Diff #87092)

SDLoc SL(N)

test/CodeGen/X86/adde-carry.ll

109–110 ↗

(On Diff #87092)

Can you add tests with more types?

[deadalnix]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7874 ↗

(On Diff #87092)

There is no wrapper for this ?

[deadalnix]

Add test cases for various sizes.
Use SDLoc SL(N) .

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7872 ↗

(On Diff #87119)

clang-format

[deadalnix]

Rebase, clang-format

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7876 ↗

(On Diff #87232)

This should probably be (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT)) - otherwise you might get into trouble if custom lowering results in the truncate being regenerated.

7879 ↗

(On Diff #87232)

Typically we don't use auto for these cases - just use SDvalue

[deadalnix]

Use (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT))

[arsenm]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
     }
   }
 
   // Simplify the operands using demanded-bits information.
   if (!VT.isVector() &&
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
+  // (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
+  // When the adde's carry is not used.
+  if (N0.getOpcode() == ISD::ADDE && N0.hasOneUse() &&
+      !N0.getNode()->hasAnyUseOfValue(1) &&
+      (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT))) {
+    SDLoc SL(N);
+    auto X = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
+    auto Y = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
+    return DAG.getNode(ISD::ADDE, SL, DAG.getVTList(VT, MVT::Glue),
+                       X, Y, N0.getOperand(2));
+  }
+
   return SDValue();
 }
 
 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
   SDValue Elt = N->getOperand(i);
   if (Elt.getOpcode() != ISD::MERGE_VALUES)
     return Elt.getNode();
   return Elt.getOperand(Elt.getResNo()).getNode();

llvm/trunk/test/CodeGen/X86/adde-carry.ll

  store i64 %8, i64* %t, align 8
  ret void
 }
 
 define void @b(i32* nocapture %r, i64 %a, i64 %b, i32 %c) nounwind {
 ; CHECK-LABEL: b:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rsi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    adcl $0, %ecx
 ; CHECK-NEXT:    movl %ecx, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
  %0 = zext i64 %a to i128
  %1 = zext i64 %b to i128
  %2 = zext i32 %c to i128
  %3 = add i128 %1, %0
  %4 = lshr i128 %3, 64
  %5 = add i128 %4, %2
  %6 = trunc i128 %5 to i32
  store i32 %6, i32* %r, align 4
  ret void
 }
 
 define void @c(i16* nocapture %r, i64 %a, i64 %b, i16 %c) nounwind {
 ; CHECK-LABEL: c:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rsi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    adcl $0, %ecx
 ; CHECK-NEXT:    movw %cx, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
  %0 = zext i64 %a to i128
  %1 = zext i64 %b to i128
  %2 = zext i16 %c to i128
  %3 = add i128 %1, %0
  %4 = lshr i128 %3, 64
  %5 = add i128 %4, %2
  %6 = trunc i128 %5 to i16
  store i16 %6, i16* %r, align 4
  ret void
 }
 
 define void @d(i8* nocapture %r, i64 %a, i64 %b, i8 %c) nounwind {
 ; CHECK-LABEL: d:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addq %rdx, %rsi
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    adcl $0, %ecx
 ; CHECK-NEXT:    movb %cl, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
  %0 = zext i64 %a to i128
  %1 = zext i64 %b to i128
  %2 = zext i8 %c to i128
  %3 = add i128 %1, %0
  %4 = lshr i128 %3, 64

 ; CHECK-LABEL: muladd:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    movq %rdx, %rax
 ; CHECK-NEXT:    mulq %rsi
 ; CHECK-NEXT:    addq (%rdi), %rax
 ; CHECK-NEXT:    adcq $0, %rdx
 ; CHECK-NEXT:    movq %rax, (%rdi)
 ; CHECK-NEXT:    addq 8(%rdi), %rdx
-; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    sbbl %eax, %eax
 ; CHECK-NEXT:    subl %eax, 16(%rdi)
 ; CHECK-NEXT:    retq
 entry:
   %0 = zext i64 %arg.a to i128
   %1 = zext i64 %arg.b to i128
   %2 = mul nuw i128 %1, %0
   %3 = getelementptr inbounds %accumulator, %accumulator* %this, i64 0, i32 0
   %4 = load i64, i64* %3, align 8

llvm/trunk/test/CodeGen/X86/known-bits.ll

 ; X32-NEXT:    popl %edi
 ; X32-NEXT:    retl $4
 ;
 ; X64-LABEL: knownbits_mask_addc_shl:
 ; X64:       # BB#0:
 ; X64-NEXT:    andq $-1024, %rdi # imm = 0xFC00
 ; X64-NEXT:    andq $-1024, %rsi # imm = 0xFC00
 ; X64-NEXT:    addq %rdi, %rsi
-; X64-NEXT:    sbbq %rax, %rax
-; X64-NEXT:    subl %eax, %edx
+; X64-NEXT:    adcl $0, %edx
 ; X64-NEXT:    shldq $54, %rsi, %rdx
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %1 = and i64 %a0, -1024
   %2 = zext i64 %1 to i128
   %3 = and i64 %a1, -1024
   %4 = zext i64 %3 to i128
   %5 = add i128 %2, %4
   %6 = zext i64 %a2 to i128
   %7 = shl i128 %6, 64
   %8 = add i128 %5, %7
   %9 = shl i128 %8, 54
   ret i128 %9
 }