[DAGCombiner] Push truncate through adde when the carry isn't used.

[deadalnix]

Summary

As per title.

[arsenm]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7781

Extra whitespace change

7871–7873

Needs a legality check for the resulting adde?

[deadalnix]

Check for adde's validity before combining.

[arsenm]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7874

Usually this is done as !LegalizeDAG || TLI.isOperationLegal..

7875

SDLoc SL(N)

test/CodeGen/X86/adde-carry.ll

109–110

Can you add tests with more types?

[deadalnix]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7874

There is no wrapper for this ?

[deadalnix]

Add test cases for various sizes.
Use SDLoc SL(N) .

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7872

clang-format

[deadalnix]

Rebase, clang-format

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7873

This should probably be (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT)) - otherwise you might get into trouble if custom lowering results in the truncate being regenerated.

7876

Typically we don't use auto for these cases - just use SDvalue

[deadalnix]

Use (!LegalOperations || TLI.isOperationLegal(ISD::ADDE, VT))

[arsenm]

LGTM

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
   // Currently we only perform this optimization on scalars because vectors
   // may have different active low bits.
   if (!VT.isVector()) {
     if (SDValue Shorter =
             GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
                                                      VT.getSizeInBits())))
       return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
   }
 
   // fold (truncate (load x)) -> (smaller load x)
   // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
   if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
     if (SDValue Reduced = ReduceLoadWidth(N))
       return Reduced;
 
     // Handle the case where the load remains an extending load even
     // after truncation.
if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
     }
   }
 
   // Simplify the operands using demanded-bits information.
   if (!VT.isVector() &&
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
+  // (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
+  // When the adde's carry is not used.
+  if (N0.getOpcode() == ISD::ADDE &&
+      N0.hasOneUse() &&
+      !N0.getNode()->hasAnyUseOfValue(1) &&
+      TLI.isOperationLegalOrCustom(ISD::ADDE, VT)) {
+    auto SL = SDLoc(N);
+    auto C1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
+    auto C2 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
+    return DAG.getNode(ISD::ADDE, SL, DAG.getVTList(VT, MVT::Glue),
+                       C1, C2, N0.getOperand(2));
+  }
+
   return SDValue();
 }
 
 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
   SDValue Elt = N->getOperand(i);
   if (Elt.getOpcode() != ISD::MERGE_VALUES)
     return Elt.getNode();
   return Elt.getOperand(Elt.getResNo()).getNode();

test/CodeGen/X86/adde-carry.ll

 ; CHECK-LABEL: muladd:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    movq %rdx, %rax
 ; CHECK-NEXT:    mulq %rsi
 ; CHECK-NEXT:    addq (%rdi), %rax
 ; CHECK-NEXT:    adcq $0, %rdx
 ; CHECK-NEXT:    movq %rax, (%rdi)
 ; CHECK-NEXT:    addq 8(%rdi), %rdx
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    addl %eax, 16(%rdi)
 ; CHECK-NEXT:    retq
 entry:
   %0 = zext i64 %arg.a to i128
   %1 = zext i64 %arg.b to i128
   %2 = mul nuw i128 %1, %0
   %3 = getelementptr inbounds %accumulator, %accumulator* %this, i64 0, i32 0
   %4 = load i64, i64* %3, align 8