[ARM] Classification Improvements to ARM Sched-Model. NFCI.

[javed.absar]

Summary

This is the second one in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions.

[rengolin]

Hi Javed,

Awesome work, thanks!

Adding Tim, as you touch some of the Swift stuff.

Does that make some of the scheduler to be "complete"? If so, we should also update:

let CompleteModel = 1;

So that it gets validated from now on.

cheers,
--renato

[javed.absar]

Hi Renato:
Thanks for the feedback.
We can't set CompleteModel just yet, but we are getting there. We need add missing schedule information some more instructions (notably Thumb2, VLD/VST)

Best Regards
Javed

[rovka]

lib/Target/ARM/ARMInstrInfo.td

4079

I see you're modelling IIC_iMUL16 the same as IIC_iMUL32, but they don't seem to be exactly identical in any of the models (A9, A8, V6). Same for IIC_iMAC16.

test/CodeGen/ARM/misched-int-basic.ll

41

Can you also add a test for 64-bit mac?

[javed.absar]

Hi Diana:
I have made the changes you mentioned.
Best Regards
Javed

[rovka]

Hi Javed,

I'm not sure if it's you or Phab, but I'm only seeing the changes between the first patch and the current one (not between trunk and the current one). You might want to try to upload again with all the changes included.

test/CodeGen/ARM/misched-int-basic.ll

1

Nitpick: Why this is an IR test and not an MIR test?

49

This looks a bit contrived, is there any reason why you don't use mul i16 %c, %c to get a smulbb?

[javed.absar]

Hi Diana:
As requested, I have simplified the test (removed the contrived way of generating SMULBB), added test for SMLABB. Also, converted the test to MIR test.
Thanks and Best Regards
Javed

[rovka]

Thanks, Javed. LGTM now.

lib/Target/ARM/ARMInstrInfo.td

def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
              Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
 
 multiclass AI_smul<string opc> {
   def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
               IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
               [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16),
                                       (sext_inreg GPR:$Rm, i16)))]>,
            Requires<[IsARM, HasV5TE]>,
-           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+           Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
 
   def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
               IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
               [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16),
                                       (sra GPR:$Rm, (i32 16))))]>,
            Requires<[IsARM, HasV5TE]>,
-           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+           Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
 
   def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
               IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
               [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)),
                                       (sext_inreg GPR:$Rm, i16)))]>,
            Requires<[IsARM, HasV5TE]>,
-           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+           Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
 
   def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
               IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
               [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)),
                                       (sra GPR:$Rm, (i32 16))))]>,
             Requires<[IsARM, HasV5TE]>,
-           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+           Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
 
   def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
               IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
               []>,
            Requires<[IsARM, HasV5TE]>,
-           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+           Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
 
   def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
               IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
               []>,
             Requires<[IsARM, HasV5TE]>,
-           Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+           Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
 }
 
 
 multiclass AI_smla<string opc> {
   let DecoderMethod = "DecodeSMLAInstruction" in {
   def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
               (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
               IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set GPRnopc:$Rd, (add GPR:$Ra,
                                (mul (sext_inreg GPRnopc:$Rn, i16),
                                        (sext_inreg GPRnopc:$Rm, i16))))]>,
            Requires<[IsARM, HasV5TE, UseMulOps]>,
-           Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
+           Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
 
   def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
               (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
               IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set GPRnopc:$Rd,
                     (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16),
                                           (sra GPRnopc:$Rm, (i32 16)))))]>,
            Requires<[IsARM, HasV5TE, UseMulOps]>,
-           Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
+           Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
 
   def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
               (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
               IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set GPRnopc:$Rd,
                     (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)),
                                           (sext_inreg GPRnopc:$Rm, i16))))]>,
            Requires<[IsARM, HasV5TE, UseMulOps]>,
-           Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
+           Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
 
   def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
               (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
               IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
              [(set GPRnopc:$Rd,
                    (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)),
                                          (sra GPRnopc:$Rm, (i32 16)))))]>,
             Requires<[IsARM, HasV5TE, UseMulOps]>,
-            Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
+            Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
 
   def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
               (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
               IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
               []>,
            Requires<[IsARM, HasV5TE, UseMulOps]>,
-           Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
+           Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
 
   def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
               (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
               IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
               []>,
            Requires<[IsARM, HasV5TE, UseMulOps]>,
-           Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
+           Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
   }
 }
 
 defm SMUL : AI_smul<"smul">;
 defm SMLA : AI_smla<"smla">;
 
 // Halfword multiply accumulate long: SMLAL<x><y>.
 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),

lib/Target/ARM/ARMSchedule.td

 def ReadALUsr : SchedRead; // Some operands are read later.
 
 // Compares.
 def WriteCMP : SchedWrite;
 def WriteCMPsi : SchedWrite;
 def WriteCMPsr : SchedWrite;
 
 // Multiplys.
-def WriteMUL32   : SchedWrite; // 32-bit result
+def WriteMUL16   : SchedWrite; // 16-bit multiply.
+def WriteMUL32   : SchedWrite; // 32-bit multiply.
 def WriteMUL64Lo : SchedWrite; // 64-bit result. Low reg.
 def WriteMUL64Hi : SchedWrite; // 64-bit result. High reg.
 def ReadMUL  : SchedRead;
 
 // Multiply-accumulates.
-def WriteMAC32   : SchedWrite; // 32-bit result
-def WriteMAC64Lo : SchedWrite; // 64-bit result. Low reg.
-def WriteMAC64Hi : SchedWrite; // 64-bit result. High reg.
+def WriteMAC16   : SchedWrite; // 16-bit mac.
+def WriteMAC32   : SchedWrite; // 32-bit mac.
+def WriteMAC64Lo : SchedWrite; // 64-bit mac. Low reg.
+def WriteMAC64Hi : SchedWrite; // 64-bit mac. High reg.
 def ReadMAC : SchedRead;
 
 // Divisions.
 def WriteDIV : SchedWrite;
 
 // Loads.
 def WriteLd : SchedWrite;
 def WritePreLd : SchedWrite;

lib/Target/ARM/ARMScheduleA9.td

 
 // Multiplication
 def A9WriteM   : SchedWriteRes<[A9UnitMul, A9UnitMul]> { let Latency = 4; }
 def A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5;
                                               let NumMicroOps = 0; }
 def A9WriteM16   : SchedWriteRes<[A9UnitMul]> { let Latency = 3; }
 def A9WriteM16Hi : SchedWriteRes<[A9UnitMul]> { let Latency = 4;
                                                 let NumMicroOps = 0; }
+def : SchedAlias<WriteMUL16, A9WriteM16>;
 def : SchedAlias<WriteMUL32, A9WriteM>;
 def : SchedAlias<WriteMUL64Lo, A9WriteM>;
 def : SchedAlias<WriteMUL64Hi, A9WriteMHi>;
+def : SchedAlias<WriteMAC16, A9WriteM16>;
 def : SchedAlias<WriteMAC32, A9WriteM>;
 def : SchedAlias<WriteMAC64Lo, A9WriteM>;
 def : SchedAlias<WriteMAC64Hi, A9WriteMHi>;
 def : ReadAdvance<ReadMUL, 0>;
 def : ReadAdvance<ReadMAC, 0>;
 
 // Floating-point
 // Only one FP or AGU instruction may issue per cycle. We model this

lib/Target/ARM/ARMScheduleR52.td

 def R52WriteALU_EX1    : SchedWriteRes<[R52UnitALU]> { let Latency = 2; }
 def R52WriteALU_EX2    : SchedWriteRes<[R52UnitALU]> { let Latency = 3; }
 def R52WriteALU_WRI    : SchedWriteRes<[R52UnitALU]> { let Latency = 4; }
 
 def R52WriteNoRSRC_EX2 : SchedWriteRes<[]> { let Latency = 3; }
 def R52WriteNoRSRC_WRI : SchedWriteRes<[]> { let Latency = 4; }
 
 // Alias generics to sub-target specific
+def : SchedAlias<WriteMUL16, R52WriteMAC>;
 def : SchedAlias<WriteMUL32, R52WriteMAC>;
 def : SchedAlias<WriteMUL64Lo, R52WriteMAC>;
 def : SchedAlias<WriteMUL64Hi, R52WriteMACHi>;
+def : SchedAlias<WriteMAC16, R52WriteMAC>;
 def : SchedAlias<WriteMAC32, R52WriteMAC>;
 def : SchedAlias<WriteMAC64Lo, R52WriteMAC>;
 def : SchedAlias<WriteMAC64Hi, R52WriteMACHi>;
 
 def R52WriteFPALU_F3   : SchedWriteRes<[R52UnitFPALU]> { let Latency = 4; }
 def R52Write2FPALU_F3  : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> {
   let Latency = 4;
 }

lib/Target/ARM/ARMScheduleSwift.td

let SchedModel = SwiftModel in {
 
   def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
     let Latency = 7;
     let NumMicroOps = 5;
     let ResourceCycles = [2, 3];
   }
 
   // Aliasing sub-target specific WriteRes to generic ones
+  def : SchedAlias<WriteMUL16, SwiftWriteP0FourCycle>;
   def : SchedAlias<WriteMUL32, SwiftWriteP0FourCycle>;
   def : SchedAlias<WriteMUL64Lo, SwiftP0P0P01FiveCycle>;
   def : SchedAlias<WriteMUL64Hi, SwiftWrite5Cycle>;
+  def : SchedAlias<WriteMAC16, SwiftPredP0P01FourFiveCycle>;
   def : SchedAlias<WriteMAC32, SwiftPredP0P01FourFiveCycle>;
   def : SchedAlias<WriteMAC64Lo, SwiftWrite5Cycle>;
   def : SchedAlias<WriteMAC64Hi, Swift2P03P01FiveCycle>;
   def : ReadAdvance<ReadMUL, 0>;
   def : SchedAlias<ReadMAC, SwiftReadAdvanceFourCyclesPred>;
 
   // 4.2.15 Integer Multiply Accumulate, Long
   // 4.2.16 Integer Multiply Accumulate, Dual

test/CodeGen/ARM/misched-int-basic.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
 ; RUN:   /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
 ; RUN:   /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
 ; RUN:   /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
 ;
 ; Check the latency of basic int instructions for processors with sched-models
 ;
 ; Function Attrs: norecurse nounwind readnone
-define i64 @foo(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {
+define i64 @foo(i32 %a, i32 %b, i16 signext %c) local_unnamed_addr #0 {
 entry:
 ;
 ; CHECK:       ********** MI Scheduling **********
 ; CHECK:       ADDrr
 ; CHECK_A9:    Latency    : 1
 ; CHECK_SWIFT: Latency    : 1
 ; CHECK_R52:   Latency    : 3
 ;
+; CHECK:       SMULBB
+; CHECK_A9:    Latency    : 2
+; CHECK_SWIFT: Latency    : 4
+; CHECK_R52:   Latency    : 4
+;
 ; CHECK:       MUL
 ; CHECK_SWIFT: Latency    : 4
 ; CHECK_A9:    Latency    : 2
 ; CHECK_R52:   Latency    : 4
 ;
 ; CHECK:       MLA
 ; CHECK_SWIFT: Latency    : 4
 ; CHECK_A9:    Latency    : 2
 ; CHECK_R52:   Latency    : 4
 ;
 ; CHECK:       SMULL
 ; CHECK_SWIFT: Latency    : 5
 ; CHECK_A9:    Latency    : 3
 ; CHECK_R52:   Latency    : 4
 ;
+; CHECK:       SMLAL
+; CHECK_SWIFT: Latency    : 7
+; CHECK_A9:    Latency    : 3
+; CHECK_R52:   Latency    : 4
+;
   %add = add nsw i32 %b, %a
-  %mul = mul nsw i32 %add, %c
+  %tmp = trunc i32 %add to i16
+  %convc = sext i16 %tmp to i32
+  %mul0 = mul nsw i32 %convc, %convc
+  %mul = mul nsw i32 %add, %mul0
   %mul1 = mul nsw i32 %mul, %mul
   %add2 = add nsw i32 %mul1, %mul
   %conv = sext i32 %add2 to i64
   %mul3 = mul nsw i64 %conv, %conv
-  ret i64 %mul3
+  %mul4 = mul nsw i64 %mul3, %mul3
+  %add3  = add nsw i64 %mul4, %mul3
+  ret i64 %add3
 }