SPARC: allow usage of floating-point registers in inline ASM

[pboettch]

Summary

Make clang recognize floating point registers in inline assembler
when using the targeting Sparc.

This code now works:

static inline float fabsf(float a)
{

float res;
__asm __volatile__("fabss  %1, %0;"
                   : "=f"(res)
                   : "f"(a));
return res;

}

[pboettch]

Added test-code.

[bruno]

Hi,

Thanks for working on this. Few questions:

• What happens with the validation if +soft-float is used?
• What about the 'e' mode, can you double check if the sparc backend support these instructions? If so it might be interesting to add it here.

Also, please attach patches with full context, it's easier to review.

[pboettch]

On SparcV8 there is no %e register.

Regarding soft-float, good question, I'll try.

How do I create full-context-patches? Does this mean just more context lines? Like 500 or 1000 lines?

[sdardis]

How do I create full-context-patches? Does this mean just more context lines? Like 500 or 1000 lines?

http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

lib/Basic/Targets.cpp

     case 'N': // Same as 'K' but zext (required for SIMode)
     case 'O': // The constant 4096
       return true;
+
+    case 'f':
+      info.setAllowsRegister();
+      return true;
     }
     return false;
   }

test/CodeGen/sparcv8-inline-asm.c

+// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define float @fabsf(float %a) #0 {
+// CHECK: %2 = call float asm sideeffect "fabss  $1, $0;", "=f,f"(float %1) #1
+float fabsf(float a) {
+  float res;
+  __asm __volatile__("fabss  %1, %0;"
+                     : /* reg out*/ "=f"(res)
+                     : /* reg in */ "f"(a));
+  return res;
+}